Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/87688/?format=api
{ "id": 87688, "url": "http://patches.dpdk.org/api/patches/87688/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1612355037-48768-8-git-send-email-oulijun@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1612355037-48768-8-git-send-email-oulijun@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1612355037-48768-8-git-send-email-oulijun@huawei.com", "date": "2021-02-03T12:23:53", "name": "[07/11] net/hns3: replace all atomic type with C11 atomic builtins", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "368f5b8da2185e90f3202383626b3b5a58ce3f02", "submitter": { "id": 1675, "url": "http://patches.dpdk.org/api/people/1675/?format=api", "name": "Lijun Ou", "email": "oulijun@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1612355037-48768-8-git-send-email-oulijun@huawei.com/mbox/", "series": [ { "id": 15123, "url": "http://patches.dpdk.org/api/series/15123/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15123", "date": "2021-02-03T12:23:47", "name": "critical bugfixes for hns3", "version": 1, "mbox": "http://patches.dpdk.org/series/15123/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/87688/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/87688/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2E7B3A0A0E;\n\tWed, 3 Feb 2021 13:25:54 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E86C1240585;\n\tWed, 3 Feb 2021 13:24:40 +0100 (CET)", "from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32])\n by mails.dpdk.org (Postfix) with ESMTP id B629E240549\n for <dev@dpdk.org>; Wed, 3 Feb 2021 13:24:30 +0100 (CET)", "from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DW1710NqzzjHJB;\n Wed, 3 Feb 2021 20:23:25 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id\n 14.3.498.0; Wed, 3 Feb 2021 20:24:23 +0800" ], "From": "Lijun Ou <oulijun@huawei.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <linuxarm@openeuler.org>", "Date": "Wed, 3 Feb 2021 20:23:53 +0800", "Message-ID": "<1612355037-48768-8-git-send-email-oulijun@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1612355037-48768-1-git-send-email-oulijun@huawei.com>", "References": "<1612355037-48768-1-git-send-email-oulijun@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 07/11] net/hns3: replace all atomic type with C11\n atomic builtins", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chengchang Tang <tangchengchang@huawei.com>\n\nReplace all the atomic type with C11 atomic builtins in hns3\nPMD.\n\nSigned-off-by: Chengchang Tang <tangchengchang@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.c | 13 +++++++------\n drivers/net/hns3/hns3_ethdev.c | 21 ++++++++++++---------\n drivers/net/hns3/hns3_ethdev.h | 4 ++--\n drivers/net/hns3/hns3_ethdev_vf.c | 19 +++++++++++--------\n drivers/net/hns3/hns3_intr.c | 22 ++++++++++++++--------\n drivers/net/hns3/hns3_mbx.c | 4 ++--\n 6 files changed, 48 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nindex b750022..3d6ffc0 100644\n--- a/drivers/net/hns3/hns3_cmd.c\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -202,7 +202,8 @@ hns3_cmd_csq_clean(struct hns3_hw *hw)\n \t\thns3_err(hw, \"wrong cmd head (%u, %u-%u)\", head,\n \t\t\t csq->next_to_use, csq->next_to_clean);\n \t\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\t\t__atomic_store_n(&hw->reset.disable_cmd, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t\thns3_schedule_delayed_reset(HNS3_DEV_HW_TO_ADAPTER(hw));\n \t\t}\n \n@@ -311,7 +312,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \t\tif (hns3_cmd_csq_done(hw))\n \t\t\treturn 0;\n \n-\t\tif (rte_atomic16_read(&hw->reset.disable_cmd)) {\n+\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n \t\t\thns3_err(hw,\n \t\t\t\t \"Don't wait for reply because of disable_cmd\");\n \t\t\treturn -EBUSY;\n@@ -358,7 +359,7 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)\n \tint retval;\n \tuint32_t ntc;\n \n-\tif (rte_atomic16_read(&hw->reset.disable_cmd))\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))\n \t\treturn -EBUSY;\n \n \trte_spinlock_lock(&hw->cmq.csq.lock);\n@@ -535,7 +536,7 @@ hns3_cmd_init(struct hns3_hw *hw)\n \t\tret = -EBUSY;\n \t\tgoto err_cmd_init;\n \t}\n-\trte_atomic16_clear(&hw->reset.disable_cmd);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);\n \n \tret = hns3_cmd_query_firmware_version_and_capability(hw);\n \tif (ret) {\n@@ -557,7 +558,7 @@ hns3_cmd_init(struct hns3_hw *hw)\n \treturn 0;\n \n err_cmd_init:\n-\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \treturn ret;\n }\n \n@@ -583,7 +584,7 @@ hns3_cmd_uninit(struct hns3_hw *hw)\n {\n \trte_spinlock_lock(&hw->cmq.csq.lock);\n \trte_spinlock_lock(&hw->cmq.crq.lock);\n-\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \thns3_cmd_clear_regs(hw);\n \trte_spinlock_unlock(&hw->cmq.crq.lock);\n \trte_spinlock_unlock(&hw->cmq.csq.lock);\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex c0ab3fc..a7ae8f8 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -130,7 +130,7 @@ hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);\n \tif (!is_delay) {\n@@ -150,7 +150,7 @@ hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);\n \tif (!is_delay) {\n@@ -5070,7 +5070,7 @@ hns3_do_stop(struct hns3_adapter *hns)\n \t\treturn ret;\n \thw->mac.link_status = ETH_LINK_DOWN;\n \n-\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {\n \t\thns3_configure_all_mac_addr(hns, true);\n \t\tret = hns3_reset_all_tqps(hns);\n \t\tif (ret) {\n@@ -5613,7 +5613,7 @@ hns3_prepare_reset(struct hns3_adapter *hns)\n \t\t * any mailbox handling or command to firmware is only valid\n \t\t * after hns3_cmd_init is called.\n \t\t */\n-\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \t\thw->reset.stats.request_cnt++;\n \t\tbreak;\n \tcase HNS3_IMP_RESET:\n@@ -5673,7 +5673,7 @@ hns3_stop_service(struct hns3_adapter *hns)\n \t * from table space. Hence, for function reset software intervention is\n \t * required to delete the entries\n \t */\n-\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0)\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)\n \t\thns3_configure_all_mc_mac_addr(hns, true);\n \trte_spinlock_unlock(&hw->lock);\n \n@@ -5795,8 +5795,10 @@ hns3_reset_service(void *param)\n \t * The interrupt may have been lost. It is necessary to handle\n \t * the interrupt to recover from the error.\n \t */\n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {\n-\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\t SCHEDULE_DEFERRED) {\n+\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n \t\thns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n \t\treset_level = hns3_get_reset_level(hns, &hw->reset.pending);\n@@ -5805,7 +5807,7 @@ hns3_reset_service(void *param)\n \t\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t\t}\n \t}\n-\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);\n+\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);\n \n \t/*\n \t * Check if there is any ongoing reset in the hardware. This status can\n@@ -6325,7 +6327,8 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)\n \n \thw->adapter_state = HNS3_NIC_INITIALIZED;\n \n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\t SCHEDULE_PENDING) {\n \t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n \t\thns3_schedule_reset(hns);\n \t} else {\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex e72f3e1..4c535ea 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -352,11 +352,11 @@ enum hns3_schedule {\n \n struct hns3_reset_data {\n \tenum hns3_reset_stage stage;\n-\trte_atomic16_t schedule;\n+\tuint16_t schedule;\n \t/* Reset flag, covering the entire reset process */\n \tuint16_t resetting;\n \t/* Used to disable sending cmds during reset */\n-\trte_atomic16_t disable_cmd;\n+\tuint16_t disable_cmd;\n \t/* The reset level being processed */\n \tenum hns3_reset_level level;\n \t/* Reset level set, each bit represents a reset level */\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 2446574..4f9da4a 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -1059,7 +1059,7 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \t\trst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n \t\thns3_warn(hw, \"resetting reg: 0x%x\", rst_ing_reg);\n \t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n-\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \t\tval = hns3_read_dev(hw, HNS3_VF_RST_ING);\n \t\thns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);\n \t\tval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);\n@@ -1934,7 +1934,7 @@ hns3vf_do_stop(struct hns3_adapter *hns)\n \n \thw->mac.link_status = ETH_LINK_DOWN;\n \n-\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {\n \t\thns3vf_configure_mac_addr(hns, true);\n \t\tret = hns3_reset_all_tqps(hns);\n \t\tif (ret) {\n@@ -2410,7 +2410,7 @@ hns3vf_prepare_reset(struct hns3_adapter *hns)\n \t\tret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,\n \t\t\t\t\t0, true, NULL, 0);\n \t}\n-\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n \n \treturn ret;\n }\n@@ -2449,7 +2449,7 @@ hns3vf_stop_service(struct hns3_adapter *hns)\n \t * from table space. Hence, for function reset software intervention is\n \t * required to delete the entries.\n \t */\n-\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0)\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)\n \t\thns3vf_configure_all_mc_mac_addr(hns, true);\n \trte_spinlock_unlock(&hw->lock);\n \n@@ -2621,8 +2621,10 @@ hns3vf_reset_service(void *param)\n \t * The interrupt may have been lost. It is necessary to handle\n \t * the interrupt to recover from the error.\n \t */\n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {\n-\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\t SCHEDULE_DEFERRED) {\n+\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n \t\thns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n \t\treset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);\n@@ -2631,7 +2633,7 @@ hns3vf_reset_service(void *param)\n \t\t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n \t\t}\n \t}\n-\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);\n+\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);\n \n \t/*\n \t * Hardware reset has been notified, we now have to poll & check if\n@@ -2854,7 +2856,8 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n \n \thw->adapter_state = HNS3_NIC_INITIALIZED;\n \n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\t SCHEDULE_PENDING) {\n \t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n \t\thns3_schedule_reset(hns);\n \t} else {\ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex 51f19b4..88ce4c6 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -1762,7 +1762,7 @@ hns3_reset_init(struct hns3_hw *hw)\n \thw->reset.request = 0;\n \thw->reset.pending = 0;\n \thw->reset.resetting = 0;\n-\trte_atomic16_init(&hw->reset.disable_cmd);\n+\t__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);\n \thw->reset.wait_data = rte_zmalloc(\"wait_data\",\n \t\t\t\t\t sizeof(struct hns3_wait_data), 0);\n \tif (!hw->reset.wait_data) {\n@@ -1779,7 +1779,8 @@ hns3_schedule_reset(struct hns3_adapter *hns)\n \n \t/* Reschedule the reset process after successful initialization */\n \tif (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {\n-\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);\n+\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\treturn;\n \t}\n \n@@ -1787,11 +1788,14 @@ hns3_schedule_reset(struct hns3_adapter *hns)\n \t\treturn;\n \n \t/* Schedule restart alarm if it is not scheduled yet */\n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\tSCHEDULE_REQUESTED)\n \t\treturn;\n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\t\t\tSCHEDULE_DEFERRED)\n \t\trte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);\n-\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t __ATOMIC_RELAXED);\n \n \trte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);\n }\n@@ -1808,9 +1812,11 @@ hns3_schedule_delayed_reset(struct hns3_adapter *hns)\n \t\treturn;\n \t}\n \n-\tif (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)\n+\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=\n+\t\t\t SCHEDULE_NONE)\n \t\treturn;\n-\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);\n+\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,\n+\t\t\t __ATOMIC_RELAXED);\n \trte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);\n }\n \n@@ -1983,7 +1989,7 @@ hns3_reset_err_handle(struct hns3_adapter *hns)\n \t * Regardless of whether the execution is successful or not, the\n \t * flow after execution must be continued.\n \t */\n-\tif (rte_atomic16_read(&hw->reset.disable_cmd))\n+\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))\n \t\t(void)hns3_cmd_init(hw);\n reset_fail:\n \thw->reset.attempts = 0;\ndiff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c\nindex 925cfca..61d1584 100644\n--- a/drivers/net/hns3/hns3_mbx.c\n+++ b/drivers/net/hns3/hns3_mbx.c\n@@ -83,7 +83,7 @@ hns3_get_mbx_resp(struct hns3_hw *hw, uint16_t code0, uint16_t code1,\n \tend = now + HNS3_MAX_RETRY_MS;\n \twhile ((hw->mbx_resp.head != hw->mbx_resp.tail + hw->mbx_resp.lost) &&\n \t (now < end)) {\n-\t\tif (rte_atomic16_read(&hw->reset.disable_cmd)) {\n+\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n \t\t\thns3_err(hw, \"Don't wait for mbx respone because of \"\n \t\t\t\t \"disable_cmd\");\n \t\t\treturn -EBUSY;\n@@ -369,7 +369,7 @@ hns3_dev_handle_mbx_msg(struct hns3_hw *hw)\n \tint i;\n \n \twhile (!hns3_cmd_crq_empty(hw)) {\n-\t\tif (rte_atomic16_read(&hw->reset.disable_cmd))\n+\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))\n \t\t\treturn;\n \n \t\tdesc = &crq->desc[crq->next_to_use];\n", "prefixes": [ "07/11" ] }