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GET /api/patches/8718/?format=api
{ "id": 8718, "url": "http://patches.dpdk.org/api/patches/8718/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446741498-3096-9-git-send-email-jerin.jacob@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446741498-3096-9-git-send-email-jerin.jacob@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446741498-3096-9-git-send-email-jerin.jacob@caviumnetworks.com", "date": "2015-11-05T16:38:11", "name": "[dpdk-dev,08/15] acl: arm64: acl implementation using NEON gcc intrinsic", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "850caae6a7378dfab025709a7dde972d9221df33", "submitter": { "id": 305, "url": "http://patches.dpdk.org/api/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446741498-3096-9-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8718/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8718/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 09EC891B8;\n\tThu, 5 Nov 2015 17:39:44 +0100 (CET)", "from na01-bn1-obe.outbound.protection.outlook.com\n\t(mail-bn1on0078.outbound.protection.outlook.com [157.56.110.78])\n\tby dpdk.org (Postfix) with ESMTP id 9D27691C1\n\tfor <dev@dpdk.org>; Thu, 5 Nov 2015 17:39:41 +0100 (CET)", "from jerin.caveonetworks.com (111.93.218.67) by\n\tCY1PR0701MB1977.namprd07.prod.outlook.com (10.163.141.19) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.1.312.18; Thu, 5 Nov 2015 16:39:38 +0000" ], "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Jerin.Jacob@caviumnetworks.com; ", "From": "Jerin Jacob <jerin.jacob@caviumnetworks.com>", "To": "<dev@dpdk.org>", "Date": "Thu, 5 Nov 2015 22:08:11 +0530", "Message-ID": "<1446741498-3096-9-git-send-email-jerin.jacob@caviumnetworks.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1446741498-3096-8-git-send-email-jerin.jacob@caviumnetworks.com>", "References": "<1446741498-3096-1-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-2-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-3-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-4-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-5-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-6-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-7-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1446741498-3096-8-git-send-email-jerin.jacob@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": "MA1PR01CA0067.INDPRD01.PROD.OUTLOOK.COM (25.164.116.167)\n\tTo\n\tCY1PR0701MB1977.namprd07.prod.outlook.com (25.163.141.19)", "X-Microsoft-Exchange-Diagnostics": [ "1; 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CY1PR0701MB1977;\n\t5:L3ooiCqxXpS8f/9gbgIzgF8yg8wn3UdMGJ+bnO5N6kd84cQ4F6K3OqKlzrjF0I3p3Y4Rc995uMP/P5ccMHkoKMWEJ46/OpmdyJskQcAPSOBC5wHAVetF10pNwBDLk1Tryp666KqMXCAdkLhO+VDUhQ==;\n\t24:Mo8Ublv2yGmOmLh2VhSmXDNGrupTtlE8d64eoNg74alsamYObEezVwyOeVL2R+J6b4+qSnUYE854IR4stE+2wsup3DDgSWW528eKIlJgcng=;\n\t20:Mvj81TfmAiz4yRkKXpYIcwB53t17LOui4MGVgZOfjqaQhHszr24R6OCMkfQCYgCM7A6QL//ZlgGpuu20HTO02g==" ], "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0701MB1977;", "X-Microsoft-Antispam-PRVS": "<CY1PR0701MB1977A9F6FC12C48D1D86BD7E8C290@CY1PR0701MB1977.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(236414709691187);", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(2401047)(520078)(5005006)(8121501046)(3002001)(10201501046);\n\tSRVR:CY1PR0701MB1977; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0701MB1977; ", "X-Forefront-PRVS": "0751474A44", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6009001)(189002)(199003)(5007970100001)(86362001)(5001960100002)(107886002)(36756003)(122386002)(40100003)(189998001)(42186005)(5008740100001)(575784001)(87976001)(110136002)(97736004)(66066001)(101416001)(92566002)(2950100001)(5009440100003)(4001430100002)(19580405001)(76176999)(5003940100001)(50986999)(50226001)(50466002)(106356001)(77096005)(105586002)(5004730100002)(2351001)(81156007)(229853001)(48376002)(33646002)(19580395003)(69596002)(53416004)(93886004)(47776003)(7099028);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR0701MB1977;\n\tH:jerin.caveonetworks.com; \n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: caviumnetworks.com does not\n\tdesignate permitted sender hosts)", "SpamDiagnosticOutput": "1:23", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Nov 2015 16:39:38.3201\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0701MB1977", "Subject": "[dpdk-dev] [PATCH 08/15] acl: arm64: acl implementation using NEON\n\tgcc intrinsic", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "verified with testacl and acl_autotest applications on arm64 architecture.\n\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n app/test-acl/main.c | 4 +\n lib/librte_acl/Makefile | 5 +\n lib/librte_acl/acl.h | 4 +\n lib/librte_acl/acl_run_neon.c | 46 +++++++\n lib/librte_acl/acl_run_neon.h | 289 ++++++++++++++++++++++++++++++++++++++++++\n lib/librte_acl/rte_acl.c | 25 ++++\n lib/librte_acl/rte_acl.h | 1 +\n 7 files changed, 374 insertions(+)\n create mode 100644 lib/librte_acl/acl_run_neon.c\n create mode 100644 lib/librte_acl/acl_run_neon.h", "diff": "diff --git a/app/test-acl/main.c b/app/test-acl/main.c\nindex 72ce83c..0b0c093 100644\n--- a/app/test-acl/main.c\n+++ b/app/test-acl/main.c\n@@ -101,6 +101,10 @@ static const struct acl_alg acl_alg[] = {\n \t\t.name = \"avx2\",\n \t\t.alg = RTE_ACL_CLASSIFY_AVX2,\n \t},\n+\t{\n+\t\t.name = \"neon\",\n+\t\t.alg = RTE_ACL_CLASSIFY_NEON,\n+\t},\n };\n \n static struct {\ndiff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile\nindex 7a1cf8a..27f91d5 100644\n--- a/lib/librte_acl/Makefile\n+++ b/lib/librte_acl/Makefile\n@@ -48,9 +48,14 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += rte_acl.c\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_bld.c\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_gen.c\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c\n+ifeq ($(CONFIG_RTE_ARCH_ARM64),y)\n+SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c\n+else\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c\n+endif\n \n CFLAGS_acl_run_sse.o += -msse4.1\n+CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized\n \n #\n # If the compiler supports AVX2 instructions,\ndiff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h\nindex eb4930c..09d6784 100644\n--- a/lib/librte_acl/acl.h\n+++ b/lib/librte_acl/acl.h\n@@ -230,6 +230,10 @@ int\n rte_acl_classify_avx2(const struct rte_acl_ctx *ctx, const uint8_t **data,\n \tuint32_t *results, uint32_t num, uint32_t categories);\n \n+int\n+rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\tuint32_t *results, uint32_t num, uint32_t categories);\n+\n #ifdef __cplusplus\n }\n #endif /* __cplusplus */\ndiff --git a/lib/librte_acl/acl_run_neon.c b/lib/librte_acl/acl_run_neon.c\nnew file mode 100644\nindex 0000000..b014451\n--- /dev/null\n+++ b/lib/librte_acl/acl_run_neon.c\n@@ -0,0 +1,46 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) Cavium networks Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Cavium networks nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include \"acl_run_neon.h\"\n+\n+int\n+rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\t\t uint32_t *results, uint32_t num, uint32_t categories)\n+{\n+\tif (likely(num >= 8))\n+\t\treturn search_neon_8(ctx, data, results, num, categories);\n+\telse if (num >= 4)\n+\t\treturn search_neon_4(ctx, data, results, num, categories);\n+\telse\n+\t\treturn rte_acl_classify_scalar(ctx, data, results, num,\n+\t\t\tcategories);\n+}\ndiff --git a/lib/librte_acl/acl_run_neon.h b/lib/librte_acl/acl_run_neon.h\nnew file mode 100644\nindex 0000000..cf7c57f\n--- /dev/null\n+++ b/lib/librte_acl/acl_run_neon.h\n@@ -0,0 +1,289 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) Cavium networks Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Cavium networks nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include \"acl_run.h\"\n+#include \"acl_vect.h\"\n+\n+struct _neon_acl_const {\n+\trte_xmm_t xmm_shuffle_input;\n+\trte_xmm_t xmm_index_mask;\n+\trte_xmm_t range_base;\n+} neon_acl_const __attribute__((aligned(RTE_CACHE_LINE_SIZE))) = {\n+\t{\n+\t\t.u32 = {0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c}\n+\t},\n+\t{\n+\t\t.u32 = {RTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX,\n+\t\tRTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX}\n+\t},\n+\t{\n+\t\t.u32 = {0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c}\n+\t},\n+};\n+\n+/*\n+ * Resolve priority for multiple results (neon version).\n+ * This consists comparing the priority of the current traversal with the\n+ * running set of results for the packet.\n+ * For each result, keep a running array of the result (rule number) and\n+ * its priority for each category.\n+ */\n+static inline void\n+resolve_priority_neon(uint64_t transition, int n, const struct rte_acl_ctx *ctx,\n+\t\t struct parms *parms,\n+\t\t const struct rte_acl_match_results *p,\n+\t\t uint32_t categories)\n+{\n+\tuint32_t x;\n+\tint32x4_t results, priority, results1, priority1;\n+\tuint32x4_t selector;\n+\tint32_t *saved_results, *saved_priority;\n+\n+\tfor (x = 0; x < categories; x += RTE_ACL_RESULTS_MULTIPLIER) {\n+\t\tsaved_results = (int32_t *)(&parms[n].cmplt->results[x]);\n+\t\tsaved_priority = (int32_t *)(&parms[n].cmplt->priority[x]);\n+\n+\t\t/* get results and priorities for completed trie */\n+\t\tresults = vld1q_s32(\n+\t\t\t(const int32_t *)&p[transition].results[x]);\n+\t\tpriority = vld1q_s32(\n+\t\t\t(const int32_t *)&p[transition].priority[x]);\n+\n+\t\t/* if this is not the first completed trie */\n+\t\tif (parms[n].cmplt->count != ctx->num_tries) {\n+\t\t\t/* get running best results and their priorities */\n+\t\t\tresults1 = vld1q_s32(saved_results);\n+\t\t\tpriority1 = vld1q_s32(saved_priority);\n+\n+\t\t\t/* select results that are highest priority */\n+\t\t\tselector = vcgtq_s32(priority1, priority);\n+\t\t\tresults = vbslq_s32(selector, results1, results);\n+\t\t\tpriority = vbslq_s32(selector, priority1, priority);\n+\t\t}\n+\n+\t\t/* save running best results and their priorities */\n+\t\tvst1q_s32(saved_results, results);\n+\t\tvst1q_s32(saved_priority, priority);\n+\t}\n+}\n+\n+/*\n+ * Check for any match in 4 transitions\n+ */\n+static inline __attribute__((always_inline)) uint32_t\n+check_any_match_x4(uint64_t val[])\n+{\n+\treturn ((val[0] | val[1] | val[2] | val[3]) & RTE_ACL_NODE_MATCH);\n+}\n+\n+static inline __attribute__((always_inline)) void\n+acl_match_check_x4(int slot, const struct rte_acl_ctx *ctx, struct parms *parms,\n+\t\t struct acl_flow_data *flows, uint64_t transitions[])\n+{\n+\twhile (check_any_match_x4(transitions)) {\n+\t\ttransitions[0] = acl_match_check(transitions[0], slot, ctx,\n+\t\t\tparms, flows, resolve_priority_neon);\n+\t\ttransitions[1] = acl_match_check(transitions[1], slot + 1, ctx,\n+\t\t\tparms, flows, resolve_priority_neon);\n+\t\ttransitions[2] = acl_match_check(transitions[2], slot + 2, ctx,\n+\t\t\tparms, flows, resolve_priority_neon);\n+\t\ttransitions[3] = acl_match_check(transitions[3], slot + 3, ctx,\n+\t\t\tparms, flows, resolve_priority_neon);\n+\t}\n+}\n+\n+/*\n+ * Process 4 transitions (in 2 NEON Q registers) in parallel\n+ */\n+static inline __attribute__((always_inline)) int32x4_t\n+transition4(int32x4_t next_input, const uint64_t *trans, uint64_t transitions[])\n+{\n+\tint32x4x2_t tr_hi_lo;\n+\tint32x4_t t, in, r;\n+\tuint32x4_t index_msk, node_type, addr;\n+\tuint32x4_t dfa_msk, mask, quad_ofs, dfa_ofs;\n+\n+\t/* Move low 32 into tr_hi_lo.val[0] and high 32 into tr_hi_lo.val[1] */\n+\ttr_hi_lo = vld2q_s32((const int32_t *)transitions);\n+\n+\t/* Calculate the address (array index) for all 4 transitions. */\n+\n+\tindex_msk = vld1q_u32((const uint32_t *)&neon_acl_const.xmm_index_mask);\n+\n+\t/* Calc node type and node addr */\n+\tnode_type = vbicq_s32(tr_hi_lo.val[0], index_msk);\n+\taddr = vandq_s32(tr_hi_lo.val[0], index_msk);\n+\n+\t/* t = 0 */\n+\tt = veorq_s32(node_type, node_type);\n+\n+\t/* mask for DFA type(0) nodes */\n+\tdfa_msk = vceqq_u32(node_type, t);\n+\n+\tmask = vld1q_s32((const int32_t *)&neon_acl_const.xmm_shuffle_input);\n+\tin = vqtbl1q_u8((uint8x16_t)next_input, (uint8x16_t)mask);\n+\n+\t/* DFA calculations. */\n+\tr = vshrq_n_u32(in, 30); /* div by 64 */\n+\tmask = vld1q_s32((const int32_t *)&neon_acl_const.range_base);\n+\tr = vaddq_u8(r, mask);\n+\tt = vshrq_n_u32(in, 24);\n+\tr = vqtbl1q_u8((uint8x16_t)tr_hi_lo.val[1], (uint8x16_t)r);\n+\tdfa_ofs = vsubq_s32(t, r);\n+\n+\t/* QUAD/SINGLE calculations. */\n+\tt = vcgtq_s8(in, tr_hi_lo.val[1]);\n+\tt = vabsq_s8(t);\n+\tt = vpaddlq_u8(t);\n+\tquad_ofs = vpaddlq_u16(t);\n+\n+\t/* blend DFA and QUAD/SINGLE. */\n+\tt = vbslq_u8(dfa_msk, dfa_ofs, quad_ofs);\n+\n+\t/* calculate address for next transitions */\n+\taddr = vaddq_u32(addr, t);\n+\n+\t/* Fill next transitions */\n+\ttransitions[0] = trans[vgetq_lane_u32(addr, 0)];\n+\ttransitions[1] = trans[vgetq_lane_u32(addr, 1)];\n+\ttransitions[2] = trans[vgetq_lane_u32(addr, 2)];\n+\ttransitions[3] = trans[vgetq_lane_u32(addr, 3)];\n+\n+\treturn vshrq_n_u32(next_input, CHAR_BIT);\n+}\n+\n+/*\n+ * Execute trie traversal with 8 traversals in parallel\n+ */\n+static inline int\n+search_neon_8(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\t uint32_t *results, uint32_t total_packets, uint32_t categories)\n+{\n+\tint n;\n+\tstruct acl_flow_data flows;\n+\tuint64_t index_array[8];\n+\tstruct completion cmplt[8];\n+\tstruct parms parms[8];\n+\tint32x4_t input0, input1;\n+\n+\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,\n+\t\t total_packets, categories, ctx->trans_table);\n+\n+\tfor (n = 0; n < 8; n++) {\n+\t\tcmplt[n].count = 0;\n+\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n+\t}\n+\n+\t /* Check for any matches. */\n+\tacl_match_check_x4(0, ctx, parms, &flows, &index_array[0]);\n+\tacl_match_check_x4(4, ctx, parms, &flows, &index_array[4]);\n+\n+\twhile (flows.started > 0) {\n+\t\t/* Gather 4 bytes of input data for each stream. */\n+\t\tinput0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), input0, 0);\n+\t\tinput1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 4), input1, 0);\n+\n+\t\tinput0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input0, 1);\n+\t\tinput1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 5), input1, 1);\n+\n+\t\tinput0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 2), input0, 2);\n+\t\tinput1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 6), input1, 2);\n+\n+\t\tinput0 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 3), input0, 3);\n+\t\tinput1 = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 7), input1, 3);\n+\n+\t\t/* Process the 4 bytes of input on each stream. */\n+\n+\t\tinput0 = transition4(input0, flows.trans, &index_array[0]);\n+\t\tinput1 = transition4(input1, flows.trans, &index_array[4]);\n+\n+\t\tinput0 = transition4(input0, flows.trans, &index_array[0]);\n+\t\tinput1 = transition4(input1, flows.trans, &index_array[4]);\n+\n+\t\tinput0 = transition4(input0, flows.trans, &index_array[0]);\n+\t\tinput1 = transition4(input1, flows.trans, &index_array[4]);\n+\n+\t\tinput0 = transition4(input0, flows.trans, &index_array[0]);\n+\t\tinput1 = transition4(input1, flows.trans, &index_array[4]);\n+\n+\t\t /* Check for any matches. */\n+\t\tacl_match_check_x4(0, ctx, parms, &flows, &index_array[0]);\n+\t\tacl_match_check_x4(4, ctx, parms, &flows, &index_array[4]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Execute trie traversal with 4 traversals in parallel\n+ */\n+static inline int\n+search_neon_4(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\t uint32_t *results, int total_packets, uint32_t categories)\n+{\n+\tint n;\n+\tstruct acl_flow_data flows;\n+\tuint64_t index_array[4];\n+\tstruct completion cmplt[4];\n+\tstruct parms parms[4];\n+\tint32x4_t input;\n+\n+\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,\n+\t\t total_packets, categories, ctx->trans_table);\n+\n+\tfor (n = 0; n < 4; n++) {\n+\t\tcmplt[n].count = 0;\n+\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n+\t}\n+\n+\t/* Check for any matches. */\n+\tacl_match_check_x4(0, ctx, parms, &flows, index_array);\n+\n+\twhile (flows.started > 0) {\n+\t\t/* Gather 4 bytes of input data for each stream. */\n+\t\tinput = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 0), input, 0);\n+\t\tinput = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 1), input, 1);\n+\t\tinput = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 2), input, 2);\n+\t\tinput = vsetq_lane_s32(GET_NEXT_4BYTES(parms, 3), input, 3);\n+\n+\t\t/* Process the 4 bytes of input on each stream. */\n+\t\tinput = transition4(input, flows.trans, index_array);\n+\t\tinput = transition4(input, flows.trans, index_array);\n+\t\tinput = transition4(input, flows.trans, index_array);\n+\t\tinput = transition4(input, flows.trans, index_array);\n+\n+\t\t/* Check for any matches. */\n+\t\tacl_match_check_x4(0, ctx, parms, &flows, index_array);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex d60219f..e2fdebd 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -55,11 +55,32 @@ rte_acl_classify_avx2(__rte_unused const struct rte_acl_ctx *ctx,\n \treturn -ENOTSUP;\n }\n \n+int __attribute__ ((weak))\n+rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx,\n+\t__rte_unused const uint8_t **data,\n+\t__rte_unused uint32_t *results,\n+\t__rte_unused uint32_t num,\n+\t__rte_unused uint32_t categories)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n+int __attribute__ ((weak))\n+rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx,\n+\t__rte_unused const uint8_t **data,\n+\t__rte_unused uint32_t *results,\n+\t__rte_unused uint32_t num,\n+\t__rte_unused uint32_t categories)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n static const rte_acl_classify_t classify_fns[] = {\n \t[RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,\n \t[RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,\n \t[RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,\n \t[RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,\n+\t[RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,\n };\n \n /* by default, use always available scalar code path. */\n@@ -93,6 +114,9 @@ rte_acl_init(void)\n {\n \tenum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;\n \n+#ifdef RTE_ARCH_ARM64\n+\talg = RTE_ACL_CLASSIFY_NEON;\n+#else\n #ifdef CC_AVX2_SUPPORT\n \tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n \t\talg = RTE_ACL_CLASSIFY_AVX2;\n@@ -102,6 +126,7 @@ rte_acl_init(void)\n #endif\n \t\talg = RTE_ACL_CLASSIFY_SSE;\n \n+#endif\n \trte_acl_set_default_classify(alg);\n }\n \ndiff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h\nindex 98ef2fc..0979a09 100644\n--- a/lib/librte_acl/rte_acl.h\n+++ b/lib/librte_acl/rte_acl.h\n@@ -270,6 +270,7 @@ enum rte_acl_classify_alg {\n \tRTE_ACL_CLASSIFY_SCALAR = 1, /**< generic implementation. */\n \tRTE_ACL_CLASSIFY_SSE = 2, /**< requires SSE4.1 support. */\n \tRTE_ACL_CLASSIFY_AVX2 = 3, /**< requires AVX2 support. */\n+\tRTE_ACL_CLASSIFY_NEON = 4, /**< requires NEON support. */\n \tRTE_ACL_CLASSIFY_NUM /* should always be the last one. */\n };\n \n", "prefixes": [ "dpdk-dev", "08/15" ] }