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GET /api/patches/87154/?format=api
{ "id": 87154, "url": "http://patches.dpdk.org/api/patches/87154/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1611486126-84749-3-git-send-email-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1611486126-84749-3-git-send-email-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1611486126-84749-3-git-send-email-suanmingm@nvidia.com", "date": "2021-01-24T11:02:04", "name": "[2/4] net/mlx5: fix secondary process port detach crash", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e96981d2dceda212b92c210147fdde53ca18cf0c", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1611486126-84749-3-git-send-email-suanmingm@nvidia.com/mbox/", "series": [ { "id": 14914, "url": "http://patches.dpdk.org/api/series/14914/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14914", "date": "2021-01-24T11:02:04", "name": "net/mlx: fix secondary process bugs", "version": 1, "mbox": "http://patches.dpdk.org/series/14914/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/87154/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/87154/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AC6F5A052A;\n\tSun, 24 Jan 2021 12:02:19 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EAC97140D8E;\n\tSun, 24 Jan 2021 12:02:18 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id A39EA140D73\n for <dev@dpdk.org>; Sun, 24 Jan 2021 12:02:16 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:15 +0200", "from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ7003937;\n Sun, 24 Jan 2021 13:02:14 +0200" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "viacheslavo@nvidia.com, matan@nvidia.com", "Cc": "rasland@nvidia.com, dev@dpdk.org, stable@dpdk.org", "Date": "Sun, 24 Jan 2021 19:02:04 +0800", "Message-Id": "<1611486126-84749-3-git-send-email-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1611486126-84749-1-git-send-email-suanmingm@nvidia.com>", "References": "<1611486126-84749-1-git-send-email-suanmingm@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 2/4] net/mlx5: fix secondary process port detach\n crash", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When secondary process starts, in rte_eth_dev_attach_secondary()\nfunction, the secondary process port device data in struct rte_eth_dev\nwill be initialized to be shared with primary process port.\n\nWhen failsafe sub-port hot-plug happens, both primary and secondary\nprocess will release the sub-port, and primary process will clear the\nsub-port device data in fs_dev_remove() deactivate stage first before\nrequest secondary process to release the sub-port. In this case, the\nsecondary process will not be able to get the priv memory pointer from\nthe shared device data memory anymore, since the device data memory\nhas been cleared.\n\nSince what secondary process needs in port detach is the UAR table size\nto unmap the UAR addresses. It used Tx queue number as size of UAR table\nin priv. In fact the uar_table_sz in struct mlx5_proc_priv means the size\nof UAR register table - the number of UAR records. However, the code set\nthis field incorrectly to the size of mlx5_proc_priv structure.\n\nThis commit fixes UAR table size to match with relevant Tx queue number,\nuses the UAR table size directly to avoid the secondary process to access\nthe priv pointer in the shared device data memory when unmapping the UAR\naddress.\n\nFixes: 120dc4a7dcd3 (\"net/mlx5: remove device register remap\")\ncc: stable@dpdk.org\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 6 +++---\n drivers/net/mlx5/mlx5_txq.c | 21 +++++++++++++--------\n 2 files changed, 16 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 3730f32..efedbb9 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1251,13 +1251,13 @@ struct mlx5_dev_ctx_shared *\n \t */\n \tppriv_size =\n \t\tsizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);\n-\tppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,\n-\t\t\t dev->device->numa_node);\n+\tppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,\n+\t\t\t RTE_CACHE_LINE_SIZE, dev->device->numa_node);\n \tif (!ppriv) {\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tppriv->uar_table_sz = ppriv_size;\n+\tppriv->uar_table_sz = priv->txqs_n;\n \tdev->process_private = ppriv;\n \treturn 0;\n }\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex b81bb4a..c53af10 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -634,18 +634,23 @@\n void\n mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_txq_data *txq;\n-\tstruct mlx5_txq_ctrl *txq_ctrl;\n+\tstruct mlx5_proc_priv *ppriv = (struct mlx5_proc_priv *)\n+\t\t\t\t\tdev->process_private;\n+\tconst size_t page_size = rte_mem_page_size();\n+\tvoid *addr;\n \tunsigned int i;\n \n+\tif (page_size == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n+\t\treturn;\n+\t}\n \tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n-\tfor (i = 0; i != priv->txqs_n; ++i) {\n-\t\tif (!(*priv->txqs)[i])\n+\tfor (i = 0; i != ppriv->uar_table_sz; ++i) {\n+\t\tif (!ppriv->uar_table[i])\n \t\t\tcontinue;\n-\t\ttxq = (*priv->txqs)[i];\n-\t\ttxq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);\n-\t\ttxq_uar_uninit_secondary(txq_ctrl);\n+\t\taddr = ppriv->uar_table[i];\n+\t\trte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);\n+\n \t}\n }\n \n", "prefixes": [ "2/4" ] }