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GET /api/patches/86535/?format=api
{ "id": 86535, "url": "http://patches.dpdk.org/api/patches/86535/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210114070743.2377-7-shirik@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210114070743.2377-7-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210114070743.2377-7-shirik@nvidia.com", "date": "2021-01-14T07:07:40", "name": "[v6,6/9] net/mlx5: create GENEVE TLV option management", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "ffa7ed739484b3eb3523dcb3dcd49f4292f90279", "submitter": { "id": 1894, "url": "http://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210114070743.2377-7-shirik@nvidia.com/mbox/", "series": [ { "id": 14717, "url": "http://patches.dpdk.org/api/series/14717/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14717", "date": "2021-01-14T07:07:34", "name": "ethdev: introduce GENEVE header TLV option item", "version": 6, "mbox": "http://patches.dpdk.org/series/14717/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86535/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86535/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A036A0A02;\n\tThu, 14 Jan 2021 08:09:25 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0E383140F24;\n\tThu, 14 Jan 2021 08:08:59 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id EEA09140F20\n for <dev@dpdk.org>; Thu, 14 Jan 2021 08:08:56 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 14 Jan 2021 09:08:52 +0200", "from nvidia.com (c-141-140-1-007.mtl.labs.mlnx [10.141.140.7])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10E78GjJ013095;\n Thu, 14 Jan 2021 09:08:52 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com,\n andrew.rybchenko@oktetlabs.ru", "Date": "Thu, 14 Jan 2021 09:07:40 +0200", "Message-Id": "<20210114070743.2377-7-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20210114070743.2377-1-shirik@nvidia.com>", "References": "<20210112140241.15914-1-shirik@nvidia.com>\n <20210114070743.2377-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v6 6/9] net/mlx5: create GENEVE TLV option\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently firmware supports the only TLV object per device\nto match on the GENEVE header option.\n\nThis patch adds the simple TLV object management to the mlx5 PMD.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 2 +\n drivers/net/mlx5/mlx5.h | 13 ++++\n drivers/net/mlx5/mlx5_flow.h | 5 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 108 ++++++++++++++++++++++++++++++++\n 4 files changed, 128 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e245276fce..3730f32295 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1008,6 +1008,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \trte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);\n \t/* Add context to the global device list. */\n \tLIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);\n+\trte_spinlock_init(&sh->geneve_tlv_opt_sl);\n exit:\n \tpthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);\n \treturn sh;\n@@ -1106,6 +1107,7 @@ mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)\n \t\tmlx5_glue->devx_free_uar(sh->devx_rx_uar);\n \tif (sh->ctx)\n \t\tclaim_zero(mlx5_glue->close_device(sh->ctx));\n+\tMLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);\n \tpthread_mutex_destroy(&sh->txpp.mutex);\n \tmlx5_free(sh);\n \treturn;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 3836a9696c..101e9c20d0 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -528,6 +528,16 @@ struct mlx5_aso_age_mng {\n \tstruct mlx5_aso_sq aso_sq; /* ASO queue objects. */\n };\n \n+/* Management structure for geneve tlv option */\n+struct mlx5_geneve_tlv_option_resource {\n+\tstruct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */\n+\trte_be16_t option_class; /* geneve tlv opt class.*/\n+\tuint8_t option_type; /* geneve tlv opt type.*/\n+\tuint8_t length; /* geneve tlv opt length. */\n+\tuint32_t refcnt; /* geneve tlv object reference counter */\n+};\n+\n+\n #define MLX5_AGE_EVENT_NEW\t\t1\n #define MLX5_AGE_TRIGGER\t\t2\n #define MLX5_AGE_SET(age_info, BIT) \\\n@@ -727,6 +737,9 @@ struct mlx5_dev_ctx_shared {\n \tvoid *devx_rx_uar; /* DevX UAR for Rx. */\n \tstruct mlx5_aso_age_mng *aso_age_mng;\n \t/* Management data for aging mechanism using ASO Flow Hit. */\n+\tstruct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;\n+\t/* Management structure for geneve tlv option */\n+\trte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 329082a48b..3d6ba9f610 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1046,6 +1046,7 @@ struct rte_flow {\n \tuint32_t counter; /**< Holds flow counter. */\n \tuint32_t tunnel_id; /**< Tunnel id */\n \tuint32_t age; /**< Holds ASO age bit index. */\n+\tuint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */\n } __rte_packed;\n \n /*\n@@ -1503,6 +1504,9 @@ void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,\n \t\t\t\t struct mlx5_cache_entry *entry);\n struct mlx5_aso_age_action *flow_aso_age_get_by_idx(struct rte_eth_dev *dev,\n \t\t\t\t\t\t uint32_t age_idx);\n+int flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n+\t\t\t\t\t const struct rte_flow_item *item,\n+\t\t\t\t\t struct rte_flow_error *error);\n \n void flow_release_workspace(void *data);\n int mlx5_flow_os_init_workspace_once(void);\n@@ -1510,4 +1514,5 @@ void *mlx5_flow_os_get_specific_workspace(void);\n int mlx5_flow_os_set_specific_workspace(struct mlx5_flow_workspace *data);\n void mlx5_flow_os_release_workspace(void);\n \n+\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex e4736ee9b5..0a657cea41 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7244,6 +7244,90 @@ flow_dv_translate_item_geneve(void *matcher, void *key,\n \t\t MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));\n }\n \n+/**\n+ * Create Geneve TLV option resource.\n+ *\n+ * @param dev[in, out]\n+ * Pointer to rte_eth_dev structure.\n+ * @param[in, out] tag_be24\n+ * Tag value in big endian then R-shift 8.\n+ * @parm[in, out] dev_flow\n+ * Pointer to the dev_flow.\n+ * @param[out] error\n+ * pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success otherwise -errno and errno is set.\n+ */\n+\n+int\n+flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n+\t\t\t\t\t const struct rte_flow_item *item,\n+\t\t\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_geneve_tlv_option_resource *geneve_opt_resource =\n+\t\t\tsh->geneve_tlv_option_resource;\n+\tstruct mlx5_devx_obj *obj;\n+\tconst struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;\n+\tint ret = 0;\n+\n+\tif (!geneve_opt_v)\n+\t\treturn -1;\n+\trte_spinlock_lock(&sh->geneve_tlv_opt_sl);\n+\tif (geneve_opt_resource != NULL) {\n+\t\tif (geneve_opt_resource->option_class ==\n+\t\t\tgeneve_opt_v->option_class &&\n+\t\t\tgeneve_opt_resource->option_type ==\n+\t\t\tgeneve_opt_v->option_type &&\n+\t\t\tgeneve_opt_resource->length ==\n+\t\t\tgeneve_opt_v->option_len) {\n+\t\t\t/* We already have GENVE TLV option obj allocated. */\n+\t\t\t__atomic_fetch_add(&geneve_opt_resource->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n+\t\t} else {\n+\t\t\tret = rte_flow_error_set(error, ENOMEM,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\"Only one GENEVE TLV option supported\");\n+\t\t\tgoto exit;\n+\t\t}\n+\t} else {\n+\t\t/* Create a GENEVE TLV object and resource. */\n+\t\tobj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,\n+\t\t\t\tgeneve_opt_v->option_class,\n+\t\t\t\tgeneve_opt_v->option_type,\n+\t\t\t\tgeneve_opt_v->option_len);\n+\t\tif (!obj) {\n+\t\t\tret = rte_flow_error_set(error, ENODATA,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\"Failed to create GENEVE TLV Devx object\");\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tsh->geneve_tlv_option_resource =\n+\t\t\t\tmlx5_malloc(MLX5_MEM_ZERO,\n+\t\t\t\t\t\tsizeof(*geneve_opt_resource),\n+\t\t\t\t\t\t0, SOCKET_ID_ANY);\n+\t\tif (!sh->geneve_tlv_option_resource) {\n+\t\t\tclaim_zero(mlx5_devx_cmd_destroy(obj));\n+\t\t\tret = rte_flow_error_set(error, ENOMEM,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\"GENEVE TLV object memory allocation failed\");\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tgeneve_opt_resource = sh->geneve_tlv_option_resource;\n+\t\tgeneve_opt_resource->obj = obj;\n+\t\tgeneve_opt_resource->option_class = geneve_opt_v->option_class;\n+\t\tgeneve_opt_resource->option_type = geneve_opt_v->option_type;\n+\t\tgeneve_opt_resource->length = geneve_opt_v->option_len;\n+\t\t__atomic_store_n(&geneve_opt_resource->refcnt, 1,\n+\t\t\t\t__ATOMIC_RELAXED);\n+\t}\n+exit:\n+\trte_spinlock_unlock(&sh->geneve_tlv_opt_sl);\n+\treturn ret;\n+}\n+\n /**\n * Add MPLS item to matcher and to the value.\n *\n@@ -11210,6 +11294,26 @@ flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,\n \t\t\t\t &cache->entry);\n }\n \n+static void\n+flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_geneve_tlv_option_resource *geneve_opt_resource =\n+\t\t\t\tsh->geneve_tlv_option_resource;\n+\trte_spinlock_lock(&sh->geneve_tlv_opt_sl);\n+\tif (geneve_opt_resource) {\n+\t\tif (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED))) {\n+\t\t\tclaim_zero(mlx5_devx_cmd_destroy\n+\t\t\t\t\t(geneve_opt_resource->obj));\n+\t\t\tmlx5_free(sh->geneve_tlv_option_resource);\n+\t\t\tsh->geneve_tlv_option_resource = NULL;\n+\t\t}\n+\t}\n+\trte_spinlock_unlock(&sh->geneve_tlv_opt_sl);\n+}\n+\n /**\n * Remove the flow from the NIC but keeps it in memory.\n * Lock free, (mutex should be acquired by caller).\n@@ -11280,6 +11384,10 @@ flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)\n \t}\n \tif (flow->age)\n \t\tflow_dv_aso_age_release(dev, flow->age);\n+\tif (flow->geneve_tlv_option) {\n+\t\tflow_dv_geneve_tlv_option_resource_release(dev);\n+\t\tflow->geneve_tlv_option = 0;\n+\t}\n \twhile (flow->dev_handles) {\n \t\tuint32_t tmp_idx = flow->dev_handles;\n \n", "prefixes": [ "v6", "6/9" ] }