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GET /api/patches/86372/?format=api
{ "id": 86372, "url": "http://patches.dpdk.org/api/patches/86372/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1610428684-20708-3-git-send-email-wei.huang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1610428684-20708-3-git-send-email-wei.huang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1610428684-20708-3-git-send-email-wei.huang@intel.com", "date": "2021-01-12T05:18:02", "name": "[v9,2/4] raw/ifpga: add fpga property get function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "30a22bcceddd6aa6be2388874dbcc12a897230ad", "submitter": { "id": 2033, "url": "http://patches.dpdk.org/api/people/2033/?format=api", "name": "Wei Huang", "email": "wei.huang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1610428684-20708-3-git-send-email-wei.huang@intel.com/mbox/", "series": [ { "id": 14655, "url": "http://patches.dpdk.org/api/series/14655/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14655", "date": "2021-01-12T05:18:00", "name": "raw/ifpga: add extra OPAE APIs", "version": 9, "mbox": "http://patches.dpdk.org/series/14655/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86372/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86372/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6D28DA04B5;\n\tTue, 12 Jan 2021 06:18:14 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BE0EA140DD3;\n\tTue, 12 Jan 2021 06:17:59 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 01DCC140DA7;\n Tue, 12 Jan 2021 06:17:57 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Jan 2021 21:17:57 -0800", "from unknown (HELO sh_lab5_1.sh.intel.com) ([10.238.175.190])\n by fmsmga002.fm.intel.com with ESMTP; 11 Jan 2021 21:17:54 -0800" ], "IronPort-SDR": [ "\n AteZbn+8JXF7/vEOTusVHvbDF0Zyu4FS+zF9eBYfRnaZ9COEn1bHU/ndV5gJRHYtkyyn8TIxa+\n NVnkCWbQpwMQ==", "\n 1nPSmqGbvFxYX2pJ0/H2kzgkFGAZ4AZToSzLYWOTQhp4KQs9FMhBIjNq8f7Dwd+Uvz58Ps9dFZ\n gYroqVSHoEfg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9861\"; a=\"165664957\"", "E=Sophos;i=\"5.79,340,1602572400\"; d=\"scan'208\";a=\"165664957\"", "E=Sophos;i=\"5.79,340,1602572400\"; d=\"scan'208\";a=\"400054390\"" ], "X-ExtLoop1": "1", "From": "Wei Huang <wei.huang@intel.com>", "To": "dev@dpdk.org,\n\trosen.xu@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "stable@dpdk.org, tianfei.zhang@intel.com, Wei Huang <wei.huang@intel.com>", "Date": "Tue, 12 Jan 2021 00:18:02 -0500", "Message-Id": "<1610428684-20708-3-git-send-email-wei.huang@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1610428684-20708-1-git-send-email-wei.huang@intel.com>", "References": "<1610428684-20708-1-git-send-email-wei.huang@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 2/4] raw/ifpga: add fpga property get function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "There are three types of property can be got from FPGA, they are\nimplemented in below functions:\n1. ifpga_rawdev_get_fme_property() get property of FME (FPGA\n Management Engine).\n2. ifpga_rawdev_get_port_property() get property of FPGA port.\n3. ifpga_rawdev_get_bmc_property() get property of BMC (Board\n Management Controller).\n\nSigned-off-by: Wei Huang <wei.huang@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_api.c | 8 ++\n drivers/raw/ifpga/base/ifpga_defines.h | 1 +\n drivers/raw/ifpga/base/ifpga_feature_dev.c | 21 +++\n drivers/raw/ifpga/base/ifpga_feature_dev.h | 1 +\n drivers/raw/ifpga/base/ifpga_fme.c | 28 +++-\n drivers/raw/ifpga/base/opae_hw_api.c | 18 +++\n drivers/raw/ifpga/base/opae_hw_api.h | 2 +\n drivers/raw/ifpga/base/opae_ifpga_hw_api.h | 1 +\n drivers/raw/ifpga/ifpga_rawdev.c | 157 +++++++++++++++++++++\n drivers/raw/ifpga/ifpga_rawdev.h | 28 ++++\n 10 files changed, 263 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/raw/ifpga/base/ifpga_api.c b/drivers/raw/ifpga/base/ifpga_api.c\nindex 1aedf150b..4610ef101 100644\n--- a/drivers/raw/ifpga/base/ifpga_api.c\n+++ b/drivers/raw/ifpga/base/ifpga_api.c\n@@ -229,6 +229,13 @@ static int ifpga_mgr_get_board_info(struct opae_manager *mgr,\n \treturn 0;\n }\n \n+static int ifpga_mgr_get_uuid(struct opae_manager *mgr, struct uuid *uuid)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fpga_get_pr_uuid(fme, uuid);\n+}\n+\n static int ifpga_mgr_update_flash(struct opae_manager *mgr, const char *image,\n \tu64 *status)\n {\n@@ -256,6 +263,7 @@ struct opae_manager_ops ifpga_mgr_ops = {\n \t.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,\n \t.get_sensor_value = ifpga_mgr_get_sensor_value,\n \t.get_board_info = ifpga_mgr_get_board_info,\n+\t.get_uuid = ifpga_mgr_get_uuid,\n \t.update_flash = ifpga_mgr_update_flash,\n \t.stop_flash_update = ifpga_mgr_stop_flash_update,\n \t.reload = ifpga_mgr_reload,\ndiff --git a/drivers/raw/ifpga/base/ifpga_defines.h b/drivers/raw/ifpga/base/ifpga_defines.h\nindex 9f0147d1e..dca1518a8 100644\n--- a/drivers/raw/ifpga/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga/base/ifpga_defines.h\n@@ -1727,6 +1727,7 @@ struct opae_board_info {\n \tu8 seu;\n \tu8 ptp;\n \n+\tu32 boot_page;\n \tu32 max10_version;\n \tu32 nios_fw_version;\n \tu32 nums_of_retimer;\ndiff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.c b/drivers/raw/ifpga/base/ifpga_feature_dev.c\nindex 0f852a75a..08135137a 100644\n--- a/drivers/raw/ifpga/base/ifpga_feature_dev.c\n+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.c\n@@ -87,6 +87,27 @@ int fpga_get_afu_uuid(struct ifpga_port_hw *port, struct uuid *uuid)\n \treturn 0;\n }\n \n+int fpga_get_pr_uuid(struct ifpga_fme_hw *fme, struct uuid *uuid)\n+{\n+\tstruct feature_fme_pr *fme_pr;\n+\tu64 guidl, guidh;\n+\n+\tif (!fme || !uuid)\n+\t\treturn -EINVAL;\n+\n+\tfme_pr = get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_PR_MGMT);\n+\n+\tspinlock_lock(&fme->lock);\n+\tguidl = readq(&fme_pr->fme_pr_intfc_id_l);\n+\tguidh = readq(&fme_pr->fme_pr_intfc_id_h);\n+\tspinlock_unlock(&fme->lock);\n+\n+\topae_memcpy(uuid->b, &guidl, sizeof(u64));\n+\topae_memcpy(uuid->b + 8, &guidh, sizeof(u64));\n+\n+\treturn 0;\n+}\n+\n /* Mask / Unmask Port Errors by the Error Mask register. */\n void port_err_mask(struct ifpga_port_hw *port, bool mask)\n {\ndiff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.h b/drivers/raw/ifpga/base/ifpga_feature_dev.h\nindex 2b1309b44..b355d22b0 100644\n--- a/drivers/raw/ifpga/base/ifpga_feature_dev.h\n+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.h\n@@ -103,6 +103,7 @@ is_port_feature_present(struct ifpga_port_hw *port, int index)\n }\n \n int fpga_get_afu_uuid(struct ifpga_port_hw *port, struct uuid *uuid);\n+int fpga_get_pr_uuid(struct ifpga_fme_hw *fme, struct uuid *uuid);\n \n int __fpga_port_disable(struct ifpga_port_hw *port);\n void __fpga_port_enable(struct ifpga_port_hw *port);\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c\nindex 34fd9a818..43c7b9c3d 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme.c\n@@ -101,6 +101,24 @@ static int fme_hdr_get_ports_num(struct ifpga_fme_hw *fme, u64 *ports_num)\n \treturn 0;\n }\n \n+static int fme_hdr_get_port_type(struct ifpga_fme_hw *fme, u64 *port_type)\n+{\n+\tstruct feature_fme_header *fme_hdr\n+\t\t= get_fme_feature_ioaddr_by_index(fme, FME_FEATURE_ID_HEADER);\n+\tstruct feature_fme_port pt;\n+\tu32 port = (u32)((*port_type >> 32) & 0xffffffff);\n+\n+\tpt.csr = readq(&fme_hdr->port[port]);\n+\tif (!pt.port_implemented)\n+\t\treturn -ENODEV;\n+\tif (pt.afu_access_control)\n+\t\t*port_type |= 0x1;\n+\telse\n+\t\t*port_type &= ~0x1;\n+\n+\treturn 0;\n+}\n+\n static int fme_hdr_get_cache_size(struct ifpga_fme_hw *fme, u64 *cache_size)\n {\n \tstruct feature_fme_header *fme_hdr\n@@ -179,6 +197,8 @@ fme_hdr_get_prop(struct ifpga_feature *feature, struct feature_prop *prop)\n \t\treturn fme_hdr_get_bitstream_id(fme, &prop->data);\n \tcase FME_HDR_PROP_BITSTREAM_METADATA:\n \t\treturn fme_hdr_get_bitstream_metadata(fme, &prop->data);\n+\tcase FME_HDR_PROP_PORT_TYPE:\n+\t\treturn fme_hdr_get_port_type(fme, &prop->data);\n \t}\n \n \treturn -ENOENT;\n@@ -891,13 +911,17 @@ static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n \t\t\tfme->board_info.nums_of_fvl,\n \t\t\tfme->board_info.ports_per_fvl);\n \n+\tif (max10_sys_read(fme->max10_dev, FPGA_PAGE_INFO, &val))\n+\t\treturn -EINVAL;\n+\tfme->board_info.boot_page = val & 0x7;\n+\n \tif (max10_sys_read(fme->max10_dev, MAX10_BUILD_VER, &val))\n \t\treturn -EINVAL;\n-\tfme->board_info.max10_version = val & 0xffffff;\n+\tfme->board_info.max10_version = val;\n \n \tif (max10_sys_read(fme->max10_dev, NIOS2_FW_VERSION, &val))\n \t\treturn -EINVAL;\n-\tfme->board_info.nios_fw_version = val & 0xffffff;\n+\tfme->board_info.nios_fw_version = val;\n \n \tdev_info(fme, \"max10 version 0x%x, nios fw version 0x%x\\n\",\n \t\tfme->board_info.max10_version,\ndiff --git a/drivers/raw/ifpga/base/opae_hw_api.c b/drivers/raw/ifpga/base/opae_hw_api.c\nindex 86ad88f72..11c9887c7 100644\n--- a/drivers/raw/ifpga/base/opae_hw_api.c\n+++ b/drivers/raw/ifpga/base/opae_hw_api.c\n@@ -967,6 +967,24 @@ opae_mgr_get_board_info(struct opae_manager *mgr,\n \treturn -ENOENT;\n }\n \n+/**\n+ * opae_mgr_get_uuid - get manager's UUID.\n+ * @mgr: targeted manager\n+ * @uuid: a pointer to UUID\n+ *\n+ * Return: 0 on success, otherwise error code.\n+ */\n+int opae_mgr_get_uuid(struct opae_manager *mgr, struct uuid *uuid)\n+{\n+\tif (!mgr || !uuid)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->ops && mgr->ops->get_uuid)\n+\t\treturn mgr->ops->get_uuid(mgr, uuid);\n+\n+\treturn -ENOENT;\n+}\n+\n /**\n * opae_mgr_update_flash - update image in flash.\n * @mgr: targeted manager\ndiff --git a/drivers/raw/ifpga/base/opae_hw_api.h b/drivers/raw/ifpga/base/opae_hw_api.h\nindex c819dc3d2..fcf7d2f6d 100644\n--- a/drivers/raw/ifpga/base/opae_hw_api.h\n+++ b/drivers/raw/ifpga/base/opae_hw_api.h\n@@ -55,6 +55,7 @@ struct opae_manager_ops {\n \t\t\tunsigned int *value);\n \tint (*get_board_info)(struct opae_manager *mgr,\n \t\t\tstruct opae_board_info **info);\n+\tint (*get_uuid)(struct opae_manager *mgr, struct uuid *uuid);\n \tint (*update_flash)(struct opae_manager *mgr, const char *image,\n \t\t\tu64 *status);\n \tint (*stop_flash_update)(struct opae_manager *mgr, int force);\n@@ -360,6 +361,7 @@ int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,\n \t\tu8 type, u8 index, u16 addr, u32 *data);\n int opae_mgr_get_board_info(struct opae_manager *mgr,\n \t\tstruct opae_board_info **info);\n+int opae_mgr_get_uuid(struct opae_manager *mgr, struct uuid *uuid);\n int opae_mgr_update_flash(struct opae_manager *mgr, const char *image,\n \t\tuint64_t *status);\n int opae_mgr_stop_flash_update(struct opae_manager *mgr, int force);\ndiff --git a/drivers/raw/ifpga/base/opae_ifpga_hw_api.h b/drivers/raw/ifpga/base/opae_ifpga_hw_api.h\nindex bab33862e..ffdbebf70 100644\n--- a/drivers/raw/ifpga/base/opae_ifpga_hw_api.h\n+++ b/drivers/raw/ifpga/base/opae_ifpga_hw_api.h\n@@ -61,6 +61,7 @@ struct feature_prop {\n #define FME_HDR_PROP_SOCKET_ID\t\t0x5\t/* RDONLY */\n #define FME_HDR_PROP_BITSTREAM_ID\t\t0x6\t/* RDONLY */\n #define FME_HDR_PROP_BITSTREAM_METADATA\t0x7\t/* RDONLY */\n+#define FME_HDR_PROP_PORT_TYPE\t\t0x8\t/* RDWR */\n \n /* FME error reporting feature's properties */\n /* FME error reporting properties format */\ndiff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c\nindex 660ea2051..8dd566e44 100644\n--- a/drivers/raw/ifpga/ifpga_rawdev.c\n+++ b/drivers/raw/ifpga/ifpga_rawdev.c\n@@ -1738,6 +1738,163 @@ RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,\n \t\"port=<int> \"\n \t\"afu_bts=<path>\");\n \n+int ifpga_rawdev_get_fme_property(struct rte_rawdev *dev,\n+\tifpga_fme_property *prop)\n+{\n+\tstruct opae_adapter *adapter = NULL;\n+\tstruct ifpga_fme_hw *fme = NULL;\n+\tstruct opae_board_info *info = NULL;\n+\tstruct feature_prop fp;\n+\tstruct uuid pr_id;\n+\tint ret = 0;\n+\n+\tif (!dev) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"rawdev is invalid\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tadapter = ifpga_rawdev_get_priv(dev);\n+\tif (!adapter) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"adapter is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (!adapter->mgr || !adapter->mgr->data) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"manager is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = opae_mgr_get_board_info(adapter->mgr, &info);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get board info\");\n+\t\treturn ret;\n+\t}\n+\tprop->boot_page = info->boot_page;\n+\n+\tfme = adapter->mgr->data;\n+\tfp.feature_id = FME_FEATURE_ID_HEADER;\n+\tfp.prop_id = FME_HDR_PROP_PORTS_NUM;\n+\tret = ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, &fp);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get property %u from FME\",\n+\t\t\tFME_HDR_PROP_PORTS_NUM);\n+\t\treturn ret;\n+\t}\n+\tprop->num_ports = fp.data;\n+\n+\tfp.prop_id = FME_HDR_PROP_BITSTREAM_ID;\n+\tret = ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, &fp);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get property %u from FME\",\n+\t\t\tFME_HDR_PROP_BITSTREAM_ID);\n+\t\treturn ret;\n+\t}\n+\tprop->bitstream_id = fp.data;\n+\n+\tfp.prop_id = FME_HDR_PROP_BITSTREAM_METADATA;\n+\tret = ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, &fp);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get property %u from FME\",\n+\t\t\tFME_HDR_PROP_BITSTREAM_METADATA);\n+\t\treturn ret;\n+\t}\n+\tprop->bitstream_metadata = fp.data;\n+\n+\tret = opae_mgr_get_uuid(adapter->mgr, &pr_id);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get PR ID from FME\");\n+\t\treturn ret;\n+\t}\n+\tmemcpy(prop->pr_id.b, pr_id.b, sizeof(ifpga_uuid));\n+\n+\treturn 0;\n+}\n+\n+int ifpga_rawdev_get_port_property(struct rte_rawdev *dev, uint32_t port,\n+\tifpga_port_property *prop)\n+{\n+\tstruct opae_adapter *adapter = NULL;\n+\tstruct ifpga_fme_hw *fme = NULL;\n+\tstruct feature_prop fp;\n+\tstruct opae_accelerator *acc = NULL;\n+\tstruct uuid afu_id;\n+\tint ret = 0;\n+\n+\tif (!dev) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"rawdev is invalid\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tadapter = ifpga_rawdev_get_priv(dev);\n+\tif (!adapter) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"adapter is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (!adapter->mgr || !adapter->mgr->data) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"manager is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tfme = adapter->mgr->data;\n+\tfp.feature_id = FME_FEATURE_ID_HEADER;\n+\tfp.prop_id = FME_HDR_PROP_PORT_TYPE;\n+\tfp.data = port;\n+\tfp.data <<= 32;\n+\tret = ifpga_get_prop(fme->parent, FEATURE_FIU_ID_FME, 0, &fp);\n+\tif (ret)\n+\t\treturn ret;\n+\tprop->type = fp.data & 0xffffffff;\n+\n+\tif (prop->type == 0) {\n+\t\tacc = opae_adapter_get_acc(adapter, port);\n+\t\tret = opae_acc_get_uuid(acc, &afu_id);\n+\t\tif (ret) {\n+\t\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get AFU ID from port %u\",\n+\t\t\t\tport);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tmemcpy(prop->afu_id.b, afu_id.b, sizeof(ifpga_uuid));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int ifpga_rawdev_get_bmc_property(struct rte_rawdev *dev,\n+\tifpga_bmc_property *prop)\n+{\n+\tstruct opae_adapter *adapter = NULL;\n+\tstruct opae_board_info *info = NULL;\n+\tint ret = 0;\n+\n+\tif (!dev) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"rawdev is invalid\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tadapter = ifpga_rawdev_get_priv(dev);\n+\tif (!adapter) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"adapter is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (!adapter->mgr) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"manager is invalid\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = opae_mgr_get_board_info(adapter->mgr, &info);\n+\tif (ret) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Failed to get board info\");\n+\t\treturn ret;\n+\t}\n+\n+\tprop->bmc_version = info->max10_version;\n+\tprop->fw_version = info->nios_fw_version;\n+\n+\treturn 0;\n+}\n+\n int ifpga_rawdev_update_flash(struct rte_rawdev *dev, const char *image,\n \tuint64_t *status)\n {\ndiff --git a/drivers/raw/ifpga/ifpga_rawdev.h b/drivers/raw/ifpga/ifpga_rawdev.h\nindex bf74a5eb3..d4be7913d 100644\n--- a/drivers/raw/ifpga/ifpga_rawdev.h\n+++ b/drivers/raw/ifpga/ifpga_rawdev.h\n@@ -67,6 +67,28 @@ enum ifpga_irq_type {\n \tIFPGA_AFU_IRQ = 1,\n };\n \n+typedef struct {\n+\tuint8_t b[16];\n+} ifpga_uuid;\n+\n+typedef struct {\n+\tuint32_t boot_page;\n+\tuint32_t num_ports;\n+\tuint64_t bitstream_id;\n+\tuint64_t bitstream_metadata;\n+\tifpga_uuid pr_id;\n+} ifpga_fme_property;\n+\n+typedef struct {\n+\tifpga_uuid afu_id;\n+\tuint32_t type; /* AFU memory access control type */\n+} ifpga_port_property;\n+\n+typedef struct {\n+\tuint32_t bmc_version;\n+\tuint32_t fw_version;\n+} ifpga_bmc_property;\n+\n int\n ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,\n \t\tenum ifpga_irq_type type, int vec_start, int count,\n@@ -76,6 +98,12 @@ int\n ifpga_unregister_msix_irq(enum ifpga_irq_type type,\n \t\tint vec_start, rte_intr_callback_fn handler, void *arg);\n \n+int ifpga_rawdev_get_fme_property(struct rte_rawdev *dev,\n+\tifpga_fme_property *prop);\n+int ifpga_rawdev_get_port_property(struct rte_rawdev *dev, uint32_t port,\n+\tifpga_port_property *prop);\n+int ifpga_rawdev_get_bmc_property(struct rte_rawdev *dev,\n+\tifpga_bmc_property *prop);\n int ifpga_rawdev_update_flash(struct rte_rawdev *dev, const char *image,\n \tuint64_t *status);\n int ifpga_rawdev_stop_flash_update(struct rte_rawdev *dev, int force);\n", "prefixes": [ "v9", "2/4" ] }