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GET /api/patches/86043/?format=api
{ "id": 86043, "url": "http://patches.dpdk.org/api/patches/86043/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-19-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-19-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-19-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:40", "name": "[v3,18/19] net/mlx5: move Rx RQ creation to common", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ba96f37b37f06fa747b0fe1b440c40857f564f43", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-19-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86043/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86043/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C2246A09FF;\n\tWed, 6 Jan 2021 09:23:02 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BF776160913;\n\tWed, 6 Jan 2021 09:21:44 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 31B4A160922\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:21:42 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:21:36 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgl009291;\n Wed, 6 Jan 2021 10:21:36 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 6 Jan 2021 08:19:40 +0000", "Message-Id": "<1609921181-5019-19-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 18/19] net/mlx5: move Rx RQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for Rx RQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 4 +-\n drivers/net/mlx5/mlx5_devx.c | 177 +++++++++----------------------------------\n drivers/net/mlx5/mlx5_rxtx.h | 4 -\n 3 files changed, 37 insertions(+), 148 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex a3fd8d5..3836a96 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -776,8 +776,9 @@ struct mlx5_rxq_obj {\n \t\t\tvoid *ibv_cq; /* Completion Queue. */\n \t\t\tvoid *ibv_channel;\n \t\t};\n+\t\tstruct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */\n \t\tstruct {\n-\t\t\tstruct mlx5_devx_obj *rq; /* DevX Rx Queue object. */\n+\t\t\tstruct mlx5_devx_rq rq_obj; /* DevX RQ object. */\n \t\t\tstruct mlx5_devx_cq cq_obj; /* DevX CQ object. */\n \t\t\tvoid *devx_channel;\n \t\t};\n@@ -954,7 +955,6 @@ struct mlx5_priv {\n \t/* Context for Verbs allocator. */\n \tint nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */\n \tint nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */\n-\tstruct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */\n \tstruct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */\n \tstruct mlx5_hlist *mreg_cp_tbl;\n \t/* Hash table of Rx metadata register copy table. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 96c44d4..935cbd0 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -45,7 +45,7 @@\n \trq_attr.state = MLX5_RQC_STATE_RDY;\n \trq_attr.vsd = (on ? 0 : 1);\n \trq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;\n-\treturn mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);\n+\treturn mlx5_devx_cmd_modify_rq(rxq_obj->rq_obj.rq, &rq_attr);\n }\n \n /**\n@@ -85,7 +85,7 @@\n \tdefault:\n \t\tbreak;\n \t}\n-\treturn mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);\n+\treturn mlx5_devx_cmd_modify_rq(rxq_obj->rq_obj.rq, &rq_attr);\n }\n \n /**\n@@ -145,44 +145,18 @@\n }\n \n /**\n- * Release the resources allocated for an RQ DevX object.\n- *\n- * @param rxq_ctrl\n- * DevX Rx queue object.\n- */\n-static void\n-mlx5_rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n-{\n-\tstruct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->rq_dbrec_page;\n-\n-\tif (rxq_ctrl->wq_umem) {\n-\t\tmlx5_os_umem_dereg(rxq_ctrl->wq_umem);\n-\t\trxq_ctrl->wq_umem = NULL;\n-\t}\n-\tif (rxq_ctrl->rxq.wqes) {\n-\t\tmlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);\n-\t\trxq_ctrl->rxq.wqes = NULL;\n-\t}\n-\tif (dbr_page) {\n-\t\tclaim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,\n-\t\t\t\t\t mlx5_os_get_umem_id(dbr_page->umem),\n-\t\t\t\t\t rxq_ctrl->rq_dbr_offset));\n-\t\trxq_ctrl->rq_dbrec_page = NULL;\n-\t}\n-}\n-\n-/**\n * Destroy the Rx queue DevX object.\n *\n * @param rxq_obj\n * Rxq object to destroy.\n */\n static void\n-mlx5_rxq_release_devx_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n+mlx5_rxq_release_devx_resources(struct mlx5_rxq_obj *rxq_obj)\n {\n-\tmlx5_rxq_release_devx_rq_resources(rxq_ctrl);\n-\tmlx5_devx_cq_destroy(&rxq_ctrl->obj->cq_obj);\n-\tmemset(&rxq_ctrl->obj->cq_obj, 0, sizeof(rxq_ctrl->obj->cq_obj));\n+\tmlx5_devx_rq_destroy(&rxq_obj->rq_obj);\n+\tmemset(&rxq_obj->rq_obj, 0, sizeof(rxq_obj->rq_obj));\n+\tmlx5_devx_cq_destroy(&rxq_obj->cq_obj);\n+\tmemset(&rxq_obj->cq_obj, 0, sizeof(rxq_obj->cq_obj));\n }\n \n /**\n@@ -195,17 +169,17 @@\n mlx5_rxq_devx_obj_release(struct mlx5_rxq_obj *rxq_obj)\n {\n \tMLX5_ASSERT(rxq_obj);\n-\tMLX5_ASSERT(rxq_obj->rq);\n \tif (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {\n+\t\tMLX5_ASSERT(rxq_obj->rq);\n \t\tmlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t} else {\n-\t\tMLX5_ASSERT(rxq_obj->cq_obj);\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n+\t\tMLX5_ASSERT(rxq_obj->cq_obj.cq);\n+\t\tMLX5_ASSERT(rxq_obj->rq_obj.rq);\n+\t\tmlx5_rxq_release_devx_resources(rxq_obj);\n \t\tif (rxq_obj->devx_channel)\n \t\t\tmlx5_os_devx_destroy_event_channel\n \t\t\t\t\t\t\t(rxq_obj->devx_channel);\n-\t\tmlx5_rxq_release_devx_resources(rxq_obj->rxq_ctrl);\n \t}\n }\n \n@@ -247,52 +221,6 @@\n }\n \n /**\n- * Fill common fields of create RQ attributes structure.\n- *\n- * @param rxq_data\n- * Pointer to Rx queue data.\n- * @param cqn\n- * CQ number to use with this RQ.\n- * @param rq_attr\n- * RQ attributes structure to fill..\n- */\n-static void\n-mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,\n-\t\t\t struct mlx5_devx_create_rq_attr *rq_attr)\n-{\n-\trq_attr->state = MLX5_RQC_STATE_RST;\n-\trq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;\n-\trq_attr->cqn = cqn;\n-\trq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;\n-}\n-\n-/**\n- * Fill common fields of DevX WQ attributes structure.\n- *\n- * @param priv\n- * Pointer to device private data.\n- * @param rxq_ctrl\n- * Pointer to Rx queue control structure.\n- * @param wq_attr\n- * WQ attributes structure to fill..\n- */\n-static void\n-mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,\n-\t\t struct mlx5_devx_wq_attr *wq_attr)\n-{\n-\twq_attr->end_padding_mode = priv->config.hw_padding ?\n-\t\t\t\t\tMLX5_WQ_END_PAD_MODE_ALIGN :\n-\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n-\twq_attr->pd = priv->sh->pdn;\n-\twq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;\n-\twq_attr->dbr_umem_id =\n-\t\t\tmlx5_os_get_umem_id(rxq_ctrl->rq_dbrec_page->umem);\n-\twq_attr->dbr_umem_valid = 1;\n-\twq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);\n-\twq_attr->wq_umem_valid = 1;\n-}\n-\n-/**\n * Create a RQ object using DevX.\n *\n * @param dev\n@@ -301,9 +229,9 @@\n * Queue index in DPDK Rx queue array.\n *\n * @return\n- * The DevX RQ object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_devx_obj *\n+static int\n mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -311,20 +239,15 @@\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct mlx5_devx_create_rq_attr rq_attr = { 0 };\n-\tuint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);\n-\tuint32_t cqn = rxq_ctrl->obj->cq_obj.cq->id;\n-\tstruct mlx5_devx_dbr_page *dbr_page;\n-\tint64_t dbr_offset;\n-\tuint32_t wq_size = 0;\n-\tuint32_t wqe_size = 0;\n-\tuint32_t log_wqe_size = 0;\n-\tvoid *buf = NULL;\n-\tstruct mlx5_devx_obj *rq;\n+\tuint16_t log_desc_n = rxq_data->elts_n - rxq_data->sges_n;\n+\tuint32_t wqe_size, log_wqe_size;\n \n \t/* Fill RQ attributes. */\n \trq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;\n \trq_attr.flush_in_error_en = 1;\n-\tmlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);\n+\trq_attr.vsd = (rxq_data->vlan_strip) ? 0 : 1;\n+\trq_attr.cqn = rxq_ctrl->obj->cq_obj.cq->id;\n+\trq_attr.scatter_fcs = (rxq_data->crc_present) ? 1 : 0;\n \t/* Fill WQ attributes for this RQ. */\n \tif (mlx5_rxq_mprq_enabled(rxq_data)) {\n \t\trq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;\n@@ -345,45 +268,17 @@\n \t\twqe_size = sizeof(struct mlx5_wqe_data_seg);\n \t}\n \tlog_wqe_size = log2above(wqe_size) + rxq_data->sges_n;\n-\trq_attr.wq_attr.log_wq_stride = log_wqe_size;\n-\trq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;\n-\t/* Calculate and allocate WQ memory space. */\n \twqe_size = 1 << log_wqe_size; /* round up power of two.*/\n-\twq_size = wqe_n * wqe_size;\n-\tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n-\tif (alignment == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn NULL;\n-\t}\n-\tbuf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,\n-\t\t\t alignment, rxq_ctrl->socket);\n-\tif (!buf)\n-\t\treturn NULL;\n-\trxq_data->wqes = buf;\n-\trxq_ctrl->wq_umem = mlx5_os_umem_reg(priv->sh->ctx,\n-\t\t\t\t\t\t buf, wq_size, 0);\n-\tif (!rxq_ctrl->wq_umem)\n-\t\tgoto error;\n-\t/* Allocate RQ door-bell. */\n-\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);\n-\tif (dbr_offset < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate RQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\trxq_ctrl->rq_dbr_offset = dbr_offset;\n-\trxq_ctrl->rq_dbrec_page = dbr_page;\n-\trxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n-\t\t\t (uintptr_t)rxq_ctrl->rq_dbr_offset);\n+\trq_attr.wq_attr.log_wq_stride = log_wqe_size;\n+\trq_attr.wq_attr.log_wq_sz = log_desc_n;\n+\trq_attr.wq_attr.end_padding_mode = priv->config.hw_padding ?\n+\t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_ALIGN :\n+\t\t\t\t\t\tMLX5_WQ_END_PAD_MODE_NONE;\n+\trq_attr.wq_attr.pd = priv->sh->pdn;\n \t/* Create RQ using DevX API. */\n-\tmlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);\n-\trq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);\n-\tif (!rq)\n-\t\tgoto error;\n-\treturn rq;\n-error:\n-\tmlx5_rxq_release_devx_rq_resources(rxq_ctrl);\n-\treturn NULL;\n+\treturn mlx5_devx_rq_create(priv->sh->ctx, &rxq_ctrl->obj->rq_obj,\n+\t\t\t\t wqe_size, log_desc_n, &rq_attr,\n+\t\t\t\t rxq_ctrl->socket);\n }\n \n /**\n@@ -604,8 +499,8 @@\n \t\tgoto error;\n \t}\n \t/* Create RQ using DevX API. */\n-\ttmpl->rq = mlx5_rxq_create_devx_rq_resources(dev, idx);\n-\tif (!tmpl->rq) {\n+\tret = mlx5_rxq_create_devx_rq_resources(dev, idx);\n+\tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u Rx queue %u RQ creation failure.\",\n \t\t\tdev->data->port_id, idx);\n \t\trte_errno = ENOMEM;\n@@ -615,19 +510,17 @@\n \tret = mlx5_devx_modify_rq(tmpl, MLX5_RXQ_MOD_RST2RDY);\n \tif (ret)\n \t\tgoto error;\n+\trxq_data->wqes = (void *)(uintptr_t)tmpl->rq_obj.umem_buf;\n+\trxq_data->rq_db = (uint32_t *)(uintptr_t)tmpl->rq_obj.db_rec;\n \trxq_data->cq_arm_sn = 0;\n-\tmlx5_rxq_initialize(rxq_data);\n \trxq_data->cq_ci = 0;\n+\tmlx5_rxq_initialize(rxq_data);\n \tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;\n-\trxq_ctrl->wqn = tmpl->rq->id;\n+\trxq_ctrl->wqn = tmpl->rq_obj.rq->id;\n \treturn 0;\n error:\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n-\tif (tmpl->rq)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->rq));\n-\tif (tmpl->devx_channel)\n-\t\tmlx5_os_devx_destroy_event_channel(tmpl->devx_channel);\n-\tmlx5_rxq_release_devx_resources(rxq_ctrl);\n+\tmlx5_rxq_devx_obj_release(tmpl);\n \trte_errno = ret; /* Restore rte_errno. */\n \treturn -rte_errno;\n }\n@@ -671,7 +564,7 @@\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\t\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n \n-\t\trqt_attr->rq_list[i] = rxq_ctrl->obj->rq->id;\n+\t\trqt_attr->rq_list[i] = rxq_ctrl->obj->rq_obj.rq->id;\n \t}\n \tMLX5_ASSERT(i > 0);\n \tfor (j = 0; i != rqt_n; ++j, ++i)\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex aba9541..7756ed3 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -193,10 +193,6 @@ struct mlx5_rxq_ctrl {\n \tuint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */\n \tuint32_t wqn; /* WQ number. */\n \tuint16_t dump_file_n; /* Number of dump files. */\n-\tstruct mlx5_devx_dbr_page *rq_dbrec_page;\n-\tuint64_t rq_dbr_offset;\n-\t/* Storing RQ door-bell information, needed when freeing door-bell. */\n-\tvoid *wq_umem; /* WQ buffer registration info. */\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n };\n", "prefixes": [ "v3", "18/19" ] }