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GET /api/patches/86040/?format=api
{ "id": 86040, "url": "http://patches.dpdk.org/api/patches/86040/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-17-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-17-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-17-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:38", "name": "[v3,16/19] net/mlx5: move ASO SQ creation to common", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1329117fcf01403ffb51bb22b220d5d9df533d85", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-17-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86040/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86040/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2459EA09FF;\n\tWed, 6 Jan 2021 09:22:37 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BEC36160918;\n\tWed, 6 Jan 2021 09:21:34 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 1EC96160915\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:21:32 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:21:29 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgj009291;\n Wed, 6 Jan 2021 10:21:29 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 6 Jan 2021 08:19:38 +0000", "Message-Id": "<1609921181-5019-17-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 16/19] net/mlx5: move ASO SQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for ASO SQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_devx.h | 1 +\n drivers/net/mlx5/mlx5.h | 8 +--\n drivers/net/mlx5/mlx5_flow_age.c | 94 ++++++++++------------------------\n 3 files changed, 30 insertions(+), 73 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h\nindex 6b078b2..992ad8f 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.h\n+++ b/drivers/common/mlx5/mlx5_common_devx.h\n@@ -28,6 +28,7 @@ struct mlx5_devx_sq {\n \tunion {\n \t\tvolatile void *umem_buf;\n \t\tvolatile struct mlx5_wqe *wqes; /* The SQ ring buffer. */\n+\t\tvolatile struct mlx5_aso_wqe *aso_wqes;\n \t};\n \tvolatile uint32_t *db_rec; /* The SQ doorbell record. */\n };\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 62d7c89..a3fd8d5 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -487,13 +487,7 @@ struct mlx5_aso_sq_elem {\n struct mlx5_aso_sq {\n \tuint16_t log_desc_n;\n \tstruct mlx5_aso_cq cq;\n-\tstruct mlx5_devx_obj *sq;\n-\tstruct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */\n-\tunion {\n-\t\tvolatile void *umem_buf;\n-\t\tvolatile struct mlx5_aso_wqe *wqes;\n-\t};\n-\tvolatile uint32_t *db_rec;\n+\tstruct mlx5_devx_sq sq_obj;\n \tvolatile uint64_t *uar_addr;\n \tstruct mlx5_aso_devx_mr mr;\n \tuint16_t pi;\ndiff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c\nindex a75adc8..3005afd 100644\n--- a/drivers/net/mlx5/mlx5_flow_age.c\n+++ b/drivers/net/mlx5/mlx5_flow_age.c\n@@ -142,18 +142,7 @@\n static void\n mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)\n {\n-\tif (sq->wqe_umem) {\n-\t\tmlx5_glue->devx_umem_dereg(sq->wqe_umem);\n-\t\tsq->wqe_umem = NULL;\n-\t}\n-\tif (sq->umem_buf) {\n-\t\tmlx5_free((void *)(uintptr_t)sq->umem_buf);\n-\t\tsq->umem_buf = NULL;\n-\t}\n-\tif (sq->sq) {\n-\t\tmlx5_devx_cmd_destroy(sq->sq);\n-\t\tsq->sq = NULL;\n-\t}\n+\tmlx5_devx_sq_destroy(&sq->sq_obj);\n \tmlx5_aso_cq_destroy(&sq->cq);\n \tmlx5_aso_devx_dereg_mr(&sq->mr);\n \tmemset(sq, 0, sizeof(*sq));\n@@ -174,7 +163,7 @@\n \tuint64_t addr;\n \n \t/* All the next fields state should stay constant. */\n-\tfor (i = 0, wqe = &sq->wqes[0]; i < size; ++i, ++wqe) {\n+\tfor (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {\n \t\twqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |\n \t\t\t\t\t\t\t (sizeof(*wqe) >> 4));\n \t\twqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);\n@@ -215,12 +204,18 @@\n mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,\n \t\t void *uar, uint32_t pdn, uint16_t log_desc_n)\n {\n-\tstruct mlx5_devx_create_sq_attr attr = { 0 };\n-\tstruct mlx5_devx_modify_sq_attr modify_attr = { 0 };\n-\tsize_t pgsize = rte_mem_page_size();\n-\tstruct mlx5_devx_wq_attr *wq_attr = &attr.wq_attr;\n+\tstruct mlx5_devx_create_sq_attr attr = {\n+\t\t.user_index = 0xFFFF,\n+\t\t.wq_attr = (struct mlx5_devx_wq_attr){\n+\t\t\t.pd = pdn,\n+\t\t\t.uar_page = mlx5_os_get_devx_uar_page_id(uar),\n+\t\t},\n+\t};\n+\tstruct mlx5_devx_modify_sq_attr modify_attr = {\n+\t\t.state = MLX5_SQC_STATE_RDY,\n+\t};\n \tuint32_t sq_desc_n = 1 << log_desc_n;\n-\tuint32_t wq_size = sizeof(struct mlx5_aso_wqe) * sq_desc_n;\n+\tuint16_t log_wqbb_n;\n \tint ret;\n \n \tif (mlx5_aso_devx_reg_mr(ctx, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *\n@@ -230,58 +225,25 @@\n \t\t\t mlx5_os_get_devx_uar_page_id(uar)))\n \t\tgoto error;\n \tsq->log_desc_n = log_desc_n;\n-\tsq->umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size +\n-\t\t\t\t sizeof(*sq->db_rec) * 2, 4096, socket);\n-\tif (!sq->umem_buf) {\n-\t\tDRV_LOG(ERR, \"Can't allocate wqe buffer.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tsq->wqe_umem = mlx5_os_umem_reg(ctx,\n-\t\t\t\t\t\t(void *)(uintptr_t)sq->umem_buf,\n-\t\t\t\t\t\twq_size +\n-\t\t\t\t\t\tsizeof(*sq->db_rec) * 2,\n-\t\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n-\tif (!sq->wqe_umem) {\n-\t\tDRV_LOG(ERR, \"Failed to register umem for SQ.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tattr.state = MLX5_SQC_STATE_RST;\n-\tattr.tis_lst_sz = 0;\n-\tattr.tis_num = 0;\n-\tattr.user_index = 0xFFFF;\n \tattr.cqn = sq->cq.cq_obj.cq->id;\n-\twq_attr->uar_page = mlx5_os_get_devx_uar_page_id(uar);\n-\twq_attr->pd = pdn;\n-\twq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC;\n-\twq_attr->log_wq_pg_sz = rte_log2_u32(pgsize);\n-\twq_attr->wq_umem_id = mlx5_os_get_umem_id(sq->wqe_umem);\n-\twq_attr->wq_umem_offset = 0;\n-\twq_attr->wq_umem_valid = 1;\n-\twq_attr->log_wq_stride = 6;\n-\twq_attr->log_wq_sz = rte_log2_u32(wq_size) - 6;\n-\twq_attr->dbr_umem_id = wq_attr->wq_umem_id;\n-\twq_attr->dbr_addr = wq_size;\n-\twq_attr->dbr_umem_valid = 1;\n-\tsq->sq = mlx5_devx_cmd_create_sq(ctx, &attr);\n-\tif (!sq->sq) {\n-\t\tDRV_LOG(ERR, \"Can't create sq object.\");\n-\t\trte_errno = ENOMEM;\n+\t/* for mlx5_aso_wqe that is twice the size of mlx5_wqe */\n+\tlog_wqbb_n = log_desc_n + 1;\n+\tret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Can't create SQ object.\");\n+\t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tmodify_attr.state = MLX5_SQC_STATE_RDY;\n-\tret = mlx5_devx_cmd_modify_sq(sq->sq, &modify_attr);\n+\tret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);\n \tif (ret) {\n-\t\tDRV_LOG(ERR, \"Can't change sq state to ready.\");\n-\t\trte_errno = ENOMEM;\n+\t\tDRV_LOG(ERR, \"Can't change SQ state to ready.\");\n+\t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n \tsq->pi = 0;\n \tsq->head = 0;\n \tsq->tail = 0;\n-\tsq->sqn = sq->sq->id;\n-\tsq->db_rec = RTE_PTR_ADD(sq->umem_buf, (uintptr_t)(wq_attr->dbr_addr));\n+\tsq->sqn = sq->sq_obj.sq->id;\n \tsq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);\n \tmlx5_aso_init_sq(sq);\n \treturn 0;\n@@ -345,8 +307,8 @@\n \t\treturn 0;\n \tsq->elts[start_head & mask].burst_size = max;\n \tdo {\n-\t\twqe = &sq->wqes[sq->head & mask];\n-\t\trte_prefetch0(&sq->wqes[(sq->head + 1) & mask]);\n+\t\twqe = &sq->sq_obj.aso_wqes[sq->head & mask];\n+\t\trte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);\n \t\t/* Fill next WQE. */\n \t\trte_spinlock_lock(&mng->resize_sl);\n \t\tpool = mng->pools[sq->next];\n@@ -371,7 +333,7 @@\n \twqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t\t\t\t MLX5_COMP_MODE_OFFSET);\n \trte_io_wmb();\n-\tsq->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);\n+\tsq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);\n \trte_wmb();\n \t*sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/\n \trte_wmb();\n@@ -418,7 +380,7 @@\n \tcq->errors++;\n \tidx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);\n \tmlx5_aso_dump_err_objs((volatile uint32_t *)cqe,\n-\t\t\t\t (volatile uint32_t *)&sq->wqes[idx]);\n+\t\t\t (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);\n }\n \n /**\n@@ -613,7 +575,7 @@\n {\n \tint retries = 1024;\n \n-\tif (!sh->aso_age_mng->aso_sq.sq)\n+\tif (!sh->aso_age_mng->aso_sq.sq_obj.sq)\n \t\treturn -EINVAL;\n \trte_errno = 0;\n \twhile (--retries) {\n", "prefixes": [ "v3", "16/19" ] }