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GET /api/patches/86037/?format=api
{ "id": 86037, "url": "http://patches.dpdk.org/api/patches/86037/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-15-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-15-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-15-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:36", "name": "[v3,14/19] net/mlx5: move rearm and clock queue SQ creation to common", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bba16f05d748791559a0bc7aecaa909546a8b731", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-15-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86037/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/86037/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6AA5A09FF;\n\tWed, 6 Jan 2021 09:22:10 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B66421608FF;\n\tWed, 6 Jan 2021 09:21:28 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 15A32160903\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:21:27 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:21:24 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgh009291;\n Wed, 6 Jan 2021 10:21:24 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 6 Jan 2021 08:19:36 +0000", "Message-Id": "<1609921181-5019-15-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 14/19] net/mlx5: move rearm and clock queue SQ\n creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for DevX SQ creation for rearm and clock queue.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 8 +--\n drivers/net/mlx5/mlx5_txpp.c | 147 +++++++++++--------------------------------\n 2 files changed, 36 insertions(+), 119 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 079cbca..0a0a943 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -615,15 +615,9 @@ struct mlx5_txpp_wq {\n \tuint32_t cq_ci:24;\n \tuint32_t arm_sn:2;\n \t/* Send Queue related data.*/\n-\tstruct mlx5_devx_obj *sq;\n-\tvoid *sq_umem;\n-\tunion {\n-\t\tvolatile void *sq_buf;\n-\t\tvolatile struct mlx5_wqe *wqes;\n-\t};\n+\tstruct mlx5_devx_sq sq_obj;\n \tuint16_t sq_size; /* Number of WQEs in the queue. */\n \tuint16_t sq_ci; /* Next WQE to execute. */\n-\tvolatile uint32_t *sq_dbrec;\n };\n \n /* Tx packet pacing internal timestamp. */\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex bd679c2..b38482d 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -129,12 +129,7 @@\n static void\n mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)\n {\n-\tif (wq->sq)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(wq->sq));\n-\tif (wq->sq_umem)\n-\t\tclaim_zero(mlx5_os_umem_dereg(wq->sq_umem));\n-\tif (wq->sq_buf)\n-\t\tmlx5_free((void *)(uintptr_t)wq->sq_buf);\n+\tmlx5_devx_sq_destroy(&wq->sq_obj);\n \tmlx5_devx_cq_destroy(&wq->cq_obj);\n \tmemset(wq, 0, sizeof(*wq));\n }\n@@ -163,6 +158,7 @@\n mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci)\n {\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n+\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;\n \tunion {\n \t\tuint32_t w32[2];\n \t\tuint64_t w64;\n@@ -171,11 +167,11 @@\n \n \twq->sq_ci = ci + 1;\n \tcs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32\n-\t\t (wq->wqes[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);\n-\tcs.w32[1] = wq->wqes[ci & (wq->sq_size - 1)].ctrl[1];\n+\t\t\t(wqe[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);\n+\tcs.w32[1] = wqe[ci & (wq->sq_size - 1)].ctrl[1];\n \t/* Update SQ doorbell record with new SQ ci. */\n \trte_compiler_barrier();\n-\t*wq->sq_dbrec = rte_cpu_to_be_32(wq->sq_ci);\n+\t*wq->sq_obj.db_rec = rte_cpu_to_be_32(wq->sq_ci);\n \t/* Make sure the doorbell record is updated. */\n \trte_wmb();\n \t/* Write to doorbel register to start processing. */\n@@ -188,7 +184,7 @@\n mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n-\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;\n+\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;\n \tuint32_t i;\n \n \tfor (i = 0; i < wq->sq_size; i += 2) {\n@@ -199,7 +195,7 @@\n \t\t/* Build SEND_EN request with slave WQE index. */\n \t\tcs = &wqe[i + 0].cseg;\n \t\tcs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);\n-\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);\n+\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);\n \t\tcs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t MLX5_COMP_MODE_OFFSET);\n \t\tcs->misc = RTE_BE32(0);\n@@ -207,11 +203,12 @@\n \t\tindex = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &\n \t\t\t((1 << MLX5_WQ_INDEX_WIDTH) - 1);\n \t\tqs->max_index = rte_cpu_to_be_32(index);\n-\t\tqs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.sq->id);\n+\t\tqs->qpn_cqn =\n+\t\t\t rte_cpu_to_be_32(sh->txpp.clock_queue.sq_obj.sq->id);\n \t\t/* Build WAIT request with slave CQE index. */\n \t\tcs = &wqe[i + 1].cseg;\n \t\tcs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);\n-\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);\n+\t\tcs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);\n \t\tcs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<\n \t\t\t\t MLX5_COMP_MODE_OFFSET);\n \t\tcs->misc = RTE_BE32(0);\n@@ -228,21 +225,23 @@\n static int\n mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n {\n-\tstruct mlx5_devx_create_sq_attr sq_attr = { 0 };\n+\tstruct mlx5_devx_create_sq_attr sq_attr = {\n+\t\t.cd_master = 1,\n+\t\t.state = MLX5_SQC_STATE_RST,\n+\t\t.tis_lst_sz = 1,\n+\t\t.tis_num = sh->tis->id,\n+\t\t.wq_attr = (struct mlx5_devx_wq_attr){\n+\t\t\t.pd = sh->pdn,\n+\t\t\t.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),\n+\t\t},\n+\t};\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n \tstruct mlx5_devx_cq_attr cq_attr = {\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),\n \t};\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;\n-\tsize_t page_size;\n-\tuint32_t umem_size, umem_dbrec;\n \tint ret;\n \n-\tpage_size = rte_mem_page_size();\n-\tif (page_size == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n-\t\treturn -ENOMEM;\n-\t}\n \t/* Create completion queue object for Rearm Queue. */\n \tret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj,\n \t\t\t\t log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr,\n@@ -253,63 +252,25 @@\n \t}\n \twq->cq_ci = 0;\n \twq->arm_sn = 0;\n-\t/*\n-\t * Allocate memory buffer for Send Queue WQEs.\n-\t * There should be no WQE leftovers in the cyclic queue.\n-\t */\n \twq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;\n \tMLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));\n-\tumem_size = MLX5_WQE_SIZE * wq->sq_size;\n-\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n-\tumem_size += MLX5_DBR_SIZE;\n-\twq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n-\t\t\t\t page_size, sh->numa_node);\n-\tif (!wq->sq_buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for Rearm Queue.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\t/* Register allocated buffer in user space with DevX. */\n-\twq->sq_umem = mlx5_os_umem_reg(sh->ctx,\n-\t\t\t\t\t (void *)(uintptr_t)wq->sq_buf,\n-\t\t\t\t\t umem_size,\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (!wq->sq_umem) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Failed to register umem for Rearm Queue.\");\n-\t\tgoto error;\n-\t}\n \t/* Create send queue object for Rearm Queue. */\n-\tsq_attr.state = MLX5_SQC_STATE_RST;\n-\tsq_attr.tis_lst_sz = 1;\n-\tsq_attr.tis_num = sh->tis->id;\n \tsq_attr.cqn = wq->cq_obj.cq->id;\n-\tsq_attr.cd_master = 1;\n-\tsq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n-\tsq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n-\tsq_attr.wq_attr.pd = sh->pdn;\n-\tsq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n-\tsq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);\n-\tsq_attr.wq_attr.dbr_umem_valid = 1;\n-\tsq_attr.wq_attr.dbr_addr = umem_dbrec;\n-\tsq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n-\tsq_attr.wq_attr.wq_umem_valid = 1;\n-\tsq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n-\tsq_attr.wq_attr.wq_umem_offset = 0;\n-\twq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);\n-\tif (!wq->sq) {\n+\t/* There should be no WQE leftovers in the cyclic queue. */\n+\tret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj,\n+\t\t\t\t log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr,\n+\t\t\t\t sh->numa_node);\n+\tif (ret) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(ERR, \"Failed to create SQ for Rearm Queue.\");\n \t\tgoto error;\n \t}\n-\twq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +\n-\t\t\t\t MLX5_SND_DBR * sizeof(uint32_t));\n \t/* Build the WQEs in the Send Queue before goto Ready state. */\n \tmlx5_txpp_fill_wqe_rearm_queue(sh);\n \t/* Change queue state to ready. */\n \tmsq_attr.sq_state = MLX5_SQC_STATE_RST;\n \tmsq_attr.state = MLX5_SQC_STATE_RDY;\n-\tret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);\n+\tret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to set SQ ready state Rearm Queue.\");\n \t\tgoto error;\n@@ -326,7 +287,7 @@\n mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)\n {\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n-\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;\n+\tstruct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;\n \tstruct mlx5_wqe_cseg *cs = &wqe->cseg;\n \tuint32_t wqe_size, opcode, i;\n \tuint8_t *dst;\n@@ -344,7 +305,7 @@\n \t\topcode = MLX5_OPCODE_NOP;\n \t}\n \tcs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */\n-\tcs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) |\n+\tcs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) |\n \t\t\t\t (wqe_size / MLX5_WSEG_SIZE));\n \tcs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);\n \tcs->misc = RTE_BE32(0);\n@@ -413,10 +374,11 @@\n \t}\n wcopy:\n \t/* Duplicate the pattern to the next WQEs. */\n-\tdst = (uint8_t *)(uintptr_t)wq->sq_buf;\n+\tdst = (uint8_t *)(uintptr_t)wq->sq_obj.umem_buf;\n \tfor (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {\n \t\tdst += wqe_size;\n-\t\trte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size);\n+\t\trte_memcpy(dst, (void *)(uintptr_t)wq->sq_obj.umem_buf,\n+\t\t\t wqe_size);\n \t}\n }\n \n@@ -432,15 +394,8 @@\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),\n \t};\n \tstruct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;\n-\tsize_t page_size;\n-\tuint32_t umem_size, umem_dbrec;\n \tint ret;\n \n-\tpage_size = rte_mem_page_size();\n-\tif (page_size == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get mem page size\");\n-\t\treturn -ENOMEM;\n-\t}\n \tsh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\t\t\t MLX5_TXPP_REARM_SQ_SIZE *\n \t\t\t\t sizeof(struct mlx5_txpp_ts),\n@@ -473,26 +428,6 @@\n \t}\n \t/* There should not be WQE leftovers in the cyclic queue. */\n \tMLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));\n-\tumem_size = MLX5_WQE_SIZE * wq->sq_size;\n-\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n-\tumem_size += MLX5_DBR_SIZE;\n-\twq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n-\t\t\t\t page_size, sh->numa_node);\n-\tif (!wq->sq_buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for Clock Queue.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\t/* Register allocated buffer in user space with DevX. */\n-\twq->sq_umem = mlx5_os_umem_reg(sh->ctx,\n-\t\t\t\t\t (void *)(uintptr_t)wq->sq_buf,\n-\t\t\t\t\t umem_size,\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (!wq->sq_umem) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Failed to register umem for Clock Queue.\");\n-\t\tgoto error;\n-\t}\n \t/* Create send queue object for Clock Queue. */\n \tif (sh->txpp.test) {\n \t\tsq_attr.tis_lst_sz = 1;\n@@ -503,37 +438,25 @@\n \t\tsq_attr.non_wire = 1;\n \t\tsq_attr.static_sq_wq = 1;\n \t}\n-\tsq_attr.state = MLX5_SQC_STATE_RST;\n \tsq_attr.cqn = wq->cq_obj.cq->id;\n \tsq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;\n \tsq_attr.wq_attr.cd_slave = 1;\n \tsq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n-\tsq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n \tsq_attr.wq_attr.pd = sh->pdn;\n-\tsq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n-\tsq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);\n-\tsq_attr.wq_attr.dbr_umem_valid = 1;\n-\tsq_attr.wq_attr.dbr_addr = umem_dbrec;\n-\tsq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n-\tsq_attr.wq_attr.wq_umem_valid = 1;\n-\tsq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);\n-\t/* umem_offset must be zero for static_sq_wq queue. */\n-\tsq_attr.wq_attr.wq_umem_offset = 0;\n-\twq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);\n-\tif (!wq->sq) {\n+\tret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size),\n+\t\t\t\t &sq_attr, sh->numa_node);\n+\tif (ret) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(ERR, \"Failed to create SQ for Clock Queue.\");\n \t\tgoto error;\n \t}\n-\twq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +\n-\t\t\t\t MLX5_SND_DBR * sizeof(uint32_t));\n \t/* Build the WQEs in the Send Queue before goto Ready state. */\n \tmlx5_txpp_fill_wqe_clock_queue(sh);\n \t/* Change queue state to ready. */\n \tmsq_attr.sq_state = MLX5_SQC_STATE_RST;\n \tmsq_attr.state = MLX5_SQC_STATE_RDY;\n \twq->sq_ci = 0;\n-\tret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);\n+\tret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to set SQ ready state Clock Queue.\");\n \t\tgoto error;\n", "prefixes": [ "v3", "14/19" ] }