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GET /api/patches/86026/?format=api
{ "id": 86026, "url": "http://patches.dpdk.org/api/patches/86026/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-3-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-3-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-3-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:24", "name": "[v3,02/19] net/mlx5: remove CQE padding device argument", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3fd5b32699649603da6f0921792b93538e02e155", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-3-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86026/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86026/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A4CE0A09FF;\n\tWed, 6 Jan 2021 09:20:37 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9183216089F;\n\tWed, 6 Jan 2021 09:20:37 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 659F9160864\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:20:36 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:20:31 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgV009291;\n Wed, 6 Jan 2021 10:20:31 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, stable@dpdk.org", "Date": "Wed, 6 Jan 2021 08:19:24 +0000", "Message-Id": "<1609921181-5019-3-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 02/19] net/mlx5: remove CQE padding device\n argument", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The data-path code doesn't take care on 'rxq_cqe_pad_en' and use padded\nCQE for any case when the system cache-line size is 128B.\n\nThis makes the argument redundant.\n\nRemove it.\n\nFixes: bc91e8db12cd (\"net/mlx5: add 128B padding of Rx completion entry\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 18 ------------------\n drivers/net/mlx5/linux/mlx5_os.c | 12 ------------\n drivers/net/mlx5/linux/mlx5_verbs.c | 2 +-\n drivers/net/mlx5/mlx5.c | 6 ------\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/windows/mlx5_os.c | 7 -------\n 6 files changed, 1 insertion(+), 45 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 3bda0f8..6950cc1 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -448,24 +448,6 @@ Driver options\n - POWER9 and ARMv8 with ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,\n ConnectX-6 Lx, BlueField and BlueField-2.\n \n-- ``rxq_cqe_pad_en`` parameter [int]\n-\n- A nonzero value enables 128B padding of CQE on RX side. The size of CQE\n- is aligned with the size of a cacheline of the core. If cacheline size is\n- 128B, the CQE size is configured to be 128B even though the device writes\n- only 64B data on the cacheline. This is to avoid unnecessary cache\n- invalidation by device's two consecutive writes on to one cacheline.\n- However in some architecture, it is more beneficial to update entire\n- cacheline with padding the rest 64B rather than striding because\n- read-modify-write could drop performance a lot. On the other hand,\n- writing extra data will consume more PCIe bandwidth and could also drop\n- the maximum throughput. It is recommended to empirically set this\n- parameter. Disabled by default.\n-\n- Supported on:\n-\n- - CPU having 128B cacheline with ConnectX-5 and BlueField.\n-\n - ``rxq_pkt_pad_en`` parameter [int]\n \n A nonzero value enables padding Rx packet to the size of cacheline on PCI\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 6812a1f..9ac1d46 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -677,7 +677,6 @@\n \tunsigned int hw_padding = 0;\n \tunsigned int mps;\n \tunsigned int cqe_comp;\n-\tunsigned int cqe_pad = 0;\n \tunsigned int tunnel_en = 0;\n \tunsigned int mpls_en = 0;\n \tunsigned int swp = 0;\n@@ -875,11 +874,6 @@\n \telse\n \t\tcqe_comp = 1;\n \tconfig->cqe_comp = cqe_comp;\n-#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n-\t/* Whether device supports 128B Rx CQE padding. */\n-\tcqe_pad = RTE_CACHE_LINE_SIZE == 128 &&\n-\t\t (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);\n-#endif\n #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n \tif (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {\n \t\ttunnel_en = ((dv_attr.tunnel_offloads_caps &\n@@ -1116,12 +1110,6 @@\n \t\tDRV_LOG(WARNING, \"Rx CQE compression isn't supported\");\n \t\tconfig->cqe_comp = 0;\n \t}\n-\tif (config->cqe_pad && !cqe_pad) {\n-\t\tDRV_LOG(WARNING, \"Rx CQE padding isn't supported\");\n-\t\tconfig->cqe_pad = 0;\n-\t} else if (config->cqe_pad) {\n-\t\tDRV_LOG(INFO, \"Rx CQE padding is enabled\");\n-\t}\n \tif (config->devx) {\n \t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);\n \t\tif (err) {\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex b52ae2e..318e39b 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -234,7 +234,7 @@\n \t\t\tdev->data->port_id);\n \t}\n #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n-\tif (priv->config.cqe_pad) {\n+\tif (RTE_CACHE_LINE_SIZE == 128) {\n \t\tcq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;\n \t\tcq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 023ef50..91492c5 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -44,9 +44,6 @@\n /* Device parameter to enable RX completion queue compression. */\n #define MLX5_RXQ_CQE_COMP_EN \"rxq_cqe_comp_en\"\n \n-/* Device parameter to enable RX completion entry padding to 128B. */\n-#define MLX5_RXQ_CQE_PAD_EN \"rxq_cqe_pad_en\"\n-\n /* Device parameter to enable padding Rx packet to cacheline size. */\n #define MLX5_RXQ_PKT_PAD_EN \"rxq_pkt_pad_en\"\n \n@@ -1625,8 +1622,6 @@ struct mlx5_dev_ctx_shared *\n \t\t}\n \t\tconfig->cqe_comp = !!tmp;\n \t\tconfig->cqe_comp_fmt = tmp;\n-\t} else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {\n-\t\tconfig->cqe_pad = !!tmp;\n \t} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {\n \t\tconfig->hw_padding = !!tmp;\n \t} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {\n@@ -1755,7 +1750,6 @@ struct mlx5_dev_ctx_shared *\n {\n \tconst char **params = (const char *[]){\n \t\tMLX5_RXQ_CQE_COMP_EN,\n-\t\tMLX5_RXQ_CQE_PAD_EN,\n \t\tMLX5_RXQ_PKT_PAD_EN,\n \t\tMLX5_RX_MPRQ_EN,\n \t\tMLX5_RX_MPRQ_LOG_STRIDE_NUM,\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 41034f5..92a5d04 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -212,7 +212,6 @@ struct mlx5_dev_config {\n \tunsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */\n \tunsigned int cqe_comp:1; /* CQE compression is enabled. */\n \tunsigned int cqe_comp_fmt:3; /* CQE compression format. */\n-\tunsigned int cqe_pad:1; /* CQE padding is enabled. */\n \tunsigned int tso:1; /* Whether TSO is supported. */\n \tunsigned int rx_vec_en:1; /* Rx vector is enabled. */\n \tunsigned int mr_ext_memseg_en:1;\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex fdd69fd..b036432 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -313,7 +313,6 @@\n \tstruct mlx5_priv *priv = NULL;\n \tint err = 0;\n \tunsigned int cqe_comp;\n-\tunsigned int cqe_pad = 0;\n \tstruct rte_ether_addr mac;\n \tchar name[RTE_ETH_NAME_MAX_LEN];\n \tint own_domain_id = 0;\n@@ -461,12 +460,6 @@\n \t\tDRV_LOG(WARNING, \"Rx CQE compression isn't supported.\");\n \t\tconfig->cqe_comp = 0;\n \t}\n-\tif (config->cqe_pad && !cqe_pad) {\n-\t\tDRV_LOG(WARNING, \"Rx CQE padding isn't supported.\");\n-\t\tconfig->cqe_pad = 0;\n-\t} else if (config->cqe_pad) {\n-\t\tDRV_LOG(INFO, \"Rx CQE padding is enabled.\");\n-\t}\n \tif (config->devx) {\n \t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);\n \t\tif (err) {\n", "prefixes": [ "v3", "02/19" ] }