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GET /api/patches/85921/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 85921,
    "url": "http://patches.dpdk.org/api/patches/85921/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-13-pnalla@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201231072247.5719-13-pnalla@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201231072247.5719-13-pnalla@marvell.com",
    "date": "2020-12-31T07:22:44",
    "name": "[12/15] net/octeontx_ep: INFO PTR mode support added.",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "114844f5397cdc1bec93d44c10098e279a4e53ad",
    "submitter": {
        "id": 2074,
        "url": "http://patches.dpdk.org/api/people/2074/?format=api",
        "name": "Pradeep Nalla",
        "email": "pnalla@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-13-pnalla@marvell.com/mbox/",
    "series": [
        {
            "id": 14507,
            "url": "http://patches.dpdk.org/api/series/14507/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14507",
            "date": "2020-12-31T07:22:32",
            "name": "Octeon Tx/Tx2 Endpoint pmd",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/14507/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/85921/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/85921/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DFFF5A0A00;\n\tThu, 31 Dec 2020 08:24:19 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 71649140D1E;\n\tThu, 31 Dec 2020 08:23:09 +0100 (CET)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B3A20140CEC\n for <dev@dpdk.org>; Thu, 31 Dec 2020 08:23:00 +0100 (CET)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BV7G0IN022182 for <dev@dpdk.org>; Wed, 30 Dec 2020 23:22:59 -0800",
            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx58-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 30 Dec 2020 23:22:59 -0800",
            "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:22:58 -0800",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 30 Dec 2020 23:22:58 -0800",
            "from localhost.localdomain (unknown [10.111.145.157])\n by maili.marvell.com (Postfix) with ESMTP id 3968C3F7041;\n Wed, 30 Dec 2020 23:22:58 -0800 (PST)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=Z51CNQwmNsdNzopUOCF7wMeGef+w+2YAtWW7EguuFTI=;\n b=j/aaTvkfk+2QKk9ZmK9W7qeRnH2Yn8H2ierLC5QWj547ru7QoKeao/xrICCnuM9icAnN\n wvsIZvu3gqb1IPoxr3mW1DDw7JPSHYzsAM2jgOgGxq9hyQuCOASftnAikpaSN7JVRZsb\n zgmcHH7LVoTdn1AUCzzLuv0XqaolLQLkJhLuhRa+qW8AMrbdl9glZjdz1Kiy/V83QP8B\n xY8ya43dYIeN46jfXd/DZzma4SS9ve5t7MjTcGqYuDKbLw04e2PrXDcO103txXXw9zqX\n fXx7V+Og4gVmqGG2+0KRd89A2QaR9ordoGAehtIt9lltT1Bpg+yHg6s8tWDVDGRiPDvQ 6w==",
        "From": "\"Nalla, Pradeep\" <pnalla@marvell.com>",
        "To": "\"Nalla, Pradeep\" <pnalla@marvell.com>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>",
        "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>",
        "Date": "Thu, 31 Dec 2020 07:22:44 +0000",
        "Message-ID": "<20201231072247.5719-13-pnalla@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20201231072247.5719-1-pnalla@marvell.com>",
        "References": "<20201231072247.5719-1-pnalla@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-31_02:2020-12-30,\n 2020-12-31 signatures=0",
        "Subject": "[dpdk-dev] [PATCH 12/15] net/octeontx_ep: INFO PTR mode support\n added.",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: \"Nalla Pradeep\" <pnalla@marvell.com>\n\nHardware can be programmed to write the meta data of incoming packet in\nthe same buffer it uses to fill the packet(BUF PTR mode) or a different\nbuffer (INFO PTR mode).\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/meson.build     |  2 +-\n drivers/net/octeontx_ep/otx_ep_common.h |  8 ++++\n drivers/net/octeontx_ep/otx_ep_rxtx.c   | 55 ++++++++++++++++++++++++-\n 3 files changed, 63 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build\nindex 8d804a0398..08e8131bfe 100644\n--- a/drivers/net/octeontx_ep/meson.build\n+++ b/drivers/net/octeontx_ep/meson.build\n@@ -9,7 +9,7 @@ sources = files(\n                'otx_ep_rxtx.c',\n                )\n \n-extra_flags = []\n+extra_flags = ['-DBUFPTR_ONLY_MODE']\n # This integrated controller runs only on a arm64 machine, remove 32bit warnings\n if not dpdk_conf.get('RTE_ARCH_64')\n         extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 978cceab01..0b6e7e2042 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -239,11 +239,19 @@ union otx_ep_rh {\n  *  about the packet.\n  */\n struct otx_ep_droq_info {\n+#ifndef BUFPTR_ONLY_MODE\n+\t/* The Output Receive Header. */\n+\tunion otx_ep_rh rh;\n+\n+\t/* The Length of the packet. */\n+\tuint64_t length;\n+#else\n \t/* The Length of the packet. */\n \tuint64_t length;\n \n \t/* The Output Receive Header. */\n \tunion otx_ep_rh rh;\n+#endif\n };\n #define OTX_EP_DROQ_INFO_SIZE\t(sizeof(struct otx_ep_droq_info))\n \ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.c b/drivers/net/octeontx_ep/otx_ep_rxtx.c\nindex 4ffe0b8546..279ab9f6d6 100644\n--- a/drivers/net/octeontx_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.c\n@@ -215,6 +215,13 @@ otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \trte_free(droq->recv_buf_list);\n \tdroq->recv_buf_list = NULL;\n \n+#ifndef BUFPTR_ONLY_MODE\n+\tif (droq->info_mz) {\n+\t\totx_ep_dmazone_free(droq->info_mz);\n+\t\tdroq->info_mz = NULL;\n+\t}\n+#endif\n+\n \tif (droq->desc_ring_mz) {\n \t\totx_ep_dmazone_free(droq->desc_ring_mz);\n \t\tdroq->desc_ring_mz = NULL;\n@@ -249,6 +256,13 @@ otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq)\n \t\t}\n \n \t\tdroq->recv_buf_list[idx] = buf;\n+#ifndef BUFPTR_ONLY_MODE\n+\t\tdroq->info_list[idx].length = 0;\n+\n+\t\t/* Map ring buffers into memory */\n+\t\tdesc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +\n+\t\t\t(idx * OTX_EP_DROQ_INFO_SIZE));\n+#endif\n \t\tinfo = rte_pktmbuf_mtod(buf, struct otx_ep_droq_info *);\n \t\tmemset(info, 0, sizeof(*info));\n \t\tdesc_ring[idx].buffer_ptr = rte_mbuf_data_iova_default(buf);\n@@ -259,6 +273,28 @@ otx_ep_droq_setup_ring_buffers(struct otx_ep_droq *droq)\n \treturn 0;\n }\n \n+#ifndef BUFPTR_ONLY_MODE\n+static void *\n+otx_ep_alloc_info_buffer(struct otx_ep_device *otx_ep __rte_unused,\n+\tstruct otx_ep_droq *droq, unsigned int socket_id)\n+{\n+\tdroq->info_mz = rte_memzone_reserve_aligned(\"OQ_info_list\",\n+\t\t\t\t(droq->nb_desc * OTX_EP_DROQ_INFO_SIZE),\n+\t\t\t\tsocket_id,\n+\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\tOTX_EP_PCI_RING_ALIGN);\n+\n+\tif (droq->info_mz == NULL)\n+\t\treturn NULL;\n+\n+\tdroq->info_list_dma = droq->info_mz->iova;\n+\tdroq->info_alloc_size = droq->info_mz->len;\n+\tdroq->info_base_addr = (size_t)droq->info_mz->addr;\n+\n+\treturn droq->info_mz->addr;\n+}\n+#endif\n+\n /* OQ initialization */\n static int\n otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n@@ -301,6 +337,16 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n \t\t    q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);\n \totx_ep_dbg(\"OQ[%d]: num_desc: %d\\n\", q_no, droq->nb_desc);\n \n+#ifndef BUFPTR_ONLY_MODE\n+\t/* OQ info_list set up */\n+\tdroq->info_list = otx_ep_alloc_info_buffer(otx_ep, droq, socket_id);\n+\tif (droq->info_list == NULL) {\n+\t\totx_ep_err(\"memory allocation failed for OQ[%d] info_list\\n\",\n+\t\t\t   q_no);\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+#endif\n \t/* OQ buf_list set up */\n \tdroq->recv_buf_list = rte_zmalloc_socket(\"recv_buf_list\",\n \t\t\t\t(droq->nb_desc * sizeof(struct rte_mbuf *)),\n@@ -836,7 +882,10 @@ otx_ep_droq_refill(struct otx_ep_droq *droq)\n \t\tdesc_ring[droq->refill_idx].buffer_ptr =\n \t\t\t\t\trte_mbuf_data_iova_default(buf);\n \n-\n+#ifndef BUFPTR_ONLY_MODE\n+\t\t/* Reset any previous values in the length field. */\n+\t\tdroq->info_list[droq->refill_idx].length = 0;\n+#endif\n \t\tdroq->refill_idx = otx_ep_incr_index(droq->refill_idx, 1,\n \t\t\t\tdroq->nb_desc);\n \n@@ -862,6 +911,9 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n \n \tdroq_pkt  = droq->recv_buf_list[droq->read_idx];\n \tdroq_pkt2  = droq->recv_buf_list[droq->read_idx];\n+#ifndef BUFPTR_ONLY_MODE\n+\tinfo = &droq->info_list[droq->read_idx];\n+#else\n \tinfo = rte_pktmbuf_mtod(droq_pkt, struct otx_ep_droq_info *);\n \t/* make sure info is available */\n \trte_rmb();\n@@ -893,6 +945,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n \t\tinfo2 = rte_pktmbuf_mtod(droq_pkt2, struct otx_ep_droq_info *);\n \t\trte_prefetch_non_temporal((const void *)info2);\n \t}\n+#endif\n \n \tinfo->length = rte_bswap64(info->length);\n \t/* Deduce the actual data size */\n",
    "prefixes": [
        "12/15"
    ]
}