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GET /api/patches/85865/?format=api
{ "id": 85865, "url": "http://patches.dpdk.org/api/patches/85865/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609231944-29274-9-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609231944-29274-9-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609231944-29274-9-git-send-email-michaelba@nvidia.com", "date": "2020-12-29T08:52:15", "name": "[v2,08/17] net/mlx5: move Rx CQ creation to common", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b9d19a5ceecf305a476774b1c9c1b4abaf8efd72", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609231944-29274-9-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14490, "url": "http://patches.dpdk.org/api/series/14490/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14490", "date": "2020-12-29T08:52:18", "name": "common/mlx5: share DevX resources creations", "version": 2, "mbox": "http://patches.dpdk.org/series/14490/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85865/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/85865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 89B76A09FF;\n\tTue, 29 Dec 2020 09:54:15 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0A9ECCA4E;\n\tTue, 29 Dec 2020 09:52:45 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 4F633C9B0\n for <dev@dpdk.org>; Tue, 29 Dec 2020 09:52:35 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 29 Dec 2020 10:52:32 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BT8qWwe022593;\n Tue, 29 Dec 2020 10:52:32 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Tue, 29 Dec 2020 08:52:15 +0000", "Message-Id": "<1609231944-29274-9-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609231944-29274-1-git-send-email-michaelba@nvidia.com>", "References": "<1608205475-20067-2-git-send-email-michaelba@nvidia.com>\n <1609231944-29274-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v2 08/17] net/mlx5: move Rx CQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for Rx CQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 8 ---\n drivers/net/mlx5/mlx5.h | 3 +-\n drivers/net/mlx5/mlx5_devx.c | 142 +++++++++++++------------------------------\n drivers/net/mlx5/mlx5_rxtx.h | 4 --\n 4 files changed, 42 insertions(+), 115 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 52a8a25..3c7e5d2 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -938,14 +938,6 @@ struct mlx5_dev_ctx_shared *\n \t\tgoto error;\n \t}\n \tif (sh->devx) {\n-\t\t/* Query the EQN for this core. */\n-\t\terr = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);\n-\t\tif (err) {\n-\t\t\trte_errno = errno;\n-\t\t\tDRV_LOG(ERR, \"Failed to query event queue number %d.\",\n-\t\t\t\trte_errno);\n-\t\t\tgoto error;\n-\t\t}\n \t\terr = mlx5_os_get_pdn(sh->pd, &sh->pdn);\n \t\tif (err) {\n \t\t\tDRV_LOG(ERR, \"Fail to extract pdn from PD\");\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 2e75498..9a59c26 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -679,7 +679,6 @@ struct mlx5_dev_ctx_shared {\n \tuint16_t bond_dev; /* Bond primary device id. */\n \tuint32_t devx:1; /* Opened with DV. */\n \tuint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */\n-\tuint32_t eqn; /* Event Queue number. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tvoid *ctx; /* Verbs/DV/DevX context. */\n \tvoid *pd; /* Protection Domain. */\n@@ -787,7 +786,7 @@ struct mlx5_rxq_obj {\n \t\t};\n \t\tstruct {\n \t\t\tstruct mlx5_devx_obj *rq; /* DevX Rx Queue object. */\n-\t\t\tstruct mlx5_devx_obj *devx_cq; /* DevX CQ object. */\n+\t\t\tstruct mlx5_devx_cq cq_obj; /* DevX CQ object. */\n \t\t\tvoid *devx_channel;\n \t\t};\n \t};\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 9560f2b..6ad70f2 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -172,30 +172,17 @@\n }\n \n /**\n- * Release the resources allocated for the Rx CQ DevX object.\n+ * Destroy the Rx queue DevX object.\n *\n- * @param rxq_ctrl\n- * DevX Rx queue object.\n+ * @param rxq_obj\n+ * Rxq object to destroy.\n */\n static void\n-mlx5_rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n+mlx5_rxq_release_devx_resources(struct mlx5_rxq_ctrl *rxq_ctrl)\n {\n-\tstruct mlx5_devx_dbr_page *dbr_page = rxq_ctrl->cq_dbrec_page;\n-\n-\tif (rxq_ctrl->cq_umem) {\n-\t\tmlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);\n-\t\trxq_ctrl->cq_umem = NULL;\n-\t}\n-\tif (rxq_ctrl->rxq.cqes) {\n-\t\trte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);\n-\t\trxq_ctrl->rxq.cqes = NULL;\n-\t}\n-\tif (dbr_page) {\n-\t\tclaim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,\n-\t\t\t\t\t mlx5_os_get_umem_id(dbr_page->umem),\n-\t\t\t\t\t rxq_ctrl->cq_dbr_offset));\n-\t\trxq_ctrl->cq_dbrec_page = NULL;\n-\t}\n+\tmlx5_rxq_release_devx_rq_resources(rxq_ctrl);\n+\tmlx5_devx_cq_destroy(&rxq_ctrl->obj->cq_obj);\n+\tmemset(&rxq_ctrl->obj->cq_obj, 0, sizeof(rxq_ctrl->obj->cq_obj));\n }\n \n /**\n@@ -213,14 +200,12 @@\n \t\tmlx5_devx_modify_rq(rxq_obj, MLX5_RXQ_MOD_RDY2RST);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t} else {\n-\t\tMLX5_ASSERT(rxq_obj->devx_cq);\n+\t\tMLX5_ASSERT(rxq_obj->cq_obj);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));\n \t\tif (rxq_obj->devx_channel)\n \t\t\tmlx5_glue->devx_destroy_event_channel\n \t\t\t\t\t\t\t(rxq_obj->devx_channel);\n-\t\tmlx5_rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);\n-\t\tmlx5_rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);\n+\t\tmlx5_rxq_release_devx_resources(rxq_obj->rxq_ctrl);\n \t}\n }\n \n@@ -249,7 +234,7 @@\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n-\tif (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->devx_cq) {\n+\tif (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->cq_obj.cq) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n@@ -327,7 +312,7 @@\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct mlx5_devx_create_rq_attr rq_attr = { 0 };\n \tuint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);\n-\tuint32_t cqn = rxq_ctrl->obj->devx_cq->id;\n+\tuint32_t cqn = rxq_ctrl->obj->cq_obj.cq->id;\n \tstruct mlx5_devx_dbr_page *dbr_page;\n \tint64_t dbr_offset;\n \tuint32_t wq_size = 0;\n@@ -410,31 +395,23 @@\n * Queue index in DPDK Rx queue array.\n *\n * @return\n- * The DevX CQ object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_devx_obj *\n+static int\n mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)\n {\n-\tstruct mlx5_devx_obj *cq_obj = 0;\n+\tstruct mlx5_devx_cq *cq_obj = 0;\n \tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\tsize_t page_size = rte_mem_page_size();\n \tunsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);\n-\tstruct mlx5_devx_dbr_page *dbr_page;\n-\tint64_t dbr_offset;\n-\tvoid *buf = NULL;\n-\tuint16_t event_nums[1] = {0};\n \tuint32_t log_cqe_n;\n-\tuint32_t cq_size;\n+\tuint16_t event_nums[1] = { 0 };\n \tint ret = 0;\n \n-\tif (page_size == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get page_size.\");\n-\t\tgoto error;\n-\t}\n \tif (priv->config.cqe_comp && !rxq_data->hw_timestamp &&\n \t !rxq_data->lro) {\n \t\tcq_attr.cqe_comp_en = 1u;\n@@ -489,71 +466,37 @@\n \t}\n \tif (priv->config.cqe_pad)\n \t\tcq_attr.cqe_size = MLX5_CQE_SIZE_128B;\n+\tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);\n \tlog_cqe_n = log2above(cqe_n);\n-\tcq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);\n-\tbuf = rte_calloc_socket(__func__, 1, cq_size, page_size,\n-\t\t\t\trxq_ctrl->socket);\n-\tif (!buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n-\t\tgoto error;\n-\t}\n-\trxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;\n-\trxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,\n-\t\t\t\t\t\t cq_size,\n-\t\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (!rxq_ctrl->cq_umem) {\n-\t\tDRV_LOG(ERR, \"Failed to register umem for CQ.\");\n-\t\tgoto error;\n-\t}\n-\t/* Allocate CQ door-bell. */\n-\tdbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs, &dbr_page);\n-\tif (dbr_offset < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\trxq_ctrl->cq_dbr_offset = dbr_offset;\n-\trxq_ctrl->cq_dbrec_page = dbr_page;\n-\trxq_data->cq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n-\t\t\t (uintptr_t)rxq_ctrl->cq_dbr_offset);\n-\trxq_data->cq_uar =\n-\t\t\tmlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);\n \t/* Create CQ using DevX API. */\n-\tcq_attr.eqn = priv->sh->eqn;\n-\tcq_attr.uar_page_id =\n-\t\t\tmlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);\n-\tcq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);\n-\tcq_attr.q_umem_valid = 1;\n-\tcq_attr.log_cq_size = log_cqe_n;\n-\tcq_attr.log_page_size = rte_log2_u32(page_size);\n-\tcq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;\n-\tcq_attr.db_umem_id = mlx5_os_get_umem_id(dbr_page->umem);\n-\tcq_attr.db_umem_valid = 1;\n-\tcq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);\n-\tif (!cq_obj)\n-\t\tgoto error;\n+\tret = mlx5_devx_cq_create(sh->ctx, &rxq_ctrl->obj->cq_obj, log_cqe_n,\n+\t\t\t\t &cq_attr, sh->numa_node);\n+\tif (ret)\n+\t\treturn ret;\n+\tcq_obj = &rxq_ctrl->obj->cq_obj;\n+\trxq_data->cqes = (volatile struct mlx5_cqe (*)[])\n+\t\t\t\t\t\t\t(uintptr_t)cq_obj->cqes;\n+\trxq_data->cq_db = cq_obj->db_rec;\n+\trxq_data->cq_uar = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);\n \trxq_data->cqe_n = log_cqe_n;\n-\trxq_data->cqn = cq_obj->id;\n+\trxq_data->cqn = cq_obj->cq->id;\n \tif (rxq_ctrl->obj->devx_channel) {\n \t\tret = mlx5_glue->devx_subscribe_devx_event\n-\t\t\t\t\t\t(rxq_ctrl->obj->devx_channel,\n-\t\t\t\t\t\t cq_obj->obj,\n-\t\t\t\t\t\t sizeof(event_nums),\n-\t\t\t\t\t\t event_nums,\n-\t\t\t\t\t\t (uint64_t)(uintptr_t)cq_obj);\n+\t\t\t\t\t (rxq_ctrl->obj->devx_channel,\n+\t\t\t\t\t cq_obj->cq->obj,\n+\t\t\t\t\t sizeof(event_nums),\n+\t\t\t\t\t event_nums,\n+\t\t\t\t\t (uint64_t)(uintptr_t)cq_obj->cq);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Fail to subscribe CQ to event channel.\");\n-\t\t\trte_errno = errno;\n-\t\t\tgoto error;\n+\t\t\tret = errno;\n+\t\t\tmlx5_devx_cq_destroy(cq_obj);\n+\t\t\tmemset(cq_obj, 0, sizeof(*cq_obj));\n+\t\t\trte_errno = ret;\n+\t\t\treturn -ret;\n \t\t}\n \t}\n-\t/* Initialise CQ to 1's to mark HW ownership for all CQEs. */\n-\tmemset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);\n-\treturn cq_obj;\n-error:\n-\tif (cq_obj)\n-\t\tmlx5_devx_cmd_destroy(cq_obj);\n-\tmlx5_rxq_release_devx_cq_resources(rxq_ctrl);\n-\treturn NULL;\n+\treturn 0;\n }\n \n /**\n@@ -657,8 +600,8 @@\n \t\ttmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);\n \t}\n \t/* Create CQ using DevX API. */\n-\ttmpl->devx_cq = mlx5_rxq_create_devx_cq_resources(dev, idx);\n-\tif (!tmpl->devx_cq) {\n+\tret = mlx5_rxq_create_devx_cq_resources(dev, idx);\n+\tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n@@ -684,12 +627,9 @@\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n \tif (tmpl->rq)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->rq));\n-\tif (tmpl->devx_cq)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(tmpl->devx_cq));\n \tif (tmpl->devx_channel)\n \t\tmlx5_glue->devx_destroy_event_channel(tmpl->devx_channel);\n-\tmlx5_rxq_release_devx_rq_resources(rxq_ctrl);\n-\tmlx5_rxq_release_devx_cq_resources(rxq_ctrl);\n+\tmlx5_rxq_release_devx_resources(rxq_ctrl);\n \trte_errno = ret; /* Restore rte_errno. */\n \treturn -rte_errno;\n }\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 7989a50..6a71791 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -196,11 +196,7 @@ struct mlx5_rxq_ctrl {\n \tstruct mlx5_devx_dbr_page *rq_dbrec_page;\n \tuint64_t rq_dbr_offset;\n \t/* Storing RQ door-bell information, needed when freeing door-bell. */\n-\tstruct mlx5_devx_dbr_page *cq_dbrec_page;\n-\tuint64_t cq_dbr_offset;\n-\t/* Storing CQ door-bell information, needed when freeing door-bell. */\n \tvoid *wq_umem; /* WQ buffer registration info. */\n-\tvoid *cq_umem; /* CQ buffer registration info. */\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n };\n", "prefixes": [ "v2", "08/17" ] }