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GET /api/patches/85504/?format=api
{ "id": 85504, "url": "http://patches.dpdk.org/api/patches/85504/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201219075454.40266-5-jingjing.wu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201219075454.40266-5-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201219075454.40266-5-jingjing.wu@intel.com", "date": "2020-12-19T07:54:53", "name": "[v1,4/5] net/iavf_be: add Rx Tx burst support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3886b4377c2a1147dcf2bdb6931ba4311ac9bb9b", "submitter": { "id": 47, "url": "http://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201219075454.40266-5-jingjing.wu@intel.com/mbox/", "series": [ { "id": 14385, "url": "http://patches.dpdk.org/api/series/14385/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14385", "date": "2020-12-19T07:54:49", "name": "introduce iavf backend driver", "version": 1, "mbox": "http://patches.dpdk.org/series/14385/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85504/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/85504/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 99A86A04B5;\n\tSat, 19 Dec 2020 09:07:30 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7FE39CB97;\n\tSat, 19 Dec 2020 09:06:15 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id F040DCB35\n for <dev@dpdk.org>; Sat, 19 Dec 2020 09:06:11 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Dec 2020 00:06:11 -0800", "from dpdk-wujingji.sh.intel.com ([10.67.119.101])\n by fmsmga001.fm.intel.com with ESMTP; 19 Dec 2020 00:06:09 -0800" ], "IronPort-SDR": [ "\n AABNqbE93W1ZoKEqwZTD5N8FJ5XuBPF00VkLyu1AFUTHG7fg/Ypd0MDITdqkCMX6Qhe1n9zv7s\n rl0pzv0TqUcw==", "\n B+oLMucGviJFvSigv7ycoOppdfeZDa/5+Mhi18WH2AUSjmvFGC5bgqm7ZfNH+O28DmIneBfEFg\n xt637+1vyf9Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9839\"; a=\"155353443\"", "E=Sophos;i=\"5.78,432,1599548400\"; d=\"scan'208\";a=\"155353443\"", "E=Sophos;i=\"5.78,432,1599548400\"; d=\"scan'208\";a=\"454532478\"" ], "X-ExtLoop1": "1", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Cc": "jingjing.wu@intel.com, beilei.xing@intel.com, chenbo.xia@intel.com,\n xiuchun.lu@intel.com, Miao Li <miao.li@intel.com>", "Date": "Sat, 19 Dec 2020 15:54:53 +0800", "Message-Id": "<20201219075454.40266-5-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 2.21.1", "In-Reply-To": "<20201219075454.40266-1-jingjing.wu@intel.com>", "References": "<20201219075454.40266-1-jingjing.wu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v1 4/5] net/iavf_be: add Rx Tx burst support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable packets revcieve and transmit functions.\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\nSigned-off-by: Xiuchun Lu <xiuchun.lu@intel.com>\nSigned-off-by: Miao Li <miao.li@intel.com>\n---\n drivers/net/iavf_be/iavf_be_ethdev.c | 3 +\n drivers/net/iavf_be/iavf_be_rxtx.c | 329 +++++++++++++++++++++++++++\n drivers/net/iavf_be/iavf_be_rxtx.h | 60 +++++\n 3 files changed, 392 insertions(+)", "diff": "diff --git a/drivers/net/iavf_be/iavf_be_ethdev.c b/drivers/net/iavf_be/iavf_be_ethdev.c\nindex e809f52312..c259c7807e 100644\n--- a/drivers/net/iavf_be/iavf_be_ethdev.c\n+++ b/drivers/net/iavf_be/iavf_be_ethdev.c\n@@ -862,6 +862,9 @@ eth_dev_iavfbe_create(struct rte_vdev_device *dev,\n \trte_ether_addr_copy(addr, ð_dev->data->mac_addrs[0]);\n \n \teth_dev->dev_ops = &iavfbe_eth_dev_ops;\n+\teth_dev->rx_pkt_burst = &iavfbe_recv_pkts;\n+\teth_dev->tx_pkt_burst = &iavfbe_xmit_pkts;\n+\teth_dev->tx_pkt_prepare = &iavfbe_prep_pkts;\n \n \teth_dev->data->dev_link = iavfbe_link;\n \teth_dev->data->numa_node = dev->device.numa_node;\ndiff --git a/drivers/net/iavf_be/iavf_be_rxtx.c b/drivers/net/iavf_be/iavf_be_rxtx.c\nindex 72cbead45a..d78f0f23eb 100644\n--- a/drivers/net/iavf_be/iavf_be_rxtx.c\n+++ b/drivers/net/iavf_be/iavf_be_rxtx.c\n@@ -160,3 +160,332 @@ iavfbe_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tqinfo->conf.offloads = DEV_TX_OFFLOAD_MULTI_SEGS;\n \tqinfo->conf.tx_deferred_start = false;\n }\n+\n+static inline void\n+iavfbe_recv_offload(struct rte_mbuf *m,\n+\tuint16_t cmd, uint32_t offset)\n+{\n+\tm->l2_len = offset & IAVF_TXD_QW1_MACLEN_MASK >>\n+\t\tIAVF_TX_DESC_LENGTH_MACLEN_SHIFT << 1;\n+\tm->l3_len = offset & IAVF_TXD_QW1_IPLEN_MASK >>\n+\t\tIAVF_TX_DESC_LENGTH_IPLEN_SHIFT << 2;\n+\tm->l4_len = offset & IAVF_TXD_QW1_L4LEN_MASK >>\n+\t\tIAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT << 2;\n+\n+\tswitch (cmd & IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM) {\n+\tcase IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM:\n+\t\tm->ol_flags = PKT_TX_IP_CKSUM;\n+\t\tbreak;\n+\tcase IAVF_TX_DESC_CMD_IIPT_IPV4:\n+\t\tm->ol_flags = PKT_TX_IPV4;\n+\t\tbreak;\n+\tcase IAVF_TX_DESC_CMD_IIPT_IPV6:\n+\t\tm->ol_flags = PKT_TX_IPV6;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tswitch (cmd & IAVF_TX_DESC_CMD_L4T_EOFT_UDP) {\n+\tcase IAVF_TX_DESC_CMD_L4T_EOFT_UDP:\n+\t\tm->ol_flags |= PKT_TX_UDP_CKSUM;\n+\t\tbreak;\n+\tcase IAVF_TX_DESC_CMD_L4T_EOFT_SCTP:\n+\t\tm->ol_flags |= PKT_TX_SCTP_CKSUM;\n+\t\tbreak;\n+\tcase IAVF_TX_DESC_CMD_L4T_EOFT_TCP:\n+\t\tm->ol_flags |= PKT_TX_TCP_CKSUM;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/* RX function */\n+uint16_t\n+iavfbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct iavfbe_rx_queue *rxq = (struct iavfbe_rx_queue *)rx_queue;\n+\tstruct iavfbe_adapter *adapter = (struct iavfbe_adapter *)rxq->adapter;\n+\tuint32_t nb_rx = 0;\n+\tuint16_t head, tail;\n+\tuint16_t cmd;\n+\tuint32_t offset;\n+\tvolatile struct iavf_tx_desc *ring_dma;\n+\tstruct rte_ether_addr *ea = NULL;\n+\tuint64_t ol_flags, tso_segsz = 0;\n+\n+\tif (unlikely(rte_atomic32_read(&rxq->enable) == 0)) {\n+\t\t/* RX queue is not enable currently */\n+\t\treturn 0;\n+\t}\n+\n+\tring_dma = rxq->tx_ring;\n+\thead = rxq->tx_head;\n+\ttail = (uint16_t)IAVFBE_READ_32(rxq->qtx_tail);\n+\n+\twhile (head != tail && nb_rx < nb_pkts) {\n+\t\tvolatile struct iavf_tx_desc *d;\n+\t\tvoid *desc_addr;\n+\t\tuint64_t data_len, tmp;\n+\t\tstruct rte_mbuf *cur, *rxm, *first = NULL;\n+\n+\t\tol_flags = 0;\n+\t\twhile (1) {\n+\t\t\td = &ring_dma[head];\n+\t\t\thead++;\n+\n+\t\t\tif (unlikely(head == rxq->nb_rx_desc))\n+\t\t\t\thead = 0;\n+\n+\t\t\tif ((head & 0x3) == 0) {\n+\t\t\t\trte_prefetch0(&ring_dma[head]);\n+\t\t\t}\n+\n+\t\t\tif ((d->cmd_type_offset_bsz &\n+\t\t\t IAVF_TXD_QW1_DTYPE_MASK) ==\n+\t\t\t IAVF_TX_DESC_DTYPE_CONTEXT) {\n+\t\t\t\tol_flags = PKT_TX_TCP_SEG;\n+\t\t\t\ttso_segsz = (d->cmd_type_offset_bsz &\n+\t\t\t\t\t IAVF_TXD_CTX_QW1_MSS_MASK) >>\n+\t\t\t\t\t IAVF_TXD_CTX_QW1_MSS_SHIFT;\n+\t\t\t\td = &ring_dma[head];\n+\t\t\t\thead++;\n+\t\t\t}\n+\n+\t\t\tcmd = (d->cmd_type_offset_bsz &IAVF_TXD_QW1_CMD_MASK) >>\n+\t\t\t\tIAVF_TXD_QW1_CMD_SHIFT;\n+\t\t\toffset = (d->cmd_type_offset_bsz & IAVF_TXD_QW1_OFFSET_MASK) >>\n+\t\t\t\tIAVF_TXD_QW1_OFFSET_SHIFT;\n+\n+\t\t\trxm = rte_pktmbuf_alloc(rxq->mp);\n+\t\t\tif (unlikely(rxm == NULL)) {\n+\t\t\t\tIAVF_BE_LOG(ERR, \"[%s] failed to allocate mbuf\\n\", __func__);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tdata_len = (rte_le_to_cpu_64(d->cmd_type_offset_bsz)\n+\t\t\t\t\t\t& IAVF_TXD_QW1_TX_BUF_SZ_MASK)\n+\t\t\t\t>> IAVF_TXD_QW1_TX_BUF_SZ_SHIFT;\n+\t\t\tif (data_len > rte_pktmbuf_tailroom(rxm)) {\n+\t\t\t\trte_pktmbuf_free(rxm);\n+\t\t\t\trte_pktmbuf_free(first);\n+\t\t\t\treturn nb_rx;\n+\t\t\t}\n+\t\t\ttmp = data_len;\n+\t\t\tdesc_addr = (void *)(uintptr_t)rte_iavf_emu_get_dma_vaddr(\n+\t\t\t\tadapter->mem_table, d->buffer_addr, &tmp);\n+\n+\t\t\trte_prefetch0(desc_addr);\n+\t\t\trte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));\n+\n+\t\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n+\n+\t\t\trte_memcpy(rte_pktmbuf_mtod(rxm, void *), desc_addr, data_len);\n+\n+\t\t\trxm->nb_segs = 1;\n+\t\t\trxm->next = NULL;\n+\t\t\trxm->pkt_len = data_len;\n+\t\t\trxm->data_len = data_len;\n+\n+\t\t\tif (cmd & IAVF_TX_DESC_CMD_IL2TAG1)\n+\t\t\t\trxm->vlan_tci = (d->cmd_type_offset_bsz &\n+\t\t\t\t\t\t IAVF_TXD_QW1_L2TAG1_MASK) >>\n+\t\t\t\t\t\tIAVF_TXD_QW1_TX_BUF_SZ_SHIFT;\n+\n+\t\t\tif (cmd & IAVF_TX_DESC_CMD_RS)\n+\t\t\t\td->cmd_type_offset_bsz =\n+\t\t\t\t\trte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);\n+\n+\t\t\tif (!first) {\n+\t\t\t\tfirst = rxm;\n+\t\t\t\tcur = rxm;\n+\t\t\t\tiavfbe_recv_offload(rxm, cmd, offset);\n+\t\t\t\t/* TSO enabled */\n+\t\t\t\tif (ol_flags & PKT_TX_TCP_SEG) {\n+\t\t\t\t\trxm->tso_segsz = tso_segsz;\n+\t\t\t\t\trxm->ol_flags |= ol_flags;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tfirst->pkt_len += (uint32_t)data_len;\n+\t\t\t\tfirst->nb_segs++;\n+\t\t\t\tcur->next = rxm;\n+\t\t\t\tcur = rxm;\n+\t\t\t}\n+\n+\t\t\tif (cmd & IAVF_TX_DESC_CMD_EOP)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif ((!(ol_flags & PKT_TX_TCP_SEG)) &&\n+\t\t (first->pkt_len > rxq->max_pkt_len)) {\n+\t\t\trte_pktmbuf_free(first);\n+\t\t\treturn nb_rx;\n+\t\t}\n+\n+\t\trx_pkts[nb_rx] = first;\n+\t\tnb_rx++;\n+\n+\t\t/* Count multicast and broadcast */\n+\t\tea = rte_pktmbuf_mtod(first, struct rte_ether_addr *);\n+\t\tif (rte_is_multicast_ether_addr(ea)) {\n+\t\t\tif (rte_is_broadcast_ether_addr(ea))\n+\t\t\t\trxq->stats.recv_broad_num++;\n+\t\t\telse\n+\t\t\t\trxq->stats.recv_multi_num++;\n+\t\t}\n+\n+\t\trxq->stats.recv_pkt_num++;\n+\t\trxq->stats.recv_bytes += first->pkt_len;\n+\t}\n+\n+\trxq->tx_head = head;\n+\treturn nb_rx;\n+}\n+\n+/* TX function */\n+uint16_t\n+iavfbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct iavfbe_tx_queue *txq = (struct iavfbe_tx_queue *)tx_queue;\n+\tstruct iavfbe_adapter *adapter = (struct iavfbe_adapter *)txq->adapter;\n+\tvolatile union iavf_rx_desc *ring_dma;\n+\tvolatile union iavf_rx_desc *d;\n+\tstruct rte_ether_addr *ea = NULL;\n+\tstruct rte_mbuf *pkt, *m;\n+\tuint16_t head, tail;\n+\tuint16_t nb_tx, nb_avail; /* number of avail desc */\n+\tvoid *desc_addr;\n+\tuint64_t len, data_len;\n+\tuint32_t pkt_len;\n+\tuint64_t qword1;\n+\n+\tif (unlikely(rte_atomic32_read(&txq->enable) == 0)) {\n+\t\t/* TX queue is not enable currently */\n+\t\treturn 0;\n+\t}\n+\n+\tnb_tx = 0;\n+\tlen = 1;\n+\thead = txq->rx_head;\n+\tring_dma = txq->rx_ring;\n+\ttail = (uint16_t)IAVFBE_READ_32(txq->qrx_tail);\n+\tnb_avail = (tail >= head) ?\n+\t\t(tail - head) : (txq->nb_tx_desc - tail + head);\n+\n+\twhile (nb_avail > 0 && nb_tx < nb_pkts) {\n+\t\tpkt = tx_pkts[nb_tx];\n+\t\tpkt_len = rte_pktmbuf_pkt_len(pkt);\n+\n+\t\tif (pkt->nb_segs > nb_avail) /* no desc to use */\n+\t\t\tgoto end_of_xmit;\n+\n+\t\tm = pkt;\n+\n+\t\tdo {\n+\t\t\tqword1 = 0;\n+\t\t\td = &ring_dma[head];\n+\t\t\tdata_len = rte_pktmbuf_data_len(m);\n+\t\t\tdesc_addr = (void *)(uintptr_t)rte_iavf_emu_get_dma_vaddr(\n+\t\t\t\tadapter->mem_table,\n+\t\t\t\trte_le_to_cpu_64(d->read.pkt_addr),\n+\t\t\t\t&len);\n+\n+\t\t\trte_memcpy(desc_addr, rte_pktmbuf_mtod(m, void *),\n+\t\t\t\t data_len);\n+\n+\t\t\t/* If pkt carries vlan info, post it to descriptor */\n+\t\t\tif (m->ol_flags & (PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN)) {\n+\t\t\t\tqword1 |= 1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT;\n+\t\t\t\td->wb.qword0.lo_dword.l2tag1 =\n+\t\t\t\t\trte_cpu_to_le_16(pkt->vlan_tci);\n+\t\t\t}\n+\t\t\tm = m->next;\n+\t\t\t/* Mark the last desc with EOP flag */\n+\t\t\tif (!m)\n+\t\t\t\tqword1 |=\n+\t\t\t\t\t((1 << IAVF_RX_DESC_STATUS_EOF_SHIFT)\n+\t\t\t\t\t << IAVF_RXD_QW1_STATUS_SHIFT);\n+\n+\t\t\tqword1 = qword1 |\n+\t\t\t\t((1 << IAVF_RX_DESC_STATUS_DD_SHIFT)\n+\t\t\t\t<< IAVF_RXD_QW1_STATUS_SHIFT) |\n+\t\t\t\t((data_len << IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)\n+\t\t\t\t& IAVF_RXD_QW1_LENGTH_PBUF_MASK);\n+\n+\t\t\trte_wmb();\n+\n+\t\t\td->wb.qword1.status_error_len = rte_cpu_to_le_64(qword1);\n+\n+\t\t\tIAVF_BE_DUMP_RX_DESC(txq, d, head);\n+\n+\t\t\thead++;\n+\t\t\tif (head >= txq->nb_tx_desc)\n+\t\t\t\thead = 0;\n+\n+\t\t\t/* Prefetch next 4 RX descriptors */\n+\t\t\tif ((head & 0x3) == 0)\n+\t\t\t\trte_prefetch0(d);\n+\t\t} while (m);\n+\n+\t\tnb_avail -= pkt->nb_segs;\n+\n+\t\tnb_tx++;\n+\n+\t\t/* update stats */\n+\t\tea = rte_pktmbuf_mtod(pkt, struct rte_ether_addr *);\n+\t\tif (rte_is_multicast_ether_addr(ea)) {\n+\t\t\tif (rte_is_broadcast_ether_addr(ea))\n+\t\t\t\ttxq->stats.sent_broad_num++;\n+\t\t\telse\n+\t\t\t\ttxq->stats.sent_multi_num++;\n+\t\t}\n+\t\ttxq->stats.sent_pkt_num++;\n+\t\ttxq->stats.sent_bytes += pkt_len;\n+\t\t/* Free entire packet */\n+\t\trte_pktmbuf_free(pkt);\n+\t}\n+\n+end_of_xmit:\n+\ttxq->rx_head = head;\n+\ttxq->stats.sent_miss_num += nb_pkts - nb_tx;\n+\treturn nb_tx;\n+}\n+\n+/* TX prep functions */\n+uint16_t\n+iavfbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct iavfbe_tx_queue *txq = (struct iavfbe_tx_queue *)tx_queue;\n+\tstruct rte_mbuf *m;\n+\tuint16_t data_len;\n+\tuint32_t pkt_len;\n+\tint i;\n+\n+\tfor (i = 0; i < nb_pkts; i++) {\n+\t\tm = tx_pkts[i];\n+\t\tpkt_len = rte_pktmbuf_pkt_len(m);\n+\n+\t\t/* Check buffer len and packet len */\n+\t\tif (pkt_len > txq->max_pkt_size) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn i;\n+\t\t}\n+\t\t/* Cannot support a pkt using more than 5 descriptors */\n+\t\tif (m->nb_segs > AVF_RX_MAX_SEG) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn i;\n+\t\t}\n+\t\tdo {\n+\t\t\tdata_len = rte_pktmbuf_data_len(m);\n+\t\t\tif (data_len > txq->buffer_size) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn i;\n+\t\t\t}\n+\t\t\tm = m->next;\n+\t\t} while (m);\n+\t}\n+\n+\treturn i;\n+}\ndiff --git a/drivers/net/iavf_be/iavf_be_rxtx.h b/drivers/net/iavf_be/iavf_be_rxtx.h\nindex e8be3f532d..65fe7ed409 100644\n--- a/drivers/net/iavf_be/iavf_be_rxtx.h\n+++ b/drivers/net/iavf_be/iavf_be_rxtx.h\n@@ -99,5 +99,65 @@ void iavfbe_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \t\t\t struct rte_eth_rxq_info *qinfo);\n void iavfbe_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \t\t\t struct rte_eth_txq_info *qinfo);\n+uint16_t iavfbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+uint16_t iavfbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+uint16_t iavfbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+\n+static inline\n+void iavfbe_dump_rx_descriptor(struct iavfbe_tx_queue *txq,\n+\t\t\t const void *desc,\n+\t\t\t uint16_t rx_id)\n+{\n+\tconst union iavf_32byte_rx_desc *rx_desc = desc;\n+\n+\tprintf(\"Queue %d Rx_desc %d: QW0: 0x%016\"PRIx64\" QW1: 0x%016\"PRIx64\n+\t \" QW2: 0x%016\"PRIx64\" QW3: 0x%016\"PRIx64\"\\n\", txq->queue_id,\n+\t rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,\n+\t rx_desc->read.rsvd1, rx_desc->read.rsvd2);\n+}\n+\n+/* All the descriptors are 16 bytes, so just use one of them\n+ * to print the qwords\n+ */\n+static inline\n+void iavfbe_dump_tx_descriptor(const struct iavfbe_rx_queue *rxq,\n+\t\t\t const void *desc, uint16_t tx_id)\n+{\n+\tconst char *name;\n+\tconst struct iavf_tx_desc *tx_desc = desc;\n+\tenum iavf_tx_desc_dtype_value type;\n+\n+\ttype = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(\n+\t\ttx_desc->cmd_type_offset_bsz &\n+\t\trte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));\n+\tswitch (type) {\n+\tcase IAVF_TX_DESC_DTYPE_DATA:\n+\t\tname = \"Tx_data_desc\";\n+\t\tbreak;\n+\tcase IAVF_TX_DESC_DTYPE_CONTEXT:\n+\t\tname = \"Tx_context_desc\";\n+\t\tbreak;\n+\tdefault:\n+\t\tname = \"unknown_desc\";\n+\t\tbreak;\n+\t}\n+\n+\tprintf(\"Queue %d %s %d: QW0: 0x%016\"PRIx64\" QW1: 0x%016\"PRIx64\"\\n\",\n+\t rxq->queue_id, name, tx_id, tx_desc->buffer_addr,\n+\t tx_desc->cmd_type_offset_bsz);\n+}\n+\n+#ifdef DEBUG_DUMP_DESC\n+#define IAVF_BE_DUMP_RX_DESC(rxq, desc, rx_id) \\\n+\tiavfbe_dump_rx_descriptor(rxq, desc, rx_id)\n+#define IAVF_BE_DUMP_TX_DESC(txq, desc, tx_id) \\\n+\tiavfbe_dump_tx_descriptor(txq, desc, tx_id)\n+#else\n+#define IAVF_BE_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)\n+#define IAVF_BE_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)\n+#endif\n \n #endif /* _AVF_BE_RXTX_H_ */\n", "prefixes": [ "v1", "4/5" ] }