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GET /api/patches/85323/?format=api
{ "id": 85323, "url": "http://patches.dpdk.org/api/patches/85323/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-14-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1608205475-20067-14-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-14-git-send-email-michaelba@nvidia.com", "date": "2020-12-17T11:44:31", "name": "[13/17] net/mlx5: move Tx SQ creation to common", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b38328780254590eec64d4795651f6de931039c6", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-14-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14348, "url": "http://patches.dpdk.org/api/series/14348/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14348", "date": "2020-12-17T11:44:23", "name": "common/mlx5: share DevX resources creations", "version": 1, "mbox": "http://patches.dpdk.org/series/14348/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85323/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/85323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 725EDA09F6;\n\tThu, 17 Dec 2020 12:49:58 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8C305CACE;\n\tThu, 17 Dec 2020 12:45:20 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id E584DCA2E\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:51 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2c004524;\n Thu, 17 Dec 2020 13:44:51 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 17 Dec 2020 11:44:31 +0000", "Message-Id": "<1608205475-20067-14-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 13/17] net/mlx5: move Tx SQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for Tx SQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 8 +--\n drivers/net/mlx5/mlx5_devx.c | 160 ++++++++++---------------------------------\n 2 files changed, 40 insertions(+), 128 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 192a5a7..6977eac 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -837,11 +837,9 @@ struct mlx5_txq_obj {\n \t\tstruct {\n \t\t\tstruct rte_eth_dev *dev;\n \t\t\tstruct mlx5_devx_cq cq_obj;\n-\t\t\tstruct mlx5_devx_obj *sq_devx;\n-\t\t\tvoid *sq_umem;\n-\t\t\tvoid *sq_buf;\n-\t\t\tint64_t sq_dbrec_offset;\n-\t\t\tstruct mlx5_devx_dbr_page *sq_dbrec_page;\n+\t\t\t/* DevX CQ object and its resources. */\n+\t\t\tstruct mlx5_devx_sq sq_obj;\n+\t\t\t/* DevX SQ object and its resources. */\n \t\t};\n \t};\n };\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex fe103a7..4154c52 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -115,7 +115,7 @@\n \t\telse\n \t\t\tmsq_attr.sq_state = MLX5_SQC_STATE_RDY;\n \t\tmsq_attr.state = MLX5_SQC_STATE_RST;\n-\t\tret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);\n+\t\tret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Cannot change the Tx SQ state to RESET\"\n \t\t\t\t\" %s\", strerror(errno));\n@@ -127,7 +127,7 @@\n \t\t/* Change queue state to ready. */\n \t\tmsq_attr.sq_state = MLX5_SQC_STATE_RST;\n \t\tmsq_attr.state = MLX5_SQC_STATE_RDY;\n-\t\tret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);\n+\t\tret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Cannot change the Tx SQ state to READY\"\n \t\t\t\t\" %s\", strerror(errno));\n@@ -1056,36 +1056,6 @@\n \n #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n /**\n- * Release DevX SQ resources.\n- *\n- * @param txq_obj\n- * DevX Tx queue object.\n- */\n-static void\n-mlx5_txq_release_devx_sq_resources(struct mlx5_txq_obj *txq_obj)\n-{\n-\tif (txq_obj->sq_devx) {\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx));\n-\t\ttxq_obj->sq_devx = NULL;\n-\t}\n-\tif (txq_obj->sq_umem) {\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(txq_obj->sq_umem));\n-\t\ttxq_obj->sq_umem = NULL;\n-\t}\n-\tif (txq_obj->sq_buf) {\n-\t\tmlx5_free(txq_obj->sq_buf);\n-\t\ttxq_obj->sq_buf = NULL;\n-\t}\n-\tif (txq_obj->sq_dbrec_page) {\n-\t\tclaim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,\n-\t\t\t\t\t mlx5_os_get_umem_id\n-\t\t\t\t\t\t (txq_obj->sq_dbrec_page->umem),\n-\t\t\t\t\t txq_obj->sq_dbrec_offset));\n-\t\ttxq_obj->sq_dbrec_page = NULL;\n-\t}\n-}\n-\n-/**\n * Destroy the Tx queue DevX object.\n *\n * @param txq_obj\n@@ -1094,7 +1064,8 @@\n static void\n mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)\n {\n-\tmlx5_txq_release_devx_sq_resources(txq_obj);\n+\tmlx5_devx_sq_destroy(&txq_obj->sq_obj);\n+\tmemset(&txq_obj->sq_obj, 0, sizeof(txq_obj->sq_obj));\n \tmlx5_devx_cq_destroy(&txq_obj->cq_obj);\n \tmemset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));\n }\n@@ -1106,100 +1077,41 @@\n * Pointer to Ethernet device.\n * @param idx\n * Queue index in DPDK Tx queue array.\n+ * @param[in] log_desc_n\n+ * Log of number of descriptors in queue.\n *\n * @return\n- * Number of WQEs in SQ, 0 otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static uint32_t\n-mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx)\n+static int\n+mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n+\t\t\t\t uint16_t log_desc_n)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n \tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n-\tstruct mlx5_devx_create_sq_attr sq_attr = { 0 };\n-\tsize_t page_size;\n-\tuint32_t wqe_n;\n-\tint ret;\n+\tstruct mlx5_devx_create_sq_attr sq_attr = {\n+\t\t.flush_in_error_en = 1,\n+\t\t.allow_multi_pkt_send_wqe = !!priv->config.mps,\n+\t\t.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode,\n+\t\t.allow_swp = !!priv->config.swp,\n+\t\t.cqn = txq_obj->cq_obj.cq->id,\n+\t\t.tis_lst_sz = 1,\n+\t\t.tis_num = priv->sh->tis->id,\n+\t\t.wq_attr = (struct mlx5_devx_wq_attr){\n+\t\t\t.pd = priv->sh->pdn,\n+\t\t\t.uar_page =\n+\t\t\t\t mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),\n+\t\t},\n+\t};\n \n \tMLX5_ASSERT(txq_data);\n \tMLX5_ASSERT(txq_obj);\n-\tpage_size = rte_mem_page_size();\n-\tif (page_size == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get mem page size.\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n-\twqe_n = RTE_MIN(1UL << txq_data->elts_n,\n-\t\t\t(uint32_t)priv->sh->device_attr.max_qp_wr);\n-\ttxq_obj->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t\t wqe_n * sizeof(struct mlx5_wqe),\n-\t\t\t\t page_size, priv->sh->numa_node);\n-\tif (!txq_obj->sq_buf) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot allocate memory (SQ).\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\t/* Register allocated buffer in user space with DevX. */\n-\ttxq_obj->sq_umem = mlx5_glue->devx_umem_reg\n-\t\t\t\t\t(priv->sh->ctx,\n-\t\t\t\t\t (void *)txq_obj->sq_buf,\n-\t\t\t\t\t wqe_n * sizeof(struct mlx5_wqe),\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (!txq_obj->sq_umem) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot register memory (SQ).\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\tgoto error;\n-\t}\n-\t/* Allocate doorbell record for send queue. */\n-\ttxq_obj->sq_dbrec_offset = mlx5_get_dbr(priv->sh->ctx,\n-\t\t\t\t\t\t&priv->dbrpgs,\n-\t\t\t\t\t\t&txq_obj->sq_dbrec_page);\n-\tif (txq_obj->sq_dbrec_offset < 0) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Failed to allocate SQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\tsq_attr.tis_lst_sz = 1;\n-\tsq_attr.tis_num = priv->sh->tis->id;\n-\tsq_attr.state = MLX5_SQC_STATE_RST;\n-\tsq_attr.cqn = txq_obj->cq_obj.cq->id;\n-\tsq_attr.flush_in_error_en = 1;\n-\tsq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;\n-\tsq_attr.allow_swp = !!priv->config.swp;\n-\tsq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;\n-\tsq_attr.wq_attr.uar_page =\n-\t\t\t\tmlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);\n-\tsq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n-\tsq_attr.wq_attr.pd = priv->sh->pdn;\n-\tsq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n-\tsq_attr.wq_attr.log_wq_sz = log2above(wqe_n);\n-\tsq_attr.wq_attr.dbr_umem_valid = 1;\n-\tsq_attr.wq_attr.dbr_addr = txq_obj->sq_dbrec_offset;\n-\tsq_attr.wq_attr.dbr_umem_id =\n-\t\t\tmlx5_os_get_umem_id(txq_obj->sq_dbrec_page->umem);\n-\tsq_attr.wq_attr.wq_umem_valid = 1;\n-\tsq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(txq_obj->sq_umem);\n-\tsq_attr.wq_attr.wq_umem_offset = (uintptr_t)txq_obj->sq_buf % page_size;\n \t/* Create Send Queue object with DevX. */\n-\ttxq_obj->sq_devx = mlx5_devx_cmd_create_sq(priv->sh->ctx, &sq_attr);\n-\tif (!txq_obj->sq_devx) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Port %u Tx queue %u SQ creation failure.\",\n-\t\t\tdev->data->port_id, idx);\n-\t\tgoto error;\n-\t}\n-\treturn wqe_n;\n-error:\n-\tret = rte_errno;\n-\tmlx5_txq_release_devx_sq_resources(txq_obj);\n-\trte_errno = ret;\n-\treturn 0;\n+\treturn mlx5_devx_sq_create(priv->sh->ctx, &txq_obj->sq_obj, log_desc_n,\n+\t\t\t\t &sq_attr, priv->sh->numa_node);\n }\n #endif\n \n@@ -1273,27 +1185,29 @@\n \ttxq_data->cq_db = txq_obj->cq_obj.db_rec;\n \t*txq_data->cq_db = 0;\n \t/* Create Send Queue object with DevX. */\n-\twqe_n = mlx5_txq_create_devx_sq_resources(dev, idx);\n-\tif (!wqe_n) {\n+\twqe_n = RTE_MIN(1UL << txq_data->elts_n,\n+\t\t\t(uint32_t)priv->sh->device_attr.max_qp_wr);\n+\tlog_desc_n = log2above(wqe_n);\n+\tret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u SQ creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n \t/* Create the Work Queue. */\n-\ttxq_data->wqe_n = log2above(wqe_n);\n+\ttxq_data->wqe_n = log_desc_n;\n \ttxq_data->wqe_s = 1 << txq_data->wqe_n;\n \ttxq_data->wqe_m = txq_data->wqe_s - 1;\n-\ttxq_data->wqes = (struct mlx5_wqe *)txq_obj->sq_buf;\n+\ttxq_data->wqes = (struct mlx5_wqe *)(uintptr_t)txq_obj->sq_obj.wqes;\n \ttxq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;\n \ttxq_data->wqe_ci = 0;\n \ttxq_data->wqe_pi = 0;\n \ttxq_data->wqe_comp = 0;\n \ttxq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;\n-\ttxq_data->qp_db = (volatile uint32_t *)\n-\t\t\t\t\t(txq_obj->sq_dbrec_page->dbrs +\n-\t\t\t\t\t txq_obj->sq_dbrec_offset +\n-\t\t\t\t\t MLX5_SND_DBR * sizeof(uint32_t));\n+\ttxq_data->qp_db = txq_obj->sq_obj.db_rec;\n \t*txq_data->qp_db = 0;\n-\ttxq_data->qp_num_8s = txq_obj->sq_devx->id << 8;\n+\ttxq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8;\n \t/* Change Send Queue state to Ready-to-Send. */\n \tret = mlx5_devx_modify_sq(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);\n \tif (ret) {\n", "prefixes": [ "13/17" ] }