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GET /api/patches/85308/?format=api
{ "id": 85308, "url": "http://patches.dpdk.org/api/patches/85308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-4-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1608205475-20067-4-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-4-git-send-email-michaelba@nvidia.com", "date": "2020-12-17T11:44:21", "name": "[03/17] regex/mlx5: move DevX CQ creation to common", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ce238a47838f5f665ab7ae9b49e0f053e9c5c9ff", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-4-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14348, "url": "http://patches.dpdk.org/api/series/14348/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14348", "date": "2020-12-17T11:44:23", "name": "common/mlx5: share DevX resources creations", "version": 1, "mbox": "http://patches.dpdk.org/series/14348/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85308/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/85308/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CF5F4A09F6;\n\tThu, 17 Dec 2020 12:45:13 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0E620CA24;\n\tThu, 17 Dec 2020 12:45:00 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 4FC50CA16\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:50 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2S004524;\n Thu, 17 Dec 2020 13:44:50 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 17 Dec 2020 11:44:21 +0000", "Message-Id": "<1608205475-20067-4-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 03/17] regex/mlx5: move DevX CQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for DevX CQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/regex/mlx5/mlx5_regex.c | 6 ---\n drivers/regex/mlx5/mlx5_regex.h | 9 +---\n drivers/regex/mlx5/mlx5_regex_control.c | 91 ++++++--------------------------\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 4 +-\n 4 files changed, 20 insertions(+), 90 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex c91c444..c0d6331 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -170,12 +170,6 @@\n \t\trte_errno = rte_errno ? rte_errno : EINVAL;\n \t\tgoto error;\n \t}\n-\tret = mlx5_glue->devx_query_eqn(ctx, 0, &priv->eqn);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"can't query event queue number.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n \t/*\n \t * This PMD always claims the write memory barrier on UAR\n \t * registers writings, it is safe to allocate UAR with any\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 2c4877c..9f7a388 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -12,6 +12,7 @@\n \n #include <mlx5_common.h>\n #include <mlx5_common_mr.h>\n+#include <mlx5_common_devx.h>\n \n #include \"mlx5_rxp.h\"\n \n@@ -30,13 +31,8 @@ struct mlx5_regex_sq {\n \n struct mlx5_regex_cq {\n \tuint32_t log_nb_desc; /* Log 2 number of desc for this object. */\n-\tstruct mlx5_devx_obj *obj; /* The CQ DevX object. */\n-\tint64_t dbr_offset; /* Door bell record offset. */\n-\tuint32_t dbr_umem; /* Door bell record umem id. */\n-\tvolatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */\n-\tstruct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */\n+\tstruct mlx5_devx_cq cq_obj; /* The CQ DevX object. */\n \tsize_t ci;\n-\tuint32_t *dbr;\n };\n \n struct mlx5_regex_qp {\n@@ -75,7 +71,6 @@ struct mlx5_regex_priv {\n \tstruct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +\n \t\t\t\tMLX5_RXP_EM_COUNT];\n \tuint32_t nb_engines; /* Number of RegEx engines. */\n-\tuint32_t eqn; /* EQ number. */\n \tstruct mlx5dv_devx_uar *uar; /* UAR object. */\n \tstruct ibv_pd *pd;\n \tstruct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex d6f452b..ca6c0f5 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -6,6 +6,7 @@\n \n #include <rte_log.h>\n #include <rte_errno.h>\n+#include <rte_memory.h>\n #include <rte_malloc.h>\n #include <rte_regexdev.h>\n #include <rte_regexdev_core.h>\n@@ -17,6 +18,7 @@\n #include <mlx5_devx_cmds.h>\n #include <mlx5_prm.h>\n #include <mlx5_common_os.h>\n+#include <mlx5_common_devx.h>\n \n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n@@ -44,8 +46,6 @@\n /**\n * destroy CQ.\n *\n- * @param priv\n- * Pointer to the priv object.\n * @param cp\n * Pointer to the CQ to be destroyed.\n *\n@@ -53,24 +53,10 @@\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-regex_ctrl_destroy_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)\n+regex_ctrl_destroy_cq(struct mlx5_regex_cq *cq)\n {\n-\tif (cq->cqe_umem) {\n-\t\tmlx5_glue->devx_umem_dereg(cq->cqe_umem);\n-\t\tcq->cqe_umem = NULL;\n-\t}\n-\tif (cq->cqe) {\n-\t\trte_free((void *)(uintptr_t)cq->cqe);\n-\t\tcq->cqe = NULL;\n-\t}\n-\tif (cq->dbr_offset) {\n-\t\tmlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);\n-\t\tcq->dbr_offset = -1;\n-\t}\n-\tif (cq->obj) {\n-\t\tmlx5_devx_cmd_destroy(cq->obj);\n-\t\tcq->obj = NULL;\n-\t}\n+\tmlx5_devx_cq_destroy(&cq->cq_obj);\n+\tmemset(cq, 0, sizeof(*cq));\n \treturn 0;\n }\n \n@@ -89,65 +75,20 @@\n regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)\n {\n \tstruct mlx5_devx_cq_attr attr = {\n-\t\t.q_umem_valid = 1,\n-\t\t.db_umem_valid = 1,\n-\t\t.eqn = priv->eqn,\n+\t\t.uar_page_id = priv->uar->page_id,\n \t};\n-\tstruct mlx5_devx_dbr_page *dbr_page = NULL;\n-\tvoid *buf = NULL;\n-\tsize_t pgsize = sysconf(_SC_PAGESIZE);\n-\tuint32_t cq_size = 1 << cq->log_nb_desc;\n-\tuint32_t i;\n-\n-\tcq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page);\n-\tif (cq->dbr_offset < 0) {\n-\t\tDRV_LOG(ERR, \"Can't allocate cq door bell record.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tcq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);\n-\tcq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n-\t\t\t (uintptr_t)cq->dbr_offset);\n+\tint ret;\n \n-\tbuf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096);\n-\tif (!buf) {\n-\t\tDRV_LOG(ERR, \"Can't allocate cqe buffer.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tcq->cqe = buf;\n-\tfor (i = 0; i < cq_size; i++)\n-\t\tcq->cqe[i].op_own = 0xff;\n-\tcq->cqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf,\n-\t\t\t\t\t\tsizeof(struct mlx5_cqe) *\n-\t\t\t\t\t\tcq_size, 7);\n \tcq->ci = 0;\n-\tif (!cq->cqe_umem) {\n-\t\tDRV_LOG(ERR, \"Can't register cqe mem.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tattr.db_umem_offset = cq->dbr_offset;\n-\tattr.db_umem_id = cq->dbr_umem;\n-\tattr.q_umem_id = mlx5_os_get_umem_id(cq->cqe_umem);\n-\tattr.log_cq_size = cq->log_nb_desc;\n-\tattr.uar_page_id = priv->uar->page_id;\n-\tattr.log_page_size = rte_log2_u32(pgsize);\n-\tcq->obj = mlx5_devx_cmd_create_cq(priv->ctx, &attr);\n-\tif (!cq->obj) {\n-\t\tDRV_LOG(ERR, \"Can't create cq object.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n+\tret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, cq->log_nb_desc,\n+\t\t\t\t &attr, SOCKET_ID_ANY);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Can't create CQ object.\");\n+\t\tmemset(cq, 0, sizeof(*cq));\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n \t}\n \treturn 0;\n-error:\n-\tif (cq->cqe_umem)\n-\t\tmlx5_glue->devx_umem_dereg(cq->cqe_umem);\n-\tif (buf)\n-\t\trte_free(buf);\n-\tif (cq->dbr_offset)\n-\t\tmlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);\n-\treturn -rte_errno;\n }\n \n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n@@ -232,7 +173,7 @@\n \tattr.tis_lst_sz = 0;\n \tattr.tis_num = 0;\n \tattr.user_index = q_ind;\n-\tattr.cqn = qp->cq.obj->id;\n+\tattr.cqn = qp->cq.cq_obj.cq->id;\n \twq_attr->uar_page = priv->uar->page_id;\n \tregex_get_pdn(priv->pd, &pd_num);\n \twq_attr->pd = pd_num;\n@@ -389,7 +330,7 @@\n err_btree:\n \tfor (i = 0; i < nb_sq_config; i++)\n \t\tregex_ctrl_destroy_sq(priv, qp, i);\n-\tregex_ctrl_destroy_cq(priv, &qp->cq);\n+\tregex_ctrl_destroy_cq(&qp->cq);\n err_cq:\n \trte_free(qp->sqs);\n \treturn ret;\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex 5857617..255fd40 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -224,7 +224,7 @@ struct mlx5_regex_job {\n \tsize_t next_cqe_offset;\n \n \tnext_cqe_offset = (cq->ci & (cq_size_get(cq) - 1));\n-\tcqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset);\n+\tcqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset);\n \trte_io_wmb();\n \n \tint ret = check_cqe(cqe, cq_size_get(cq), cq->ci);\n@@ -285,7 +285,7 @@ struct mlx5_regex_job {\n \t\t}\n \t\tcq->ci = (cq->ci + 1) & 0xffffff;\n \t\trte_wmb();\n-\t\tcq->dbr[0] = rte_cpu_to_be_32(cq->ci);\n+\t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci);\n \t\tqueue->free_sqs |= (1 << sqid);\n \t}\n \n", "prefixes": [ "03/17" ] }