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GET /api/patches/85241/?format=api
{ "id": 85241, "url": "http://patches.dpdk.org/api/patches/85241/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1608123735-3662-7-git-send-email-shirik@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1608123735-3662-7-git-send-email-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1608123735-3662-7-git-send-email-shirik@nvidia.com", "date": "2020-12-16T13:02:13", "name": "[RFC,v3,6/8] net/mlx5: add GENEVE TLV option flow validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6edcfdc98c3b63af71922849612ac88a1b3933e2", "submitter": { "id": 1894, "url": "http://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1608123735-3662-7-git-send-email-shirik@nvidia.com/mbox/", "series": [ { "id": 14330, "url": "http://patches.dpdk.org/api/series/14330/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14330", "date": "2020-12-16T13:02:07", "name": "ethdev: introduce GENEVE header TLV option item", "version": 3, "mbox": "http://patches.dpdk.org/series/14330/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85241/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/85241/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A0E2A09EF;\n\tWed, 16 Dec 2020 14:04:50 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1F3C5CA10;\n\tWed, 16 Dec 2020 14:02:59 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id E9834C9E7\n for <dev@dpdk.org>; Wed, 16 Dec 2020 14:02:54 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 16 Dec 2020 15:02:49 +0200", "from nvidia.com (nps-server-11.mtl.labs.mlnx [10.7.12.71])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BGD2M1F011463;\n Wed, 16 Dec 2020 15:02:48 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, rasland@nvidia.com", "Date": "Wed, 16 Dec 2020 15:02:13 +0200", "Message-Id": "<1608123735-3662-7-git-send-email-shirik@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1608123735-3662-1-git-send-email-shirik@nvidia.com>", "References": "<1599118768-13265-1-git-send-email-shirik@nvidia.com>\n <1608123735-3662-1-git-send-email-shirik@nvidia.com>", "Subject": "[dpdk-dev] [RFC v3 6/8] net/mlx5: add GENEVE TLV option flow\n\tvalidation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds validation routine for the GENEVE\nheader TLV option.\n\nThe GENEVE TLV option match must include all fields\nwith full masks due to NIC does not support masking\non option class, type and length.\n\nThe option data length must be non zero and provided\ndata pattern should be zero neither due to hardware\nlimitations.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 120 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 7 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 10 +++-\n 3 files changed, 136 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 82e24d7..eaf777b 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -2603,6 +2603,126 @@ struct mlx5_flow_tunnel_info {\n }\n \n /**\n+ * Validate Geneve TLV option item.\n+ *\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] last_item\n+ * Previous validated item in the pattern items.\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,\n+\t\t\t\t uint64_t last_item,\n+\t\t\t\t struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_geneve_tlv_option_resource *geneve_opt_resource;\n+\tstruct mlx5_hca_attr *hca_attr = &priv->config.hca_attr;\n+\tuint8_t data_max_supported =\n+\t\t\thca_attr->max_geneve_tlv_option_data_len * 4;\n+\tstruct mlx5_dev_config *config = &priv->config;\n+\tconst struct rte_flow_item_geneve_opt *spec = item->spec;\n+\tconst struct rte_flow_item_geneve_opt *mask = item->mask;\n+\tunsigned int i;\n+\tunsigned int data_len;\n+\tconst struct rte_flow_item_geneve_opt full_mask = {\n+\t\t.option_class = RTE_BE16(0xffff),\n+\t\t.option_type = 0xff,\n+\t\t.option_len = 0x1f,\n+\t};\n+\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_geneve_opt_mask;\n+\tif (!spec)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt class/type/length must be specified\");\n+\tif ((uint32_t)(spec->option_len) > MLX5_GENEVE_OPTLEN_MASK)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt length exceeeds the limit (31)\");\n+\t/* Check if class type and length masks are full. */\n+\tif (full_mask.option_class != mask->option_class ||\n+\t full_mask.option_type != mask->option_type ||\n+\t full_mask.option_len != (mask->option_len & full_mask.option_len))\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt class/type/length masks must be full\");\n+\t/* Check if length is supported */\n+\tif ((uint32_t)(spec->option_len) >\n+\t\t\tconfig->hca_attr.max_geneve_tlv_option_data_len)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt length not supported\");\n+\tif (config->hca_attr.max_geneve_tlv_options > 1)\n+\t\tDRV_LOG(DEBUG,\n+\t\t\t\"max_geneve_tlv_options supports more than 1 option\");\n+\t/* Check GENEVE item preceding. */\n+\tif (!(last_item & MLX5_FLOW_LAYER_GENEVE))\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve opt item must be preceded with Geneve item\");\n+\t/* Check if length is 0 or data is 0. */\n+\tif (spec->data == NULL || spec->option_len == 0)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt with zero data/length not supported\");\n+\t/* Check not all data & mask are 0. */\n+\tdata_len = spec->option_len * 4;\n+\tif (mask->data == NULL) {\n+\t\tfor (i = 0; i < data_len; i++)\n+\t\t\tif (spec->data[i])\n+\t\t\t\tbreak;\n+\t\tif (i == data_len)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\"Can't match on Geneve option data 0\");\n+\t} else {\n+\t\tfor (i = 0; i < data_len; i++)\n+\t\t\tif (spec->data[i] & mask->data[i])\n+\t\t\t\tbreak;\n+\t\tif (i == data_len)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\"Can't match on Geneve option data and mask 0\");\n+\t\t/* Check data mask supported. */\n+\t\tfor (i = data_max_supported; i < data_len ; i++)\n+\t\t\tif (mask->data[i])\n+\t\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t\"Data mask is of unsupported size\");\n+\t}\n+\t/* Check GENEVE option is supported in NIC. */\n+\tif (!config->hca_attr.geneve_tlv_opt)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\"Geneve TLV opt not supported\");\n+\t/* Check if we already have geneve option with different type/class. */\n+\trte_spinlock_lock(&sh->geneve_tlv_opt_sl);\n+\tgeneve_opt_resource = sh->geneve_tlv_option_resource;\n+\tif (geneve_opt_resource != NULL)\n+\t\tif (geneve_opt_resource->option_class != spec->option_class ||\n+\t\t geneve_opt_resource->option_type != spec->option_type ||\n+\t\t geneve_opt_resource->length != spec->option_len) {\n+\t\t\trte_spinlock_unlock(&sh->geneve_tlv_opt_sl);\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\"Only one Geneve TLV option supported\");\n+\t\t}\n+\trte_spinlock_unlock(&sh->geneve_tlv_opt_sl);\n+\treturn 0;\n+}\n+\n+/**\n * Validate MPLS item.\n *\n * @param[in] dev\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex d8a6688..f9b81f5 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -138,6 +138,9 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)\n #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)\n \n+/* Pattern tunnel Layer bits (continued). */\n+#define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -1398,6 +1401,10 @@ int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error);\n+int mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item,\n+\t\t\t\t uint64_t last_item,\n+\t\t\t\t struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_flow_error *error);\n int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t uint64_t last_item,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex ab39f23..49f900b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5496,6 +5496,15 @@ struct mlx5_hlist_entry *\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_LAYER_GENEVE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GENEVE_OPT:\n+\t\t\tret = mlx5_flow_validate_item_geneve_opt(items,\n+\t\t\t\t\t\t\t\t last_item,\n+\t\t\t\t\t\t\t\t dev,\n+\t\t\t\t\t\t\t\t error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GENEVE_OPT;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_MPLS:\n \t\t\tret = mlx5_flow_validate_item_mpls(dev, items,\n \t\t\t\t\t\t\t item_flags,\n@@ -5504,7 +5513,6 @@ struct mlx5_hlist_entry *\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_LAYER_MPLS;\n \t\t\tbreak;\n-\n \t\tcase RTE_FLOW_ITEM_TYPE_MARK:\n \t\t\tret = flow_dv_validate_item_mark(dev, items, attr,\n \t\t\t\t\t\t\t error);\n", "prefixes": [ "RFC", "v3", "6/8" ] }