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GET /api/patches/85172/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 85172,
    "url": "http://patches.dpdk.org/api/patches/85172/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201215060519.302145-16-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201215060519.302145-16-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201215060519.302145-16-qi.z.zhang@intel.com",
    "date": "2020-12-15T06:05:07",
    "name": "[15/27] net/ice/base: support VXLAN VNI field in FDIR",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "ba7015faa272b7a92951f891ead136d57d204515",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201215060519.302145-16-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 14300,
            "url": "http://patches.dpdk.org/api/series/14300/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14300",
            "date": "2020-12-15T06:04:52",
            "name": "ice base code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/14300/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/85172/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/85172/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 333EAA09E9;\n\tTue, 15 Dec 2020 07:06:55 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7BB46CA41;\n\tTue, 15 Dec 2020 07:01:54 +0100 (CET)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 09192C9D2\n for <dev@dpdk.org>; Tue, 15 Dec 2020 07:01:50 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Dec 2020 22:01:50 -0800",
            "from dpdk51.sh.intel.com ([10.67.111.142])\n by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:48 -0800"
        ],
        "IronPort-SDR": [
            "\n x15Z/Rd5K9f66PF+hKwWnA860c+XcgFFbNUgvvM01qi/C7M3TIWaabAqkjjuS6N1b8oAnG5qrn\n BKQErpmvxsJQ==",
            "\n gPh08kjxGbUc0YGd1PbhkizZDuf/FLhuMvskGvpYOBf1/jQRGvb3ExqwxyLUL6vTHUbRpK2CnJ\n mVZKhBxYcx2Q=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9835\"; a=\"193200278\"",
            "E=Sophos;i=\"5.78,420,1599548400\"; d=\"scan'208\";a=\"193200278\"",
            "E=Sophos;i=\"5.78,420,1599548400\"; d=\"scan'208\";a=\"351723573\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Zhirun Yan <zhirun.yan@intel.com>",
        "Date": "Tue, 15 Dec 2020 14:05:07 +0800",
        "Message-Id": "<20201215060519.302145-16-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.26.2",
        "In-Reply-To": "<20201215060519.302145-1-qi.z.zhang@intel.com>",
        "References": "<20201215060519.302145-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 15/27] net/ice/base: support VXLAN VNI field in\n\tFDIR",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Enable VXLAN VNI field in FDIR.\n\nSigned-off-by: Zhirun Yan <zhirun.yan@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_fdir.c | 43 +++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_fdir.h |  8 ++++++\n drivers/net/ice/base/ice_flow.c | 21 ++++++++++++++++\n drivers/net/ice/base/ice_flow.h |  6 +++++\n drivers/net/ice/base/ice_type.h |  1 +\n 5 files changed, 79 insertions(+)",
    "diff": "diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c\nindex aeff7af55d..cccbcf5e7f 100644\n--- a/drivers/net/ice/base/ice_fdir.c\n+++ b/drivers/net/ice/base/ice_fdir.c\n@@ -42,6 +42,21 @@ static const u8 ice_fdir_ipv4_pkt[] = {\n \t0x00, 0x00\n };\n \n+static const u8 ice_fdir_udp4_vxlan_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,\n+\t0x00, 0x4e, 0x00, 0x00, 0x40, 0x00, 0x40, 0x11,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,\n+\t0x45, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x40, 0x00,\n+\t0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+};\n+\n static const u8 ice_fdir_udp4_gtpu4_pkt[] = {\n \t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,\n@@ -614,6 +629,11 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {\n \t\tsizeof(ice_fdir_non_ip_l2_pkt), ice_fdir_non_ip_l2_pkt,\n \t\tsizeof(ice_fdir_non_ip_l2_pkt), ice_fdir_non_ip_l2_pkt,\n \t},\n+\t{\n+\t\tICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,\n+\t\tsizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt,\n+\t\tsizeof(ice_fdir_udp4_vxlan_pkt), ice_fdir_udp4_vxlan_pkt,\n+\t},\n \t{\n \t\tICE_FLTR_PTYPE_NONF_IPV6_TCP,\n \t\tsizeof(ice_fdir_tcpv6_pkt), ice_fdir_tcpv6_pkt,\n@@ -1102,6 +1122,29 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,\n \t\t\t\t  input->ip.v4.proto);\n \t\tice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac);\n \t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN:\n+\t\tice_pkt_insert_mac_addr(pkt, input->ext_data_outer.dst_mac);\n+\t\tice_pkt_insert_mac_addr(pkt + ETH_ALEN, input->ext_data_outer.src_mac);\n+\t\tice_pkt_insert_u32(pkt, ICE_IPV4_SRC_ADDR_OFFSET,\n+\t\t\t\t   input->ip_outer.v4.dst_ip);\n+\t\tice_pkt_insert_u32(pkt, ICE_IPV4_DST_ADDR_OFFSET,\n+\t\t\t\t   input->ip_outer.v4.src_ip);\n+\t\tice_pkt_insert_u8(pkt, ICE_IPV4_TOS_OFFSET, input->ip_outer.v4.tos);\n+\t\tice_pkt_insert_u32(pkt, ICE_IPV4_VXLAN_VNI_OFFSET,\n+\t\t\t\t   input->vxlan_data.vni);\n+\t\tice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,\n+\t\t\t\t   input->ip.v4.src_ip);\n+\t\tice_pkt_insert_u16(loc, ICE_IPV4_UDP_DST_PORT_OFFSET,\n+\t\t\t\t   input->ip.v4.src_port);\n+\t\tice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,\n+\t\t\t\t   input->ip.v4.dst_ip);\n+\t\tice_pkt_insert_u16(loc, ICE_IPV4_UDP_SRC_PORT_OFFSET,\n+\t\t\t\t   input->ip.v4.dst_port);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV4_TOS_OFFSET, input->ip.v4.tos);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV4_TTL_OFFSET, input->ip.v4.ttl);\n+\t\tice_pkt_insert_mac_addr(loc, input->ext_data.dst_mac);\n+\t\tice_pkt_insert_mac_addr(loc + ETH_ALEN, input->ext_data.src_mac);\n+\t\tbreak;\n \tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER:\n \t\tice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,\n \t\t\t\t   input->ip.v4.src_ip);\ndiff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h\nindex d363de385d..1c8de8956d 100644\n--- a/drivers/net/ice/base/ice_fdir.h\n+++ b/drivers/net/ice/base/ice_fdir.h\n@@ -55,6 +55,7 @@\n #define ICE_IPV6_AH_SPI_OFFSET\t\t58\n #define ICE_IPV4_NAT_T_ESP_SPI_OFFSET\t42\n #define ICE_IPV6_NAT_T_ESP_SPI_OFFSET\t62\n+#define ICE_IPV4_VXLAN_VNI_OFFSET\t45\n \n #define ICE_FDIR_MAX_FLTRS\t\t16384\n \n@@ -163,6 +164,10 @@ struct ice_fdir_l2tpv3 {\n \t__be32 session_id;\n };\n \n+struct ice_fdir_udp_vxlan {\n+\t__be32 vni; /* 8 bits reserved, always be zero */\n+};\n+\n struct ice_fdir_extra {\n \tu8 dst_mac[ETH_ALEN];\t/* dest MAC address */\n \tu8 src_mac[ETH_ALEN];\t/* src MAC address */\n@@ -190,6 +195,9 @@ struct ice_fdir_fltr {\n \tstruct ice_fdir_extra ext_data_outer;\n \tstruct ice_fdir_extra ext_mask_outer;\n \n+\tstruct ice_fdir_udp_vxlan vxlan_data;\n+\tstruct ice_fdir_udp_vxlan vxlan_mask;\n+\n \tstruct ice_fdir_udp_gtp gtpu_data;\n \tstruct ice_fdir_udp_gtp gtpu_mask;\n \ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex f667b8ef7d..bce90d9335 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -30,6 +30,7 @@\n #define ICE_FLOW_FLD_SZ_ESP_SPI\t4\n #define ICE_FLOW_FLD_SZ_AH_SPI\t4\n #define ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI\t4\n+#define ICE_FLOW_FLD_SZ_VXLAN_VNI\t4\n \n /* Describe properties of a protocol header field */\n struct ice_flow_field_info {\n@@ -189,6 +190,9 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {\n \t/* ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI */\n \tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NAT_T_ESP, 8,\n \t\t\t  ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI),\n+\t/* ICE_FLOW_FIELD_IDX_VXLAN_VNI */\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VXLAN, 12,\n+\t\t\t  ICE_FLOW_FLD_SZ_VXLAN_VNI),\n };\n \n /* Bitmaps indicating relevant packet types for a particular protocol header\n@@ -456,6 +460,18 @@ static const u32 ice_ptypes_gtpc[] = {\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n };\n \n+/* Packet types for VXLAN with VNI */\n+static const u32 ice_ptypes_vxlan_vni[] = {\n+\t0x00000000, 0xBFBFF800, 0x00EFDFDF, 0xFEFDE000,\n+\t0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+};\n+\n /* Packet types for GTPC with TEID */\n static const u32 ice_ptypes_gtpc_tid[] = {\n \t0x00000000, 0x00000000, 0x00000000, 0x00000000,\n@@ -974,6 +990,10 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)\n \t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_nat_t_esp;\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n \t\t\t\t       src, ICE_FLOW_PTYPE_MAX);\n+\t\t} else if (hdrs & ICE_FLOW_SEG_HDR_VXLAN) {\n+\t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_vxlan_vni;\n+\t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n+\t\t\t\t       src, ICE_FLOW_PTYPE_MAX);\n \t\t}\n \n \t\tif (hdrs & ICE_FLOW_SEG_HDR_PFCP) {\n@@ -1144,6 +1164,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \tcase ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:\n \t\tprot_id = ICE_PROT_SCTP_IL;\n \t\tbreak;\n+\tcase ICE_FLOW_FIELD_IDX_VXLAN_VNI:\n \tcase ICE_FLOW_FIELD_IDX_GTPC_TEID:\n \tcase ICE_FLOW_FIELD_IDX_GTPU_IP_TEID:\n \tcase ICE_FLOW_FIELD_IDX_GTPU_UP_TEID:\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex 2a9ae66454..23a98cfe89 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -72,6 +72,9 @@\n #define ICE_HASH_SCTP_IPV6_PRE64 \\\n \t(ICE_FLOW_HASH_IPV6_PRE64 | ICE_FLOW_HASH_SCTP_PORT)\n \n+#define ICE_FLOW_HASH_VXLAN_VNI \\\n+\t(BIT_ULL(ICE_FLOW_FIELD_IDX_VXLAN_VNI))\n+\n #define ICE_FLOW_HASH_GTP_TEID \\\n \t(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))\n \n@@ -179,6 +182,7 @@ enum ice_flow_seg_hdr {\n \tICE_FLOW_SEG_HDR_NAT_T_ESP\t= 0x00400000,\n \tICE_FLOW_SEG_HDR_ETH_NON_IP\t= 0x00800000,\n \tICE_FLOW_SEG_HDR_GTPU_NON_IP\t= 0x01000000,\n+\tICE_FLOW_SEG_HDR_VXLAN\t\t= 0x02000000,\n \t/* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and\n \t * ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs\n \t */\n@@ -267,6 +271,8 @@ enum ice_flow_field {\n \tICE_FLOW_FIELD_IDX_AH_SPI,\n \t/* NAT_T ESP */\n \tICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI,\n+\t/* VXLAN VNI */\n+\tICE_FLOW_FIELD_IDX_VXLAN_VNI,\n \t /* The total number of enums must not exceed 64 */\n \tICE_FLOW_FIELD_IDX_MAX\n };\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 7790ee2e54..4552288b85 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -329,6 +329,7 @@ enum ice_fltr_ptype {\n \tICE_FLTR_PTYPE_NONF_IPV6_TCP,\n \tICE_FLTR_PTYPE_NONF_IPV6_SCTP,\n \tICE_FLTR_PTYPE_NONF_IPV6_OTHER,\n+\tICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,\n \tICE_FLTR_PTYPE_MAX,\n };\n \n",
    "prefixes": [
        "15/27"
    ]
}