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GET /api/patches/84899/?format=api
{ "id": 84899, "url": "http://patches.dpdk.org/api/patches/84899/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201209235347.16180-6-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201209235347.16180-6-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201209235347.16180-6-ajit.khaparde@broadcom.com", "date": "2020-12-09T23:53:35", "name": "[v3,05/17] net/bnxt: remove references to Thor", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "605b12a1ebc4ddf8e39848d7ddc8a25a6a6bf2ac", "submitter": { "id": 2064, "url": "http://patches.dpdk.org/api/people/2064/?format=api", "name": "Ajit Khaparde", "email": "ajitkhaparde@gmail.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201209235347.16180-6-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 14226, "url": "http://patches.dpdk.org/api/series/14226/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14226", "date": "2020-12-09T23:53:30", "name": "fixes and refactoring changes for bnxt", "version": 3, "mbox": "http://patches.dpdk.org/series/14226/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/84899/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/84899/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6E24A04DB;\n\tThu, 10 Dec 2020 00:55:40 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 14AD5C9CC;\n\tThu, 10 Dec 2020 00:54:05 +0100 (CET)", "from mail-pl1-f195.google.com (mail-pl1-f195.google.com\n [209.85.214.195]) by dpdk.org (Postfix) with ESMTP id 00F13C9B2\n for <dev@dpdk.org>; Thu, 10 Dec 2020 00:54:01 +0100 (CET)", "by mail-pl1-f195.google.com with SMTP id u4so1812473plr.12\n for <dev@dpdk.org>; Wed, 09 Dec 2020 15:54:01 -0800 (PST)", "from localhost.localdomain ([192.19.228.250])\n by smtp.gmail.com with ESMTPSA id s7sm4047693pfh.207.2020.12.09.15.53.58\n for <dev@dpdk.org>\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Wed, 09 Dec 2020 15:53:58 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:subject:date:message-id:in-reply-to:references:mime-version\n :content-transfer-encoding;\n bh=Lanru/SQC8M99d5umQKQHOUPZsb8XRCTCQtaYxPlkXo=;\n b=RKoqA9EdkVjqjwrrv6VmqQRWszt7VbO2HjjwVLV6NV+1F45K8EBwg1vJIdy6sWuAK5\n yzGmJBfmHpDYfw0hS+bHdH9UzFNBO9zMcgprO0GZ/6YEIkf/mgBuA5NMiuRp5m6ivwUo\n xKH2mz3BxwH6AvpW6/5BorjgbwZPdTX1tYMcgohlE/MpHfh5Nwe4rsjb0H5cGJlAYMfe\n 0srHrxeU1gIjiDL3d8f4A8Wj6JVfvR1Kjz76IOx4O+j2X86VpU4F+ZRySrYnGUWVIksJ\n Q9O7lgLykwXSVAwIycxV5aGbuOOyyTzqvpPovAuHGlG93uzwe35hmFKoqjkz//ikizLb\n ZXeQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=Lanru/SQC8M99d5umQKQHOUPZsb8XRCTCQtaYxPlkXo=;\n b=PmCABkUVkU1Ywsw2t805/ks9kdT1yKz7LKchcmUk4sE7L9W4kVW/acwt1FL4uLUsZX\n 467twDTjUgc39j81fYdXdH1B+jLBhT+ZqzIm7HlukcjDZvDlkJutUo5vzCouVOvRQSYv\n wWKfBlOFB86MkYqapooJmr3+nV/siWBabKh4kXPKbbEQyNVRNrwy06GjdlF5l8mjngec\n UHFazOvM3S6fl59NHtBMv0IWPjfw4mXXSdkB7XFxh/edLhrAmGSzDlt5BdpDpVG42hyL\n OmkancosgUNN4gazLiXZIwQz1r1IW0+wtEJ4WhPI7kijf54TqFoe/0gmORYxH5kfbqsQ\n SLqQ==", "X-Gm-Message-State": "AOAM532mYr3WQjVO3C3sv5r5kMPmTtbN2otL/UpXKQQpoUi/xXFNjFH3\n JX7aoAk6w5tkHoS7T2Ah1jqJCgCb9vWcWcTc", "X-Google-Smtp-Source": "\n ABdhPJxDBguDUUyBkLQ/wJC29CDbtheh6WobpHRXEIIjmRIbfP68aMJpo0npQBN5Z0g5+vlVTC+iuA==", "X-Received": "by 2002:a17:902:8343:b029:da:cf6a:f65c with SMTP id\n z3-20020a1709028343b02900dacf6af65cmr4180066pln.5.1607558039584;\n Wed, 09 Dec 2020 15:53:59 -0800 (PST)", "From": "Ajit Khaparde <ajitkhaparde@gmail.com>", "X-Google-Original-From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Date": "Wed, 9 Dec 2020 15:53:35 -0800", "Message-Id": "<20201209235347.16180-6-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20201209235347.16180-1-ajit.khaparde@broadcom.com>", "References": "<20201209192233.6518-1-ajit.khaparde@broadcom.com>\n <20201209235347.16180-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 05/17] net/bnxt: remove references to Thor", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Refactor code to remove references to Thor.\nInstead use P5 as in phase 5 of development cycle since it is applicable\nto boards other than Thor as well.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 20 +++++++-------\n drivers/net/bnxt/bnxt_ethdev.c | 43 +++++++++++++++--------------\n drivers/net/bnxt/bnxt_hwrm.c | 44 +++++++++++++++---------------\n drivers/net/bnxt/bnxt_ring.c | 8 +++---\n drivers/net/bnxt/bnxt_rxq.c | 4 +--\n drivers/net/bnxt/bnxt_rxr.c | 12 ++++----\n drivers/net/bnxt/bnxt_rxr.h | 2 +-\n drivers/net/bnxt/bnxt_vnic.c | 4 +--\n drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 +-\n 9 files changed, 70 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex f13d586d4..9c1c87489 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -112,11 +112,11 @@\n #define TPA_MAX_SEGS\t\t5 /* 32 segments in log2 units */\n \n #define BNXT_TPA_MAX_AGGS(bp) \\\n-\t(BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \\\n+\t(BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \\\n \t\t\t TPA_MAX_AGGS)\n \n #define BNXT_TPA_MAX_SEGS(bp) \\\n-\t(BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \\\n+\t(BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \\\n \t\t\t TPA_MAX_SEGS)\n \n /*\n@@ -389,10 +389,10 @@ struct bnxt_coal {\n #define DBR_TYPE_NQ\t\t\t\t(0xaULL << 60)\n #define DBR_TYPE_NQ_ARM\t\t\t\t(0xbULL << 60)\n \n-#define BNXT_RSS_TBL_SIZE_THOR\t\t512U\n-#define BNXT_RSS_ENTRIES_PER_CTX_THOR\t64\n-#define BNXT_MAX_RSS_CTXTS_THOR \\\n-\t(BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)\n+#define BNXT_RSS_TBL_SIZE_P5\t\t512U\n+#define BNXT_RSS_ENTRIES_PER_CTX_P5\t64\n+#define BNXT_MAX_RSS_CTXTS_P5 \\\n+\t(BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5)\n \n #define BNXT_MAX_TC 8\n #define BNXT_MAX_QUEUE 8\n@@ -629,7 +629,7 @@ struct bnxt {\n #define BNXT_FLAG_KONG_MB_EN\t\tBIT(10)\n #define BNXT_FLAG_TRUSTED_VF_EN\t\tBIT(11)\n #define BNXT_FLAG_DFLT_VNIC_SET\t\tBIT(12)\n-#define BNXT_FLAG_THOR_CHIP\t\tBIT(13)\n+#define BNXT_FLAG_CHIP_P5\t\tBIT(13)\n #define BNXT_FLAG_STINGRAY\t\tBIT(14)\n #define BNXT_FLAG_FW_RESET\t\tBIT(15)\n #define BNXT_FLAG_FATAL_ERROR\t\tBIT(16)\n@@ -653,10 +653,10 @@ struct bnxt {\n #define BNXT_USE_CHIMP_MB\t0 //For non-CFA commands, everything uses Chimp.\n #define BNXT_USE_KONG(bp)\t((bp)->flags & BNXT_FLAG_KONG_MB_EN)\n #define BNXT_VF_IS_TRUSTED(bp)\t((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)\n-#define BNXT_CHIP_THOR(bp)\t((bp)->flags & BNXT_FLAG_THOR_CHIP)\n+#define BNXT_CHIP_P5(bp)\t((bp)->flags & BNXT_FLAG_CHIP_P5)\n #define BNXT_STINGRAY(bp)\t((bp)->flags & BNXT_FLAG_STINGRAY)\n-#define BNXT_HAS_NQ(bp)\t\tBNXT_CHIP_THOR(bp)\n-#define BNXT_HAS_RING_GRPS(bp)\t(!BNXT_CHIP_THOR(bp))\n+#define BNXT_HAS_NQ(bp)\t\tBNXT_CHIP_P5(bp)\n+#define BNXT_HAS_RING_GRPS(bp)\t(!BNXT_CHIP_P5(bp))\n #define BNXT_FLOW_XSTATS_EN(bp)\t((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)\n #define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)\n #define BNXT_TRUFLOW_EN(bp)\t((bp)->flags & BNXT_FLAG_TRUFLOW_EN)\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex c363c8427..8047b0b5d 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -208,22 +208,22 @@ int is_bnxt_in_error(struct bnxt *bp)\n static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)\n {\n \tunsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,\n-\t\t\t\t\t BNXT_RSS_TBL_SIZE_THOR);\n+\t\t\t\t\t BNXT_RSS_TBL_SIZE_P5);\n \n-\tif (!BNXT_CHIP_THOR(bp))\n+\tif (!BNXT_CHIP_P5(bp))\n \t\treturn 1;\n \n \treturn RTE_ALIGN_MUL_CEIL(num_rss_rings,\n-\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_THOR) /\n-\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_THOR;\n+\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_P5) /\n+\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_P5;\n }\n \n uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)\n {\n-\tif (!BNXT_CHIP_THOR(bp))\n+\tif (!BNXT_CHIP_P5(bp))\n \t\treturn HW_HASH_INDEX_SIZE;\n \n-\treturn bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;\n+\treturn bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;\n }\n \n static void bnxt_free_parent_info(struct bnxt *bp)\n@@ -427,12 +427,12 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)\n \tif (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {\n \t\tint j, nr_ctxs = bnxt_rss_ctxts(bp);\n \n-\t\tif (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_THOR) {\n+\t\tif (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {\n \t\t\tPMD_DRV_LOG(ERR, \"RxQ cnt %d > reta_size %d\\n\",\n-\t\t\t\t bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_THOR);\n+\t\t\t\t bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);\n \t\t\tPMD_DRV_LOG(ERR,\n \t\t\t\t \"Only queues 0-%d will be in RSS table\\n\",\n-\t\t\t\t BNXT_RSS_TBL_SIZE_THOR - 1);\n+\t\t\t\t BNXT_RSS_TBL_SIZE_P5 - 1);\n \t\t}\n \n \t\trc = 0;\n@@ -712,8 +712,8 @@ static int bnxt_init_chip(struct bnxt *bp)\n \t/* THOR does not support ring groups.\n \t * But we will use the array to save RSS context IDs.\n \t */\n-\tif (BNXT_CHIP_THOR(bp))\n-\t\tbp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;\n+\tif (BNXT_CHIP_P5(bp))\n+\t\tbp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;\n \n \trc = bnxt_alloc_all_hwrm_stat_ctxs(bp);\n \tif (rc) {\n@@ -1832,7 +1832,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\tif (BNXT_CHIP_THOR(bp)) {\n+\t\tif (BNXT_CHIP_P5(bp)) {\n \t\t\tvnic->rss_table[i * 2] =\n \t\t\t\trxq->rx_ring->rx_ring_struct->fw_ring_id;\n \t\t\tvnic->rss_table[i * 2 + 1] =\n@@ -1881,7 +1881,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,\n \t\tif (reta_conf[idx].mask & (1ULL << sft)) {\n \t\t\tuint16_t qid;\n \n-\t\t\tif (BNXT_CHIP_THOR(bp))\n+\t\t\tif (BNXT_CHIP_P5(bp))\n \t\t\t\tqid = bnxt_rss_to_qid(bp,\n \t\t\t\t\t\t vnic->rss_table[i * 2]);\n \t\t\telse\n@@ -3232,7 +3232,7 @@ bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n \tif (!ptp)\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_THOR(bp))\n+\tif (BNXT_CHIP_P5(bp))\n \t\trc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,\n \t\t\t\t\t &systime_cycles);\n \telse\n@@ -3278,7 +3278,7 @@ bnxt_timesync_enable(struct rte_eth_dev *dev)\n \tptp->tx_tstamp_tc.cc_shift = shift;\n \tptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;\n \n-\tif (!BNXT_CHIP_THOR(bp))\n+\tif (!BNXT_CHIP_P5(bp))\n \t\tbnxt_map_ptp_regs(bp);\n \n \treturn 0;\n@@ -3299,7 +3299,7 @@ bnxt_timesync_disable(struct rte_eth_dev *dev)\n \n \tbnxt_hwrm_ptp_cfg(bp);\n \n-\tif (!BNXT_CHIP_THOR(bp))\n+\tif (!BNXT_CHIP_P5(bp))\n \t\tbnxt_unmap_ptp_regs(bp);\n \n \treturn 0;\n@@ -3318,7 +3318,7 @@ bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \tif (!ptp)\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_THOR(bp))\n+\tif (BNXT_CHIP_P5(bp))\n \t\trx_tstamp_cycles = ptp->rx_timestamp;\n \telse\n \t\tbnxt_get_rx_ts(bp, &rx_tstamp_cycles);\n@@ -3341,7 +3341,7 @@ bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \tif (!ptp)\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_THOR(bp))\n+\tif (BNXT_CHIP_P5(bp))\n \t\trc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,\n \t\t\t\t\t &tx_tstamp_cycles);\n \telse\n@@ -4007,7 +4007,8 @@ static bool bnxt_vf_pciid(uint16_t device_id)\n \t}\n }\n \n-static bool bnxt_thor_device(uint16_t device_id)\n+/* Phase 5 device */\n+static bool bnxt_p5_device(uint16_t device_id)\n {\n \tswitch (device_id) {\n \tcase BROADCOM_DEV_ID_57508:\n@@ -5240,8 +5241,8 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)\n \tif (bnxt_vf_pciid(pci_dev->id.device_id))\n \t\tbp->flags |= BNXT_FLAG_VF;\n \n-\tif (bnxt_thor_device(pci_dev->id.device_id))\n-\t\tbp->flags |= BNXT_FLAG_THOR_CHIP;\n+\tif (bnxt_p5_device(pci_dev->id.device_id))\n+\t\tbp->flags |= BNXT_FLAG_CHIP_P5;\n \n \tif (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||\n \t pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 784e9778a..6f5402070 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -635,7 +635,7 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)\n \n \tHWRM_CHECK_RESULT();\n \n-\tif (!BNXT_CHIP_THOR(bp) &&\n+\tif (!BNXT_CHIP_P5(bp) &&\n \t !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))\n \t\treturn 0;\n \n@@ -646,7 +646,7 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)\n \tif (!ptp)\n \t\treturn -ENOMEM;\n \n-\tif (!BNXT_CHIP_THOR(bp)) {\n+\tif (!BNXT_CHIP_P5(bp)) {\n \t\tptp->rx_regs[BNXT_PTP_RX_TS_L] =\n \t\t\trte_le_to_cpu_32(resp->rx_ts_reg_off_lower);\n \t\tptp->rx_regs[BNXT_PTP_RX_TS_H] =\n@@ -766,7 +766,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \tbp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);\n \tbp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);\n \tbp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);\n-\tif (!BNXT_CHIP_THOR(bp) && !bp->pdev->max_vfs)\n+\tif (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)\n \t\tbp->max_l2_ctx += bp->max_rx_em_flows;\n \t/* TODO: For now, do not support VMDq/RFS on VFs. */\n \tif (BNXT_PF(bp)) {\n@@ -1056,7 +1056,7 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)\n \t * So use the value provided by func_qcaps.\n \t */\n \tbp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);\n-\tif (!BNXT_CHIP_THOR(bp) && !bp->pdev->max_vfs)\n+\tif (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)\n \t\tbp->max_l2_ctx += bp->max_rx_em_flows;\n \tbp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);\n \tbp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);\n@@ -1557,7 +1557,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp,\n \t\treq.ring_type = ring_type;\n \t\treq.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);\n \t\treq.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);\n-\t\tif (BNXT_CHIP_THOR(bp)) {\n+\t\tif (BNXT_CHIP_P5(bp)) {\n \t\t\tmb_pool = bp->rx_queues[0]->mb_pool;\n \t\t\trx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -\n \t\t\t\t RTE_PKTMBUF_HEADROOM;\n@@ -1927,7 +1927,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \n \tHWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);\n \n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\tint dflt_rxq = vnic->start_grp_id;\n \t\tstruct bnxt_rx_ring_info *rxr;\n \t\tstruct bnxt_cp_ring_info *cpr;\n@@ -2117,7 +2117,7 @@ int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n \tint rc = 0;\n \n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\tint j;\n \n \t\tfor (j = 0; j < vnic->num_lb_ctxts; j++) {\n@@ -2164,7 +2164,7 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n }\n \n static int\n-bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n \tint i;\n \tint rc = 0;\n@@ -2208,8 +2208,8 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \tif (!vnic->rss_table)\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_THOR(bp))\n-\t\treturn bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);\n+\tif (BNXT_CHIP_P5(bp))\n+\t\treturn bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);\n \n \tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n@@ -2274,7 +2274,7 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,\n \tstruct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n-\tif (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {\n+\tif (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {\n \t\tif (enable)\n \t\t\tPMD_DRV_LOG(ERR, \"No HW support for LRO\\n\");\n \t\treturn -ENOTSUP;\n@@ -2566,7 +2566,7 @@ void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)\n \tring = rxr->ag_ring_struct;\n \tif (ring->fw_ring_id != INVALID_HW_RING_ID) {\n \t\tbnxt_hwrm_ring_free(bp, ring,\n-\t\t\t\t BNXT_CHIP_THOR(bp) ?\n+\t\t\t\t BNXT_CHIP_P5(bp) ?\n \t\t\t\t HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :\n \t\t\t\t HWRM_RING_FREE_INPUT_RING_TYPE_RX);\n \t\tif (BNXT_HAS_RING_GRPS(bp))\n@@ -3068,7 +3068,7 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)\n \t\tgoto port_phy_cfg;\n \n \tautoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);\n-\tif (BNXT_CHIP_THOR(bp) &&\n+\tif (BNXT_CHIP_P5(bp) &&\n \t dev_conf->link_speeds == ETH_LINK_SPEED_40G) {\n \t\t/* 40G is not supported as part of media auto detect.\n \t\t * The speed should be forced and autoneg disabled\n@@ -3093,7 +3093,7 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)\n \t * to 40G until link comes up at new speed.\n \t */\n \tif (autoneg == 1 &&\n-\t !(!BNXT_CHIP_THOR(bp) &&\n+\t !(!BNXT_CHIP_P5(bp) &&\n \t (bp->link_info->auto_link_speed ||\n \t bp->link_info->force_link_speed))) {\n \t\tlink_req.phy_flags |=\n@@ -4820,7 +4820,7 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,\n }\n \n static int\n-bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n \tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \tuint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;\n@@ -4844,7 +4844,7 @@ bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \n \t\treq.ring_grp_tbl_addr =\n \t\t rte_cpu_to_le_64(vnic->rss_table_dma_addr +\n-\t\t\t\t i * BNXT_RSS_ENTRIES_PER_CTX_THOR *\n+\t\t\t\t i * BNXT_RSS_ENTRIES_PER_CTX_P5 *\n \t\t\t\t 2 * sizeof(*ring_tbl));\n \t\treq.hash_key_tbl_addr =\n \t\t rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);\n@@ -4899,8 +4899,8 @@ int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \tif (!(vnic->rss_table && vnic->hash_type))\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_THOR(bp))\n-\t\treturn bnxt_vnic_rss_configure_thor(bp, vnic);\n+\tif (BNXT_CHIP_P5(bp))\n+\t\treturn bnxt_vnic_rss_configure_p5(bp, vnic);\n \n \tif (vnic->fw_vnic_id == INVALID_HW_RING_ID)\n \t\treturn 0;\n@@ -4959,7 +4959,7 @@ static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,\n \treq->flags = rte_cpu_to_le_16(flags);\n }\n \n-static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,\n+static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,\n \t\tstruct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)\n {\n \tstruct hwrm_ring_aggint_qcaps_input req = {0};\n@@ -4996,8 +4996,8 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp,\n \tint rc;\n \n \t/* Set ring coalesce parameters only for 100G NICs */\n-\tif (BNXT_CHIP_THOR(bp)) {\n-\t\tif (bnxt_hwrm_set_coal_params_thor(bp, &req))\n+\tif (BNXT_CHIP_P5(bp)) {\n+\t\tif (bnxt_hwrm_set_coal_params_p5(bp, &req))\n \t\t\treturn -1;\n \t} else if (bnxt_stratus_device(bp)) {\n \t\tbnxt_hwrm_set_coal_params(coal, &req);\n@@ -5026,7 +5026,7 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n \tint total_alloc_len;\n \tint rc, i, tqm_rings;\n \n-\tif (!BNXT_CHIP_THOR(bp) ||\n+\tif (!BNXT_CHIP_P5(bp) ||\n \t bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||\n \t BNXT_VF(bp) ||\n \t bp->ctx)\ndiff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c\nindex aeb6cb615..579c48d8c 100644\n--- a/drivers/net/bnxt/bnxt_ring.c\n+++ b/drivers/net/bnxt/bnxt_ring.c\n@@ -57,8 +57,8 @@ int bnxt_alloc_ring_grps(struct bnxt *bp)\n \t/* THOR does not support ring groups.\n \t * But we will use the array to save RSS context IDs.\n \t */\n-\tif (BNXT_CHIP_THOR(bp)) {\n-\t\tbp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;\n+\tif (BNXT_CHIP_P5(bp)) {\n+\t\tbp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;\n \t} else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {\n \t\t/* 1 ring is for default completion ring */\n \t\tPMD_DRV_LOG(ERR, \"Insufficient resource: Ring Group\\n\");\n@@ -344,7 +344,7 @@ static void bnxt_set_db(struct bnxt *bp,\n \t\t\tuint32_t map_idx,\n \t\t\tuint32_t fid)\n {\n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\tif (BNXT_PF(bp))\n \t\t\tdb->doorbell = (char *)bp->doorbell_base + 0x10000;\n \t\telse\n@@ -538,7 +538,7 @@ static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)\n \n \tring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id;\n \n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\tring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG;\n \t\thw_stats_ctx_id = cpr->hw_stats_ctx_id;\n \t} else {\ndiff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c\nindex 61196eba9..328cc994d 100644\n--- a/drivers/net/bnxt/bnxt_rxq.c\n+++ b/drivers/net/bnxt/bnxt_rxq.c\n@@ -472,7 +472,7 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \tif (rc)\n \t\treturn rc;\n \n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\t/* Reconfigure default receive ring and MRU. */\n \t\tbnxt_hwrm_vnic_cfg(bp, rxq->vnic);\n \t}\n@@ -562,7 +562,7 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\tif (bp->rx_queues[i]->rx_started)\n \t\t\tactive_queue_cnt++;\n \n-\tif (BNXT_CHIP_THOR(bp)) {\n+\tif (BNXT_CHIP_P5(bp)) {\n \t\t/*\n \t\t * For Thor, we need to ensure that the VNIC default receive\n \t\t * ring corresponds to an active receive queue. When no queue\ndiff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c\nindex af1774844..e9c4fffed 100644\n--- a/drivers/net/bnxt/bnxt_rxr.c\n+++ b/drivers/net/bnxt/bnxt_rxr.c\n@@ -225,13 +225,13 @@ static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,\n \tuint16_t cp_cons, ag_cons;\n \tstruct rx_pkt_cmpl *rxcmp;\n \tstruct rte_mbuf *last = mbuf;\n-\tbool is_thor_tpa = tpa_info && BNXT_CHIP_THOR(rxq->bp);\n+\tbool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);\n \n \tfor (i = 0; i < agg_buf; i++) {\n \t\tstruct rte_mbuf **ag_buf;\n \t\tstruct rte_mbuf *ag_mbuf;\n \n-\t\tif (is_thor_tpa) {\n+\t\tif (is_p5_tpa) {\n \t\t\trxcmp = (void *)&tpa_info->agg_arr[i];\n \t\t} else {\n \t\t\t*tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);\n@@ -285,7 +285,7 @@ static inline struct rte_mbuf *bnxt_tpa_end(\n \tuint8_t payload_offset;\n \tstruct bnxt_tpa_info *tpa_info;\n \n-\tif (BNXT_CHIP_THOR(rxq->bp)) {\n+\tif (BNXT_CHIP_P5(rxq->bp)) {\n \t\tstruct rx_tpa_v2_end_cmpl *th_tpa_end;\n \t\tstruct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;\n \n@@ -497,11 +497,11 @@ bnxt_set_ol_flags(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1,\n \n #ifdef RTE_LIBRTE_IEEE1588\n static void\n-bnxt_get_rx_ts_thor(struct bnxt *bp, uint32_t rx_ts_cmpl)\n+bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)\n {\n \tuint64_t systime_cycles = 0;\n \n-\tif (!BNXT_CHIP_THOR(bp))\n+\tif (!BNXT_CHIP_P5(bp))\n \t\treturn;\n \n \t/* On Thor, Rx timestamps are provided directly in the\n@@ -747,7 +747,7 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \t\t RX_PKT_CMPL_FLAGS_MASK) ==\n \t\t RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) {\n \t\tmbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;\n-\t\tbnxt_get_rx_ts_thor(rxq->bp, rxcmp1->reorder);\n+\t\tbnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);\n \t}\n #endif\n \ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nindex 3fc901fdf..2a53cf87b 100644\n--- a/drivers/net/bnxt/bnxt_rxr.h\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -17,7 +17,7 @@\n static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,\n \t\t\t\t\t struct rx_tpa_start_cmpl *cmp)\n {\n-\tif (BNXT_CHIP_THOR(bp))\n+\tif (BNXT_CHIP_P5(bp))\n \t\treturn BNXT_TPA_START_AGG_ID_TH(cmp);\n \telse\n \t\treturn BNXT_TPA_START_AGG_ID_PRE_TH(cmp);\ndiff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c\nindex 1602fb2b8..4d378eca4 100644\n--- a/drivers/net/bnxt/bnxt_vnic.c\n+++ b/drivers/net/bnxt/bnxt_vnic.c\n@@ -129,8 +129,8 @@ int bnxt_alloc_vnic_attributes(struct bnxt *bp)\n \tentry_length = HW_HASH_KEY_SIZE +\n \t\t BNXT_MAX_MC_ADDRS * RTE_ETHER_ADDR_LEN;\n \n-\tif (BNXT_CHIP_THOR(bp))\n-\t\trss_table_size = BNXT_RSS_TBL_SIZE_THOR *\n+\tif (BNXT_CHIP_P5(bp))\n+\t\trss_table_size = BNXT_RSS_TBL_SIZE_P5 *\n \t\t\t\t 2 * sizeof(*vnic->rss_table);\n \telse\n \t\trss_table_size = HW_HASH_INDEX_SIZE * sizeof(*vnic->rss_table);\ndiff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\nindex 26fd3009f..de47fde88 100644\n--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c\n@@ -52,7 +52,7 @@ static int32_t\n bnxt_ulp_devid_get(struct bnxt *bp,\n \t\t enum bnxt_ulp_device_id *ulp_dev_id)\n {\n-\tif (BNXT_CHIP_THOR(bp))\n+\tif (BNXT_CHIP_P5(bp))\n \t\treturn -EINVAL;\n \t/* Assuming Whitney */\n \t*ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS;\n", "prefixes": [ "v3", "05/17" ] }