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GET /api/patches/83955/?format=api
{ "id": 83955, "url": "http://patches.dpdk.org/api/patches/83955/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201111064936.768604-15-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201111064936.768604-15-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201111064936.768604-15-jiawenwu@trustnetic.com", "date": "2020-11-11T06:49:13", "name": "[v2,14/37] net/txgbe: configure FDIR filter", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "4bca39ab50bdeaf182a234ad82734168cf8bf2a5", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201111064936.768604-15-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13798, "url": "http://patches.dpdk.org/api/series/13798/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13798", "date": "2020-11-11T06:49:00", "name": "net: add txgbe PMD part 2", "version": 2, "mbox": "http://patches.dpdk.org/series/13798/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/83955/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/83955/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 66021A09D2;\n\tWed, 11 Nov 2020 07:51:48 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B9DBAAA31;\n\tWed, 11 Nov 2020 07:47:52 +0100 (CET)", "from smtpproxy21.qq.com (smtpbg702.qq.com [203.205.195.102])\n by dpdk.org (Postfix) with ESMTP id EECA16947\n for <dev@dpdk.org>; Wed, 11 Nov 2020 07:47:42 +0100 (CET)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp10.qq.com (ESMTP) with\n id ; Wed, 11 Nov 2020 14:47:38 +0800 (CST)" ], "X-QQ-mid": "bizesmtp27t1605077258tgge7is8", "X-QQ-SSF": "01400000000000C0C000B00A0000000", "X-QQ-FEAT": "SMzIe2qKYdPQ958EB3cNenFxsUnlKrkSxmnBwet9WdOB5BRkPtubnqFObJcht\n dNlrINscFPPA+TbWZEy2H4NJBOMW5x8kZKfmRpxlhs1Dg3rwIZHMEQ1pWaLjwRXF2KRr0gL\n KcigjdF3FkMamLBMUBp4ZcanBjgvCafKc6U/fufax8Wz6PnxLuOxcaJcQ9lGwKNY1yjWCDr\n Xyobtkt40BlZ1ITgNpUuMDO4t5cmSKFBZpbySQAPd+BQJhqxwMOSwpJxVAmZWMVKpR1VASe\n VujxOeNoofwcHH/zzDd/5CBhZUnYtGcanSMih29AX5RST3Dr+2UjpaVJXMTk4I2j6XaooL4\n EzfzsCzTxljuCu3JAbPhJdBY8uudg==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Wed, 11 Nov 2020 14:49:13 +0800", "Message-Id": "<20201111064936.768604-15-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201111064936.768604-1-jiawenwu@trustnetic.com>", "References": "<20201111064936.768604-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign6", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 14/37] net/txgbe: configure FDIR filter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Configure flow director filter with it enabled.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_type.h | 6 +\n drivers/net/txgbe/meson.build | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 6 +\n drivers/net/txgbe/txgbe_ethdev.h | 6 +\n drivers/net/txgbe/txgbe_fdir.c | 407 ++++++++++++++++++++++++++++\n 5 files changed, 426 insertions(+)\n create mode 100644 drivers/net/txgbe/txgbe_fdir.c", "diff": "diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex b9d31ab83..633692cd7 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -21,6 +21,8 @@\n #define TXGBE_MAX_QP\t\t(128)\n #define TXGBE_MAX_UTA\t\t128\n \n+#define TXGBE_FDIR_INIT_DONE_POLL\t\t10\n+\n #define TXGBE_ALIGN\t\t128 /* as intel did */\n \n #include \"txgbe_status.h\"\n@@ -65,6 +67,10 @@ enum {\n #define TXGBE_PHYSICAL_LAYER_10BASE_T\t\t0x08000\n #define TXGBE_PHYSICAL_LAYER_2500BASE_KX\t0x10000\n \n+/* Software ATR hash keys */\n+#define TXGBE_ATR_BUCKET_HASH_KEY\t\t0x3DAD14E2\n+#define TXGBE_ATR_SIGNATURE_HASH_KEY\t\t0x174D3614\n+\n #define TXGBE_ATR_HASH_MASK\t\t\t0x7fff\n \n /* Flow Director ATR input struct. */\ndiff --git a/drivers/net/txgbe/meson.build b/drivers/net/txgbe/meson.build\nindex 45379175d..bb1683631 100644\n--- a/drivers/net/txgbe/meson.build\n+++ b/drivers/net/txgbe/meson.build\n@@ -6,6 +6,7 @@ objs = [base_objs]\n \n sources = files(\n \t'txgbe_ethdev.c',\n+\t'txgbe_fdir.c',\n \t'txgbe_flow.c',\n \t'txgbe_ptypes.c',\n \t'txgbe_pf.c',\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 589306f0a..75a170764 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -1633,6 +1633,12 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \ttxgbe_configure_port(dev);\n \ttxgbe_configure_dcb(dev);\n \n+\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {\n+\t\terr = txgbe_fdir_configure(dev);\n+\t\tif (err)\n+\t\t\tgoto error;\n+\t}\n+\n \t/* Restore vf rate limit */\n \tif (vfinfo != NULL) {\n \t\tfor (vf = 0; vf < pci_dev->max_vfs; vf++)\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex f33ca1d32..cd24efeea 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -13,6 +13,7 @@\n #include <rte_time.h>\n #include <rte_hash.h>\n #include <rte_hash_crc.h>\n+#include <rte_ethdev.h>\n \n /* need update link, bit flag */\n #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n@@ -430,6 +431,11 @@ txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,\n void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,\n \t\t\t uint8_t queue, uint8_t msix_vector);\n \n+/*\n+ * Flow director function prototypes\n+ */\n+int txgbe_fdir_configure(struct rte_eth_dev *dev);\n+int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);\n void txgbe_configure_pb(struct rte_eth_dev *dev);\n void txgbe_configure_port(struct rte_eth_dev *dev);\n void txgbe_configure_dcb(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/txgbe/txgbe_fdir.c b/drivers/net/txgbe/txgbe_fdir.c\nnew file mode 100644\nindex 000000000..df6125d4a\n--- /dev/null\n+++ b/drivers/net/txgbe/txgbe_fdir.c\n@@ -0,0 +1,407 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdarg.h>\n+#include <errno.h>\n+#include <sys/queue.h>\n+\n+\n+#include \"txgbe_logs.h\"\n+#include \"base/txgbe.h\"\n+#include \"txgbe_ethdev.h\"\n+\n+#define TXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /*default flexbytes offset in bytes*/\n+#define TXGBE_MAX_FLX_SOURCE_OFF 62\n+\n+#define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \\\n+\tuint8_t ipv6_addr[16]; \\\n+\tuint8_t i; \\\n+\trte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\\\n+\t(ipv6m) = 0; \\\n+\tfor (i = 0; i < sizeof(ipv6_addr); i++) { \\\n+\t\tif (ipv6_addr[i] == UINT8_MAX) \\\n+\t\t\t(ipv6m) |= 1 << i; \\\n+\t\telse if (ipv6_addr[i] != 0) { \\\n+\t\t\tPMD_DRV_LOG(ERR, \" invalid IPv6 address mask.\"); \\\n+\t\t\treturn -EINVAL; \\\n+\t\t} \\\n+\t} \\\n+} while (0)\n+\n+#define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \\\n+\tuint8_t ipv6_addr[16]; \\\n+\tuint8_t i; \\\n+\tfor (i = 0; i < sizeof(ipv6_addr); i++) { \\\n+\t\tif ((ipv6m) & (1 << i)) \\\n+\t\t\tipv6_addr[i] = UINT8_MAX; \\\n+\t\telse \\\n+\t\t\tipv6_addr[i] = 0; \\\n+\t} \\\n+\trte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\\\n+} while (0)\n+\n+/**\n+ * Initialize Flow Director control registers\n+ * @hw: pointer to hardware structure\n+ * @fdirctrl: value to write to flow director control register\n+ **/\n+static int\n+txgbe_fdir_enable(struct txgbe_hw *hw, uint32_t fdirctrl)\n+{\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Prime the keys for hashing */\n+\twr32(hw, TXGBE_FDIRBKTHKEY, TXGBE_ATR_BUCKET_HASH_KEY);\n+\twr32(hw, TXGBE_FDIRSIGHKEY, TXGBE_ATR_SIGNATURE_HASH_KEY);\n+\n+\t/*\n+\t * Continue setup of fdirctrl register bits:\n+\t * Set the maximum length per hash bucket to 0xA filters\n+\t * Send interrupt when 64 filters are left\n+\t */\n+\tfdirctrl |= TXGBE_FDIRCTL_MAXLEN(0xA) |\n+\t\t TXGBE_FDIRCTL_FULLTHR(4);\n+\n+\t/*\n+\t * Poll init-done after we write the register. Estimated times:\n+\t * 10G: PBALLOC = 11b, timing is 60us\n+\t * 1G: PBALLOC = 11b, timing is 600us\n+\t * 100M: PBALLOC = 11b, timing is 6ms\n+\t *\n+\t * Multiple these timings by 4 if under full Rx load\n+\t *\n+\t * So we'll poll for TXGBE_FDIR_INIT_DONE_POLL times, sleeping for\n+\t * 1 msec per poll time. If we're at line rate and drop to 100M, then\n+\t * this might not finish in our poll time, but we can live with that\n+\t * for now.\n+\t */\n+\twr32(hw, TXGBE_FDIRCTL, fdirctrl);\n+\ttxgbe_flush(hw);\n+\tfor (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {\n+\t\tif (rd32(hw, TXGBE_FDIRCTL) & TXGBE_FDIRCTL_INITDONE)\n+\t\t\tbreak;\n+\t\tmsec_delay(1);\n+\t}\n+\n+\tif (i >= TXGBE_FDIR_INIT_DONE_POLL) {\n+\t\tPMD_INIT_LOG(ERR, \"Flow Director poll time exceeded during enabling!\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Set appropriate bits in fdirctrl for: variable reporting levels, moving\n+ * flexbytes matching field, and drop queue (only for perfect matching mode).\n+ */\n+static inline int\n+configure_fdir_flags(const struct rte_fdir_conf *conf,\n+\t\t uint32_t *fdirctrl, uint32_t *flex)\n+{\n+\t*fdirctrl = 0;\n+\t*flex = 0;\n+\n+\tswitch (conf->pballoc) {\n+\tcase RTE_FDIR_PBALLOC_64K:\n+\t\t/* 8k - 1 signature filters */\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_BUF_64K;\n+\t\tbreak;\n+\tcase RTE_FDIR_PBALLOC_128K:\n+\t\t/* 16k - 1 signature filters */\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_BUF_128K;\n+\t\tbreak;\n+\tcase RTE_FDIR_PBALLOC_256K:\n+\t\t/* 32k - 1 signature filters */\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_BUF_256K;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* bad value */\n+\t\tPMD_INIT_LOG(ERR, \"Invalid fdir_conf->pballoc value\");\n+\t\treturn -EINVAL;\n+\t};\n+\n+\t/* status flags: write hash & swindex in the rx descriptor */\n+\tswitch (conf->status) {\n+\tcase RTE_FDIR_NO_REPORT_STATUS:\n+\t\t/* do nothing, default mode */\n+\t\tbreak;\n+\tcase RTE_FDIR_REPORT_STATUS:\n+\t\t/* report status when the packet matches a fdir rule */\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_REPORT_MATCH;\n+\t\tbreak;\n+\tcase RTE_FDIR_REPORT_STATUS_ALWAYS:\n+\t\t/* always report status */\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_REPORT_ALWAYS;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* bad value */\n+\t\tPMD_INIT_LOG(ERR, \"Invalid fdir_conf->status value\");\n+\t\treturn -EINVAL;\n+\t};\n+\n+\t*flex |= TXGBE_FDIRFLEXCFG_BASE_MAC;\n+\t*flex |= TXGBE_FDIRFLEXCFG_OFST(TXGBE_DEFAULT_FLEXBYTES_OFFSET / 2);\n+\n+\tswitch (conf->mode) {\n+\tcase RTE_FDIR_MODE_SIGNATURE:\n+\t\tbreak;\n+\tcase RTE_FDIR_MODE_PERFECT:\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_PERFECT;\n+\t\t*fdirctrl |= TXGBE_FDIRCTL_DROPQP(conf->drop_queue);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* bad value */\n+\t\tPMD_INIT_LOG(ERR, \"Invalid fdir_conf->mode value\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline uint32_t\n+reverse_fdir_bmks(uint16_t hi_dword, uint16_t lo_dword)\n+{\n+\tuint32_t mask = hi_dword << 16;\n+\n+\tmask |= lo_dword;\n+\tmask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);\n+\tmask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);\n+\tmask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);\n+\treturn ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);\n+}\n+\n+int\n+txgbe_fdir_set_input_mask(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_hw_fdir_info *info = TXGBE_DEV_FDIR(dev);\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n+\t/*\n+\t * mask VM pool and DIPv6 since there are currently not supported\n+\t * mask FLEX byte, it will be set in flex_conf\n+\t */\n+\tuint32_t fdirm = TXGBE_FDIRMSK_POOL;\n+\tuint32_t fdirtcpm; /* TCP source and destination port masks. */\n+\tuint32_t fdiripv6m; /* IPv6 source and destination masks. */\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (mode != RTE_FDIR_MODE_SIGNATURE &&\n+\t mode != RTE_FDIR_MODE_PERFECT) {\n+\t\tPMD_DRV_LOG(ERR, \"Not supported fdir mode - %d!\", mode);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/*\n+\t * Program the relevant mask registers. If src/dst_port or src/dst_addr\n+\t * are zero, then assume a full mask for that field. Also assume that\n+\t * a VLAN of 0 is unspecified, so mask that out as well. L4type\n+\t * cannot be masked out in this implementation.\n+\t */\n+\tif (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0) {\n+\t\t/* use the L4 protocol mask for raw IPv4/IPv6 traffic */\n+\t\tfdirm |= TXGBE_FDIRMSK_L4P;\n+\t}\n+\n+\t/* TBD: don't support encapsulation yet */\n+\twr32(hw, TXGBE_FDIRMSK, fdirm);\n+\n+\t/* store the TCP/UDP port masks, bit reversed from port layout */\n+\tfdirtcpm = reverse_fdir_bmks(rte_be_to_cpu_16(info->mask.dst_port_mask),\n+\t\t\trte_be_to_cpu_16(info->mask.src_port_mask));\n+\n+\t/* write all the same so that UDP, TCP and SCTP use the same mask\n+\t * (little-endian)\n+\t */\n+\twr32(hw, TXGBE_FDIRTCPMSK, ~fdirtcpm);\n+\twr32(hw, TXGBE_FDIRUDPMSK, ~fdirtcpm);\n+\twr32(hw, TXGBE_FDIRSCTPMSK, ~fdirtcpm);\n+\n+\t/* Store source and destination IPv4 masks (big-endian) */\n+\twr32(hw, TXGBE_FDIRSIP4MSK, ~info->mask.src_ipv4_mask);\n+\twr32(hw, TXGBE_FDIRDIP4MSK, ~info->mask.dst_ipv4_mask);\n+\n+\tif (mode == RTE_FDIR_MODE_SIGNATURE) {\n+\t\t/*\n+\t\t * Store source and destination IPv6 masks (bit reversed)\n+\t\t */\n+\t\tfdiripv6m = TXGBE_FDIRIP6MSK_DST(info->mask.dst_ipv6_mask) |\n+\t\t\t TXGBE_FDIRIP6MSK_SRC(info->mask.src_ipv6_mask);\n+\n+\t\twr32(hw, TXGBE_FDIRIP6MSK, ~fdiripv6m);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_fdir_store_input_mask(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_fdir_masks *input_mask =\n+\t\t\t\t&dev->data->dev_conf.fdir_conf.mask;\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n+\tstruct txgbe_hw_fdir_info *info = TXGBE_DEV_FDIR(dev);\n+\tuint16_t dst_ipv6m = 0;\n+\tuint16_t src_ipv6m = 0;\n+\n+\tif (mode != RTE_FDIR_MODE_SIGNATURE &&\n+\t mode != RTE_FDIR_MODE_PERFECT) {\n+\t\tPMD_DRV_LOG(ERR, \"Not supported fdir mode - %d!\", mode);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tmemset(&info->mask, 0, sizeof(struct txgbe_hw_fdir_mask));\n+\tinfo->mask.vlan_tci_mask = input_mask->vlan_tci_mask;\n+\tinfo->mask.src_port_mask = input_mask->src_port_mask;\n+\tinfo->mask.dst_port_mask = input_mask->dst_port_mask;\n+\tinfo->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;\n+\tinfo->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;\n+\tIPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);\n+\tIPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);\n+\tinfo->mask.src_ipv6_mask = src_ipv6m;\n+\tinfo->mask.dst_ipv6_mask = dst_ipv6m;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * txgbe_check_fdir_flex_conf -check if the flex payload and mask configuration\n+ * arguments are valid\n+ */\n+static int\n+txgbe_set_fdir_flex_conf(struct rte_eth_dev *dev, uint32_t flex)\n+{\n+\tconst struct rte_eth_fdir_flex_conf *conf =\n+\t\t\t\t&dev->data->dev_conf.fdir_conf.flex_conf;\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_hw_fdir_info *info = TXGBE_DEV_FDIR(dev);\n+\tconst struct rte_eth_flex_payload_cfg *flex_cfg;\n+\tconst struct rte_eth_fdir_flex_mask *flex_mask;\n+\tuint16_t flexbytes = 0;\n+\tuint16_t i;\n+\n+\tif (conf == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"NULL pointer.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tflex |= TXGBE_FDIRFLEXCFG_DIA;\n+\n+\tfor (i = 0; i < conf->nb_payloads; i++) {\n+\t\tflex_cfg = &conf->flex_set[i];\n+\t\tif (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {\n+\t\t\tPMD_DRV_LOG(ERR, \"unsupported payload type.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (((flex_cfg->src_offset[0] & 0x1) == 0) &&\n+\t\t (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&\n+\t\t flex_cfg->src_offset[0] <= TXGBE_MAX_FLX_SOURCE_OFF) {\n+\t\t\tflex &= ~TXGBE_FDIRFLEXCFG_OFST_MASK;\n+\t\t\tflex |=\n+\t\t\t TXGBE_FDIRFLEXCFG_OFST(flex_cfg->src_offset[0] / 2);\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR, \"invalid flexbytes arguments.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n+\t\tflex_mask = &conf->flex_mask[i];\n+\t\tif (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {\n+\t\t\tPMD_DRV_LOG(ERR, \"flexmask should be set globally.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tflexbytes = (uint16_t)(((flex_mask->mask[1] << 8) & 0xFF00) |\n+\t\t\t\t\t((flex_mask->mask[0]) & 0xFF));\n+\t\tif (flexbytes == UINT16_MAX) {\n+\t\t\tflex &= ~TXGBE_FDIRFLEXCFG_DIA;\n+\t\t} else if (flexbytes != 0) {\n+\t\t /* TXGBE_FDIRFLEXCFG_DIA is set by default when set mask */\n+\t\t\tPMD_DRV_LOG(ERR, \" invalid flexbytes mask arguments.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tinfo->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;\n+\tinfo->flex_bytes_offset = (uint8_t)(TXGBD_FDIRFLEXCFG_OFST(flex) * 2);\n+\n+\tfor (i = 0; i < 64; i++) {\n+\t\tuint32_t flexreg;\n+\t\tflexreg = rd32(hw, TXGBE_FDIRFLEXCFG(i / 4));\n+\t\tflexreg &= ~(TXGBE_FDIRFLEXCFG_ALL(~0UL, i % 4));\n+\t\tflexreg |= TXGBE_FDIRFLEXCFG_ALL(flex, i % 4);\n+\t\twr32(hw, TXGBE_FDIRFLEXCFG(i / 4), flexreg);\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+txgbe_fdir_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tint err;\n+\tuint32_t fdirctrl, flex, pbsize;\n+\tint i;\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* supports mac-vlan and tunnel mode */\n+\tif (mode != RTE_FDIR_MODE_SIGNATURE &&\n+\t mode != RTE_FDIR_MODE_PERFECT)\n+\t\treturn -ENOSYS;\n+\n+\terr = configure_fdir_flags(&dev->data->dev_conf.fdir_conf,\n+\t\t\t\t &fdirctrl, &flex);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/*\n+\t * Before enabling Flow Director, the Rx Packet Buffer size\n+\t * must be reduced. The new value is the current size minus\n+\t * flow director memory usage size.\n+\t */\n+\tpbsize = rd32(hw, TXGBE_PBRXSIZE(0));\n+\tpbsize -= TXGBD_FDIRCTL_BUF_BYTE(fdirctrl);\n+\twr32(hw, TXGBE_PBRXSIZE(0), pbsize);\n+\n+\t/*\n+\t * The defaults in the HW for RX PB 1-7 are not zero and so should be\n+\t * initialized to zero for non DCB mode otherwise actual total RX PB\n+\t * would be bigger than programmed and filter space would run into\n+\t * the PB 0 region.\n+\t */\n+\tfor (i = 1; i < 8; i++)\n+\t\twr32(hw, TXGBE_PBRXSIZE(i), 0);\n+\n+\terr = txgbe_fdir_store_input_mask(dev);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \" Error on setting FD mask\");\n+\t\treturn err;\n+\t}\n+\n+\terr = txgbe_fdir_set_input_mask(dev);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \" Error on setting FD mask\");\n+\t\treturn err;\n+\t}\n+\n+\terr = txgbe_set_fdir_flex_conf(dev, flex);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \" Error on setting FD flexible arguments.\");\n+\t\treturn err;\n+\t}\n+\n+\terr = txgbe_fdir_enable(hw, fdirctrl);\n+\tif (err < 0) {\n+\t\tPMD_INIT_LOG(ERR, \" Error on enabling FD.\");\n+\t\treturn err;\n+\t}\n+\treturn 0;\n+}\n+\n", "prefixes": [ "v2", "14/37" ] }