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GET /api/patches/83907/?format=api
{ "id": 83907, "url": "http://patches.dpdk.org/api/patches/83907/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1605024259-18318-1-git-send-email-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1605024259-18318-1-git-send-email-viacheslavo@nvidia.com", "date": "2020-11-10T16:04:16", "name": "[1/4] common/mlx5: share UAR allocation routine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "39377653508dce4897e03056341f1bc50b691e3d", "submitter": { "id": 1926, "url": "http://patches.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1605024259-18318-1-git-send-email-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 13779, "url": "http://patches.dpdk.org/api/series/13779/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13779", "date": "2020-11-10T16:04:17", "name": "[1/4] common/mlx5: share UAR allocation routine", "version": 1, "mbox": "http://patches.dpdk.org/series/13779/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/83907/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/83907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BB838A04DD;\n\tTue, 10 Nov 2020 17:04:51 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EF2DD5937;\n\tTue, 10 Nov 2020 17:04:31 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 6607FF90\n for <dev@dpdk.org>; Tue, 10 Nov 2020 17:04:27 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@nvidia.com) with SMTP; 10 Nov 2020 18:04:22 +0200", "from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0AAG4L93012156;\n Tue, 10 Nov 2020 18:04:21 +0200" ], "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "dev@dpdk.org", "Cc": "rasland@nvidia.com, matan@nvidia.com, stable@dpdk.org", "Date": "Tue, 10 Nov 2020 16:04:16 +0000", "Message-Id": "<1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH 1/4] common/mlx5: share UAR allocation routine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch introduces the routine to allocate the UAR (User\nAccess Region) with various memory mapping types. The origin\npatch being fixed provided the UAR allocation workaround\nfor the mlx5 net PMD only. As it was found the other mlx5\nbased drivers - vdpa and regex are affected by the issue\nas well and must be fixed.\n\nFixes: a0bfe9d56f74 (\"net/mlx5: fix UAR memory mapping type\")\nCc: stable@dpdk.org\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common.c | 98 ++++++++++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common.h | 2 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 8 +++\n drivers/common/mlx5/version.map | 1 +\n drivers/net/mlx5/mlx5_defs.h | 9 ----\n 5 files changed, 109 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c\nindex 06f0a64..d2bdf29 100644\n--- a/drivers/common/mlx5/mlx5_common.c\n+++ b/drivers/common/mlx5/mlx5_common.c\n@@ -244,3 +244,101 @@ static inline void mlx5_cpu_id(unsigned int level,\n \t}\n \treturn ret;\n }\n+\n+/**\n+ * Allocate the User Access Region with DevX on specified device.\n+ *\n+ * @param [in] ctx\n+ * Infiniband device context to perform allocation on.\n+ * @param [in] mapping\n+ * MLX5DV_UAR_ALLOC_TYPE_BF - allocate as cached memory with write-combining\n+ *\t\t\t\tattributes (if supported by the host), the\n+ *\t\t\t\twrites to the UAR registers must be followed\n+ *\t\t\t\tby write memory barrier.\n+ * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are\n+ *\t\t\t\tpromoted to the registers immediately, no\n+ *\t\t\t\tmemory barriers needed.\n+ * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF,\n+ *\t\t if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC\n+ *\t\t is performed. The drivers specifying negative values should\n+ *\t\t always provide the write memory barrier operation after UAR\n+ *\t\t register writings.\n+ * If there is no definitions for the MLX5DV_UAR_ALLOC_TYPE_xx (older rdma\n+ * library headers), the caller can specify 0.\n+ *\n+ * @return\n+ * UAR object pointer on success, NULL otherwise and rte_errno is set.\n+ */\n+void *\n+mlx5_devx_alloc_uar(void *ctx, int mapping)\n+{\n+\tvoid *uar;\n+\tuint32_t retry, uar_mapping;\n+\tvoid *base_addr;\n+\n+\tfor (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {\n+#ifdef MLX5DV_UAR_ALLOC_TYPE_NC\n+\t\t/* Control the mapping type according to the settings. */\n+\t\tuar_mapping = (mapping < 0) ?\n+\t\t\t MLX5DV_UAR_ALLOC_TYPE_NC : mapping;\n+#else\n+\t\t/*\n+\t\t * It seems we have no way to control the memory mapping type\n+\t\t * for the UAR, the default \"Write-Combining\" type is supposed.\n+\t\t */\n+\t\tuar_mapping = 0;\n+#endif\n+\t\tuar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);\n+#ifdef MLX5DV_UAR_ALLOC_TYPE_NC\n+\t\tif (!uar &&\n+\t\t mapping < 0 &&\n+\t\t uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {\n+\t\t\t/*\n+\t\t\t * In some environments like virtual machine the\n+\t\t\t * Write Combining mapped might be not supported and\n+\t\t\t * UAR allocation fails. We tried \"Non-Cached\" mapping\n+\t\t\t * for the case.\n+\t\t\t */\n+\t\t\tDRV_LOG(WARNING, \"Failed to allocate DevX UAR (BF)\");\n+\t\t\tuar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;\n+\t\t\tuar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);\n+\t\t} else if (!uar &&\n+\t\t\t mapping < 0 &&\n+\t\t\t uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {\n+\t\t\t/*\n+\t\t\t * If Verbs/kernel does not support \"Non-Cached\"\n+\t\t\t * try the \"Write-Combining\".\n+\t\t\t */\n+\t\t\tDRV_LOG(WARNING, \"Failed to allocate DevX UAR (NC)\");\n+\t\t\tuar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;\n+\t\t\tuar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);\n+\t\t}\n+#endif\n+\t\tif (!uar) {\n+\t\t\tDRV_LOG(ERR, \"Failed to allocate DevX UAR (BF/NC)\");\n+\t\t\trte_errno = ENOMEM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tbase_addr = mlx5_os_get_devx_uar_base_addr(uar);\n+\t\tif (base_addr)\n+\t\t\tbreak;\n+\t\t/*\n+\t\t * The UARs are allocated by rdma_core within the\n+\t\t * IB device context, on context closure all UARs\n+\t\t * will be freed, should be no memory/object leakage.\n+\t\t */\n+\t\tDRV_LOG(WARNING, \"Retrying to allocate DevX UAR\");\n+\t\tuar = NULL;\n+\t}\n+\t/* Check whether we finally succeeded with valid UAR allocation. */\n+\tif (!uar) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate DevX UAR (NULL base)\");\n+\t\trte_errno = ENOMEM;\n+\t}\n+\t/*\n+\t * Return void * instead of struct mlx5dv_devx_uar *\n+\t * is for compatibility with older rdma-core library headers.\n+\t */\n+exit:\n+\treturn uar;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 9d226e5..10a0851 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -261,6 +261,8 @@ int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,\n __rte_internal\n int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,\n \t\t\t uint64_t offset);\n+__rte_internal\n+void *mlx5_devx_alloc_uar(void *ctx, int mapping);\n extern uint8_t haswell_broadwell_cpu;\n \n __rte_internal\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 8d66f1d..726e9f5 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -8,6 +8,14 @@\n #include \"mlx5_glue.h\"\n #include \"mlx5_prm.h\"\n \n+/*\n+ * Defines the amount of retries to allocate the first UAR in the page.\n+ * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as\n+ * UAR base address if UAR was not the first object in the UAR page.\n+ * It caused the PMD failure and we should try to get another UAR\n+ * till we get the first one with non-NULL base address returned.\n+ */\n+#define MLX5_ALLOC_UAR_RETRY 32\n \n /* This is limitation of libibverbs: in length variable type is u16. */\n #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \\\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex af182e6..17dd11f 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -40,6 +40,7 @@ INTERNAL {\n \tmlx5_devx_cmd_query_virtq;\n \tmlx5_devx_cmd_register_read;\n \tmlx5_devx_get_out_command_status;\n+\tmlx5_devx_alloc_uar;\n \n \tmlx5_get_ifname_sysfs;\n \tmlx5_get_dbr;\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex f8f8a1f..aa55db3 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -204,13 +204,4 @@\n #define static_assert _Static_assert\n #endif\n \n-/*\n- * Defines the amount of retries to allocate the first UAR in the page.\n- * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as\n- * UAR base address if UAR was not the first object in the UAR page.\n- * It caused the PMD failure and we should try to get another UAR\n- * till we get the first one with non-NULL base address returned.\n- */\n-#define MLX5_ALLOC_UAR_RETRY 32\n-\n #endif /* RTE_PMD_MLX5_DEFS_H_ */\n", "prefixes": [ "1/4" ] }