Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/8389/?format=api
{ "id": 8389, "url": "http://patches.dpdk.org/api/patches/8389/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446210115-13927-3-git-send-email-zhe.tao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446210115-13927-3-git-send-email-zhe.tao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446210115-13927-3-git-send-email-zhe.tao@intel.com", "date": "2015-10-30T13:01:53", "name": "[dpdk-dev,2/4,v3] add vector PMD TX for FVL", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a7ff981cff38a423540ab5d273917424baab2dc2", "submitter": { "id": 276, "url": "http://patches.dpdk.org/api/people/276/?format=api", "name": "Zhe Tao", "email": "zhe.tao@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446210115-13927-3-git-send-email-zhe.tao@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8389/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8389/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 2A7CA91C8;\n\tFri, 30 Oct 2015 14:02:32 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 327AB918F\n\tfor <dev@dpdk.org>; Fri, 30 Oct 2015 14:02:30 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 30 Oct 2015 06:02:14 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 30 Oct 2015 06:02:14 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9UD2C7U031072;\n\tFri, 30 Oct 2015 21:02:12 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9UD29vr013984; Fri, 30 Oct 2015 21:02:11 +0800", "(from zhetao@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9UD293s013980; \n\tFri, 30 Oct 2015 21:02:09 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,218,1444719600\"; d=\"scan'208\";a=\"675030766\"", "From": "Zhe Tao <zhe.tao@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 30 Oct 2015 21:01:53 +0800", "Message-Id": "<1446210115-13927-3-git-send-email-zhe.tao@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1446210115-13927-1-git-send-email-zhe.tao@intel.com>", "References": "<1446202336-8723-1-git-send-email-zhe.tao@intel.com>\n\t<1446210115-13927-1-git-send-email-zhe.tao@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/4 v3] add vector PMD TX for FVL", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The way to increase the performance of the vPMD TX is to use some fast mbuf \nrelease method compares to the scalar TX.\n\nSigned-off-by: Zhe Tao <zhe.tao@intel.com>\n---\n drivers/net/i40e/i40e_rxtx.c | 8 ++\n drivers/net/i40e/i40e_rxtx.h | 3 +\n drivers/net/i40e/i40e_rxtx_vec.c | 162 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 173 insertions(+)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c\nindex dfdc7d5..8fac220 100644\n--- a/drivers/net/i40e/i40e_rxtx.c\n+++ b/drivers/net/i40e/i40e_rxtx.c\n@@ -3085,3 +3085,11 @@ i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)\n {\n \treturn;\n }\n+\n+uint16_t __attribute__((weak))\n+i40e_xmit_pkts_vec(void __rte_unused *tx_queue,\n+\t\t struct rte_mbuf __rte_unused **tx_pkts,\n+\t\t uint16_t __rte_unused nb_pkts)\n+{\n+\treturn 0;\n+}\ndiff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h\nindex 961a415..6dea402 100644\n--- a/drivers/net/i40e/i40e_rxtx.h\n+++ b/drivers/net/i40e/i40e_rxtx.h\n@@ -232,6 +232,9 @@ int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);\n uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n int i40e_rxq_vec_setup(struct i40e_rx_queue *rxq);\n+int i40e_txq_vec_setup(struct i40e_tx_queue *txq);\n void i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq);\n+uint16_t i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n \n #endif /* _I40E_RXTX_H_ */\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec.c b/drivers/net/i40e/i40e_rxtx_vec.c\nindex a95916b..ba7987d 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec.c\n@@ -447,6 +447,162 @@ i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);\n }\n \n+static inline void\n+vtx1(volatile struct i40e_tx_desc *txdp,\n+\t\tstruct rte_mbuf *pkt, uint64_t flags)\n+{\n+\tuint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |\n+\t\t\t((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |\n+\t\t\t((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));\n+\n+\t__m128i descriptor = _mm_set_epi64x(high_qw,\n+\t\t\t\tpkt->buf_physaddr + pkt->data_off);\n+\t_mm_store_si128((__m128i *)txdp, descriptor);\n+}\n+\n+static inline void\n+vtx(volatile struct i40e_tx_desc *txdp,\n+\t\tstruct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)\n+\t\tvtx1(txdp, *pkt, flags);\n+}\n+\n+static inline int __attribute__((always_inline))\n+i40e_tx_free_bufs(struct i40e_tx_queue *txq)\n+{\n+\tstruct i40e_tx_entry *txep;\n+\tuint32_t n;\n+\tuint32_t i;\n+\tint nb_free = 0;\n+\tstruct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];\n+\t/* check DD bits on threshold descriptor */\n+\tif ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &\n+\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n+\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n+\t\treturn 0;\n+\n+\tn = txq->tx_rs_thresh;\n+\n+\t /* first buffer to free from S/W ring is at index\n+\t * tx_next_dd - (tx_rs_thresh-1)\n+\t */\n+\ttxep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];\n+\tm = __rte_pktmbuf_prefree_seg(txep[0].mbuf);\n+\tif (likely(m != NULL)) {\n+\t\tfree[0] = m;\n+\t\tnb_free = 1;\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (likely(m != NULL)) {\n+\t\t\t\tif (likely(m->pool == free[0]->pool)) {\n+\t\t\t\t\tfree[nb_free++] = m;\n+\t\t\t\t} else {\n+\t\t\t\t\trte_mempool_put_bulk(free[0]->pool,\n+\t\t\t\t\t\t\t (void *)free,\n+\t\t\t\t\t\t\t nb_free);\n+\t\t\t\t\tfree[0] = m;\n+\t\t\t\t\tnb_free = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\trte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);\n+\t} else {\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (m != NULL)\n+\t\t\t\trte_mempool_put(m->pool, m);\n+\t\t}\n+\t}\n+\n+\t/* buffers were freed, update counters */\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n+\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n+\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n+\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\treturn txq->tx_rs_thresh;\n+}\n+\n+static inline void __attribute__((always_inline))\n+tx_backlog_entry(struct i40e_tx_entry *txep,\n+\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < (int)nb_pkts; ++i)\n+\t\ttxep[i].mbuf = tx_pkts[i];\n+}\n+\n+uint16_t\n+i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;\n+\tvolatile struct i40e_tx_desc *txdp;\n+\tstruct i40e_tx_entry *txep;\n+\tuint16_t n, nb_commit, tx_id;\n+\tuint64_t flags = I40E_TD_CMD;\n+\tuint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;\n+\tint i;\n+\n+\t/* cross rx_thresh boundary is not allowed */\n+\tnb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\n+\tif (txq->nb_tx_free < txq->tx_free_thresh)\n+\t\ti40e_tx_free_bufs(txq);\n+\n+\tnb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n+\tif (unlikely(nb_pkts == 0))\n+\t\treturn 0;\n+\n+\ttx_id = txq->tx_tail;\n+\ttxdp = &txq->tx_ring[tx_id];\n+\ttxep = &txq->sw_ring[tx_id];\n+\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n+\n+\tn = (uint16_t)(txq->nb_tx_desc - tx_id);\n+\tif (nb_commit >= n) {\n+\t\ttx_backlog_entry(txep, tx_pkts, n);\n+\n+\t\tfor (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)\n+\t\t\tvtx1(txdp, *tx_pkts, flags);\n+\n+\t\tvtx1(txdp, *tx_pkts++, rs);\n+\n+\t\tnb_commit = (uint16_t)(nb_commit - n);\n+\n+\t\ttx_id = 0;\n+\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\t\t/* avoid reach the end of ring */\n+\t\ttxdp = &txq->tx_ring[tx_id];\n+\t\ttxep = &txq->sw_ring[tx_id];\n+\t}\n+\n+\ttx_backlog_entry(txep, tx_pkts, nb_commit);\n+\n+\tvtx(txdp, tx_pkts, nb_commit, flags);\n+\n+\ttx_id = (uint16_t)(tx_id + nb_commit);\n+\tif (tx_id > txq->tx_next_rs) {\n+\t\ttxq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=\n+\t\t\trte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<\n+\t\t\t\t\t\tI40E_TXD_QW1_CMD_SHIFT);\n+\t\ttxq->tx_next_rs =\n+\t\t\t(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);\n+\t}\n+\n+\ttxq->tx_tail = tx_id;\n+\n+\tI40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n+\n+\treturn nb_pkts;\n+}\n+\n void __attribute__((cold))\n i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)\n {\n@@ -482,3 +638,9 @@ i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)\n \trxq->mbuf_initializer = *(uint64_t *)p;\n \treturn 0;\n }\n+\n+int __attribute__((cold))\n+i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)\n+{\n+\treturn 0;\n+}\n", "prefixes": [ "dpdk-dev", "2/4", "v3" ] }