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GET /api/patches/83874/?format=api
{ "id": 83874, "url": "http://patches.dpdk.org/api/patches/83874/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201110054257.80765-1-chenxux.di@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201110054257.80765-1-chenxux.di@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201110054257.80765-1-chenxux.di@intel.com", "date": "2020-11-10T05:42:57", "name": "[v3] net/i40e: fix incorrect FDIR flex configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "232a6fcdb7bb26eaa420a1f530044556cfe2d7ba", "submitter": { "id": 1409, "url": "http://patches.dpdk.org/api/people/1409/?format=api", "name": "Chenxu Di", "email": "chenxux.di@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201110054257.80765-1-chenxux.di@intel.com/mbox/", "series": [ { "id": 13764, "url": "http://patches.dpdk.org/api/series/13764/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13764", "date": "2020-11-10T05:42:57", "name": "[v3] net/i40e: fix incorrect FDIR flex configuration", "version": 3, "mbox": "http://patches.dpdk.org/series/13764/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/83874/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/83874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 99FD0A052A;\n\tTue, 10 Nov 2020 06:57:43 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6C0EABC5E;\n\tTue, 10 Nov 2020 06:57:42 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 7E0F5BB94;\n Tue, 10 Nov 2020 06:57:39 +0100 (CET)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Nov 2020 21:57:35 -0800", "from dpdk-server06.sh.intel.com ([10.239.255.61])\n by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Nov 2020 21:57:28 -0800" ], "IronPort-SDR": [ "\n goJQiz5Rjt1iTzNr0G0G4SZfa1pcVHz5MI9vV+xxWyYsfj1FR9M//eoKJVZHSc/Zb7IwnE/uDM\n gcaawQ273Hsw==", "\n yR2xLVHHHZWR9FZitdqsGmt8UoShA5h+FONOwL1B966om1ifqnUFzsEBDboTaZuJ2tGE8h0kgD\n ygls2XCPVnZg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9800\"; a=\"166413633\"", "E=Sophos;i=\"5.77,465,1596524400\"; d=\"scan'208\";a=\"166413633\"", "E=Sophos;i=\"5.77,465,1596524400\"; d=\"scan'208\";a=\"473299555\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "From": "Chenxu Di <chenxux.di@intel.com>", "To": "dev@dpdk.org", "Cc": "beilei.xing@intel.com, jia.guo@intel.com, haiyue.wang@intel.com,\n junx.w.zhou@intel.com, Chenxu Di <chenxux.di@intel.com>, stable@dpdk.org", "Date": "Tue, 10 Nov 2020 05:42:57 +0000", "Message-Id": "<20201110054257.80765-1-chenxux.di@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201104082959.63800-1-chenxux.di@intel.com>", "References": "<20201104082959.63800-1-chenxux.di@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] net/i40e: fix incorrect FDIR flex\n\tconfiguration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The configuration of FDIR flex mask and flex pit should not be set\nduring flow validate. It should be set when flow create.\n\nFixes: 6ced3dd72f5f (\"net/i40e: support flexible payload parsing for FDIR\")\nCc: stable@dpdk.org\n\nSigned-off-by: Chenxu Di <chenxux.di@intel.com>\nTested-by: Zhou, Jun <junx.w.zhou@intel.com>\n---\nv3:\n-rebased the patch, fixed the crismas tree\n---\n drivers/net/i40e/i40e_ethdev.h | 22 ++--\n drivers/net/i40e/i40e_fdir.c | 200 ++++++++++++++++++++++++++++++++-\n drivers/net/i40e/i40e_flow.c | 195 ++------------------------------\n 3 files changed, 219 insertions(+), 198 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 1466998aa..98433e86b 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -599,11 +599,22 @@ enum i40e_fdir_ip_type {\n \tI40E_FDIR_IPTYPE_IPV6,\n };\n \n+/**\n+ * Structure to store flex pit for flow diretor.\n+ */\n+struct i40e_fdir_flex_pit {\n+\tuint8_t src_offset; /* offset in words from the beginning of payload */\n+\tuint8_t size; /* size in words */\n+\tuint8_t dst_offset; /* offset in words of flexible payload */\n+};\n+\n /* A structure used to contain extend input of flow */\n struct i40e_fdir_flow_ext {\n \tuint16_t vlan_tci;\n \tuint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];\n \t/* It is filled by the flexible payload to match. */\n+\tuint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];\n+\tuint8_t raw_id;\n \tuint8_t is_vf; /* 1 for VF, 0 for port dev */\n \tuint16_t dst_id; /* VF ID, available when is_vf is 1*/\n \tbool inner_ip; /* If there is inner ip */\n@@ -612,6 +623,8 @@ struct i40e_fdir_flow_ext {\n \tbool customized_pctype; /* If customized pctype is used */\n \tbool pkt_template; /* If raw packet template is used */\n \tbool is_udp; /* ipv4|ipv6 udp flow */\n+\tenum i40e_flxpld_layer_idx layer_idx;\n+\tstruct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];\n };\n \n /* A structure used to define the input for a flow director filter entry */\n@@ -663,15 +676,6 @@ struct i40e_fdir_filter_conf {\n \tstruct i40e_fdir_action action; /* Action taken when match */\n };\n \n-/*\n- * Structure to store flex pit for flow diretor.\n- */\n-struct i40e_fdir_flex_pit {\n-\tuint8_t src_offset; /* offset in words from the beginning of payload */\n-\tuint8_t size; /* size in words */\n-\tuint8_t dst_offset; /* offset in words of flexible payload */\n-};\n-\n struct i40e_fdir_flex_mask {\n \tuint8_t word_mask; /**< Bit i enables word i of flexible payload */\n \tuint8_t nb_bitmask;\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex aa8e72949..d2f88ce34 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -1765,6 +1765,153 @@ i40e_add_del_fdir_filter(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+static int\n+i40e_flow_store_flex_pit(struct i40e_pf *pf,\n+\t\t\t struct i40e_fdir_flex_pit *flex_pit,\n+\t\t\t enum i40e_flxpld_layer_idx layer_idx,\n+\t\t\t uint8_t raw_id)\n+{\n+\tuint8_t field_idx;\n+\n+\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;\n+\t/* Check if the configuration is conflicted */\n+\tif (pf->fdir.flex_pit_flag[layer_idx] &&\n+\t (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||\n+\t pf->fdir.flex_set[field_idx].size != flex_pit->size ||\n+\t pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))\n+\t\treturn -1;\n+\n+\t/* Check if the configuration exists. */\n+\tif (pf->fdir.flex_pit_flag[layer_idx] &&\n+\t (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&\n+\t pf->fdir.flex_set[field_idx].size == flex_pit->size &&\n+\t pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))\n+\t\treturn 1;\n+\n+\tpf->fdir.flex_set[field_idx].src_offset =\n+\t\tflex_pit->src_offset;\n+\tpf->fdir.flex_set[field_idx].size =\n+\t\tflex_pit->size;\n+\tpf->fdir.flex_set[field_idx].dst_offset =\n+\t\tflex_pit->dst_offset;\n+\n+\treturn 0;\n+}\n+\n+static void\n+i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,\n+\t\t\t enum i40e_flxpld_layer_idx layer_idx,\n+\t\t\t uint8_t raw_id)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint32_t flx_pit, flx_ort;\n+\tuint16_t min_next_off = 0;\n+\tuint8_t field_idx;\n+\tuint8_t i;\n+\n+\tif (raw_id) {\n+\t\tflx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |\n+\t\t\t (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n+\t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n+\t\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n+\t}\n+\n+\t/* Set flex pit */\n+\tfor (i = 0; i < raw_id; i++) {\n+\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n+\t\tflx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,\n+\t\t\t\t pf->fdir.flex_set[field_idx].size,\n+\t\t\t\t pf->fdir.flex_set[field_idx].dst_offset);\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n+\t\tmin_next_off = pf->fdir.flex_set[field_idx].src_offset +\n+\t\t\tpf->fdir.flex_set[field_idx].size;\n+\t}\n+\n+\tfor (; i < I40E_MAX_FLXPLD_FIED; i++) {\n+\t\t/* set the non-used register obeying register's constrain */\n+\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n+\t\tflx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,\n+\t\t\t\t NONUSE_FLX_PIT_DEST_OFF);\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n+\t\tmin_next_off++;\n+\t}\n+\n+\tpf->fdir.flex_pit_flag[layer_idx] = 1;\n+}\n+\n+static int\n+i40e_flow_store_flex_mask(struct i40e_pf *pf,\n+\t\t\t enum i40e_filter_pctype pctype,\n+\t\t\t uint8_t *mask)\n+{\n+\tstruct i40e_fdir_flex_mask flex_mask;\n+\tuint8_t nb_bitmask = 0;\n+\tuint16_t mask_tmp;\n+\tuint8_t i;\n+\n+\tmemset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));\n+\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {\n+\t\tmask_tmp = I40E_WORD(mask[i], mask[i + 1]);\n+\t\tif (mask_tmp) {\n+\t\t\tflex_mask.word_mask |=\n+\t\t\t\tI40E_FLEX_WORD_MASK(i / sizeof(uint16_t));\n+\t\t\tif (mask_tmp != UINT16_MAX) {\n+\t\t\t\tflex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;\n+\t\t\t\tflex_mask.bitmask[nb_bitmask].offset =\n+\t\t\t\t\ti / sizeof(uint16_t);\n+\t\t\t\tnb_bitmask++;\n+\t\t\t\tif (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)\n+\t\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tflex_mask.nb_bitmask = nb_bitmask;\n+\n+\tif (pf->fdir.flex_mask_flag[pctype] &&\n+\t (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],\n+\t\t sizeof(struct i40e_fdir_flex_mask))))\n+\t\treturn -2;\n+\telse if (pf->fdir.flex_mask_flag[pctype] &&\n+\t\t !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],\n+\t\t\t sizeof(struct i40e_fdir_flex_mask))))\n+\t\treturn 1;\n+\n+\tmemcpy(&pf->fdir.flex_mask[pctype], &flex_mask,\n+\t sizeof(struct i40e_fdir_flex_mask));\n+\treturn 0;\n+}\n+\n+static void\n+i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,\n+\t\t\t enum i40e_filter_pctype pctype)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tstruct i40e_fdir_flex_mask *flex_mask;\n+\tuint32_t flxinset, fd_mask;\n+\tuint8_t i;\n+\n+\t/* Set flex mask */\n+\tflex_mask = &pf->fdir.flex_mask[pctype];\n+\tflxinset = (flex_mask->word_mask <<\n+\t\t I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &\n+\t\tI40E_PRTQF_FD_FLXINSET_INSET_MASK;\n+\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n+\n+\tfor (i = 0; i < flex_mask->nb_bitmask; i++) {\n+\t\tfd_mask = (flex_mask->bitmask[i].mask <<\n+\t\t\t I40E_PRTQF_FD_MSK_MASK_SHIFT) &\n+\t\t\t I40E_PRTQF_FD_MSK_MASK_MASK;\n+\t\tfd_mask |= ((flex_mask->bitmask[i].offset +\n+\t\t\t I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n+\t\t\t I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &\n+\t\t\t\tI40E_PRTQF_FD_MSK_OFFSET_MASK;\n+\t\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n+\t}\n+\n+\tpf->fdir.flex_mask_flag[pctype] = 1;\n+}\n+\n static inline unsigned char *\n i40e_find_available_buffer(struct rte_eth_dev *dev)\n {\n@@ -1817,13 +1964,19 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,\n {\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tunsigned char *pkt = NULL;\n-\tenum i40e_filter_pctype pctype;\n+\tenum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;\n \tstruct i40e_fdir_info *fdir_info = &pf->fdir;\n-\tstruct i40e_fdir_filter *node;\n+\tuint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];\n \tstruct i40e_fdir_filter check_filter; /* Check if the filter exists */\n+\tstruct i40e_fdir_flex_pit flex_pit;\n+\tenum i40e_filter_pctype pctype;\n+\tstruct i40e_fdir_filter *node;\n+\tunsigned char *pkt = NULL;\n+\tbool cfg_flex_pit = true;\n \tbool wait_status = true;\n+\tuint8_t field_idx;\n \tint ret = 0;\n+\tint i;\n \n \tif (pf->fdir.fdir_vsi == NULL) {\n \t\tPMD_DRV_LOG(ERR, \"FDIR is not enabled\");\n@@ -1856,6 +2009,47 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,\n \ti40e_fdir_filter_convert(filter, &check_filter);\n \n \tif (add) {\n+\t\tif (!filter->input.flow_ext.customized_pctype) {\n+\t\t\tfor (i = 0; i < filter->input.flow_ext.raw_id; i++) {\n+\t\t\t\tlayer_idx = filter->input.flow_ext.layer_idx;\n+\t\t\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n+\t\t\t\tflex_pit = filter->input.flow_ext.flex_pit[field_idx];\n+\n+\t\t\t\t/* Store flex pit to SW */\n+\t\t\t\tret = i40e_flow_store_flex_pit(pf, &flex_pit,\n+\t\t\t\t\t\t\t layer_idx, i);\n+\t\t\t\tif (ret < 0) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"Conflict with the\"\n+\t\t\t\t\t\t \" first flexible rule.\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t} else if (ret > 0) {\n+\t\t\t\t\tcfg_flex_pit = false;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (cfg_flex_pit)\n+\t\t\t\ti40e_flow_set_fdir_flex_pit(pf, layer_idx,\n+\t\t\t\t\t\tfilter->input.flow_ext.raw_id);\n+\n+\t\t\t/* Store flex mask to SW */\n+\t\t\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++)\n+\t\t\t\tflex_mask[i] =\n+\t\t\t\t\tfilter->input.flow_ext.flex_mask[i];\n+\n+\t\t\tret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);\n+\t\t\tif (ret == -1) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Exceed maximal\"\n+\t\t\t\t\t \" number of bitmasks\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else if (ret == -2) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Conflict with the\"\n+\t\t\t\t\t \" first flexible rule\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else if (ret == 0) {\n+\t\t\t\ti40e_flow_set_fdir_flex_msk(pf, pctype);\n+\t\t\t}\n+\t\t}\n+\n \t\tret = i40e_sw_fdir_filter_insert(pf, &check_filter);\n \t\tif (ret < 0) {\n \t\t\tPMD_DRV_LOG(ERR,\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex adc5da1c5..098ae13ab 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -2240,152 +2240,6 @@ i40e_flow_check_raw_item(const struct rte_flow_item *item,\n \treturn 0;\n }\n \n-static int\n-i40e_flow_store_flex_pit(struct i40e_pf *pf,\n-\t\t\t struct i40e_fdir_flex_pit *flex_pit,\n-\t\t\t enum i40e_flxpld_layer_idx layer_idx,\n-\t\t\t uint8_t raw_id)\n-{\n-\tuint8_t field_idx;\n-\n-\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;\n-\t/* Check if the configuration is conflicted */\n-\tif (pf->fdir.flex_pit_flag[layer_idx] &&\n-\t (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||\n-\t pf->fdir.flex_set[field_idx].size != flex_pit->size ||\n-\t pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))\n-\t\treturn -1;\n-\n-\t/* Check if the configuration exists. */\n-\tif (pf->fdir.flex_pit_flag[layer_idx] &&\n-\t (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&\n-\t pf->fdir.flex_set[field_idx].size == flex_pit->size &&\n-\t pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))\n-\t\treturn 1;\n-\n-\tpf->fdir.flex_set[field_idx].src_offset =\n-\t\tflex_pit->src_offset;\n-\tpf->fdir.flex_set[field_idx].size =\n-\t\tflex_pit->size;\n-\tpf->fdir.flex_set[field_idx].dst_offset =\n-\t\tflex_pit->dst_offset;\n-\n-\treturn 0;\n-}\n-\n-static int\n-i40e_flow_store_flex_mask(struct i40e_pf *pf,\n-\t\t\t enum i40e_filter_pctype pctype,\n-\t\t\t uint8_t *mask)\n-{\n-\tstruct i40e_fdir_flex_mask flex_mask;\n-\tuint16_t mask_tmp;\n-\tuint8_t i, nb_bitmask = 0;\n-\n-\tmemset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));\n-\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {\n-\t\tmask_tmp = I40E_WORD(mask[i], mask[i + 1]);\n-\t\tif (mask_tmp) {\n-\t\t\tflex_mask.word_mask |=\n-\t\t\t\tI40E_FLEX_WORD_MASK(i / sizeof(uint16_t));\n-\t\t\tif (mask_tmp != UINT16_MAX) {\n-\t\t\t\tflex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;\n-\t\t\t\tflex_mask.bitmask[nb_bitmask].offset =\n-\t\t\t\t\ti / sizeof(uint16_t);\n-\t\t\t\tnb_bitmask++;\n-\t\t\t\tif (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)\n-\t\t\t\t\treturn -1;\n-\t\t\t}\n-\t\t}\n-\t}\n-\tflex_mask.nb_bitmask = nb_bitmask;\n-\n-\tif (pf->fdir.flex_mask_flag[pctype] &&\n-\t (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],\n-\t\t sizeof(struct i40e_fdir_flex_mask))))\n-\t\treturn -2;\n-\telse if (pf->fdir.flex_mask_flag[pctype] &&\n-\t\t !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],\n-\t\t\t sizeof(struct i40e_fdir_flex_mask))))\n-\t\treturn 1;\n-\n-\tmemcpy(&pf->fdir.flex_mask[pctype], &flex_mask,\n-\t sizeof(struct i40e_fdir_flex_mask));\n-\treturn 0;\n-}\n-\n-static void\n-i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,\n-\t\t\t enum i40e_flxpld_layer_idx layer_idx,\n-\t\t\t uint8_t raw_id)\n-{\n-\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n-\tuint32_t flx_pit, flx_ort;\n-\tuint8_t field_idx;\n-\tuint16_t min_next_off = 0; /* in words */\n-\tuint8_t i;\n-\n-\tif (raw_id) {\n-\t\tflx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |\n-\t\t\t (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |\n-\t\t\t (layer_idx * I40E_MAX_FLXPLD_FIED);\n-\t\tI40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);\n-\t}\n-\n-\t/* Set flex pit */\n-\tfor (i = 0; i < raw_id; i++) {\n-\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n-\t\tflx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,\n-\t\t\t\t pf->fdir.flex_set[field_idx].size,\n-\t\t\t\t pf->fdir.flex_set[field_idx].dst_offset);\n-\n-\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n-\t\tmin_next_off = pf->fdir.flex_set[field_idx].src_offset +\n-\t\t\tpf->fdir.flex_set[field_idx].size;\n-\t}\n-\n-\tfor (; i < I40E_MAX_FLXPLD_FIED; i++) {\n-\t\t/* set the non-used register obeying register's constrain */\n-\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n-\t\tflx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,\n-\t\t\t\t NONUSE_FLX_PIT_DEST_OFF);\n-\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n-\t\tmin_next_off++;\n-\t}\n-\n-\tpf->fdir.flex_pit_flag[layer_idx] = 1;\n-}\n-\n-static void\n-i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,\n-\t\t\t enum i40e_filter_pctype pctype)\n-{\n-\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n-\tstruct i40e_fdir_flex_mask *flex_mask;\n-\tuint32_t flxinset, fd_mask;\n-\tuint8_t i;\n-\n-\t/* Set flex mask */\n-\tflex_mask = &pf->fdir.flex_mask[pctype];\n-\tflxinset = (flex_mask->word_mask <<\n-\t\t I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &\n-\t\tI40E_PRTQF_FD_FLXINSET_INSET_MASK;\n-\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n-\n-\tfor (i = 0; i < flex_mask->nb_bitmask; i++) {\n-\t\tfd_mask = (flex_mask->bitmask[i].mask <<\n-\t\t\t I40E_PRTQF_FD_MSK_MASK_SHIFT) &\n-\t\t\tI40E_PRTQF_FD_MSK_MASK_MASK;\n-\t\tfd_mask |= ((flex_mask->bitmask[i].offset +\n-\t\t\t I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n-\t\t\t I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &\n-\t\t\tI40E_PRTQF_FD_MSK_OFFSET_MASK;\n-\t\ti40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n-\t}\n-\n-\tpf->fdir.flex_mask_flag[pctype] = 1;\n-}\n-\n static int\n i40e_flow_set_fdir_inset(struct i40e_pf *pf,\n \t\t\t enum i40e_filter_pctype pctype,\n@@ -2604,18 +2458,15 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \tuint16_t len_arr[I40E_MAX_FLXPLD_FIED];\n \tstruct i40e_fdir_flex_pit flex_pit;\n \tuint8_t next_dst_off = 0;\n-\tuint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];\n \tuint16_t flex_size;\n-\tbool cfg_flex_pit = true;\n-\tbool cfg_flex_msk = true;\n \tuint16_t ether_type;\n \tuint32_t vtc_flow_cpu;\n \tbool outer_ip = true;\n+\tuint8_t field_idx;\n \tint ret;\n \n \tmemset(off_arr, 0, sizeof(off_arr));\n \tmemset(len_arr, 0, sizeof(len_arr));\n-\tmemset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);\n \tfilter->input.flow_ext.customized_pctype = false;\n \tfor (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n \t\tif (item->last) {\n@@ -3163,6 +3014,7 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \n \t\t\tflex_size = 0;\n \t\t\tmemset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));\n+\t\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;\n \t\t\tflex_pit.size =\n \t\t\t\traw_spec->length / sizeof(uint16_t);\n \t\t\tflex_pit.dst_offset =\n@@ -3189,27 +3041,21 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \t\t\t\treturn -rte_errno;\n \t\t\t}\n \n-\t\t\t/* Store flex pit to SW */\n-\t\t\tret = i40e_flow_store_flex_pit(pf, &flex_pit,\n-\t\t\t\t\t\t layer_idx, raw_id);\n-\t\t\tif (ret < 0) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t item,\n-\t\t\t\t \"Conflict with the first flexible rule.\");\n-\t\t\t\treturn -rte_errno;\n-\t\t\t} else if (ret > 0)\n-\t\t\t\tcfg_flex_pit = false;\n-\n \t\t\tfor (i = 0; i < raw_spec->length; i++) {\n \t\t\t\tj = i + next_dst_off;\n \t\t\t\tfilter->input.flow_ext.flexbytes[j] =\n \t\t\t\t\traw_spec->pattern[i];\n-\t\t\t\tflex_mask[j] = raw_mask->pattern[i];\n+\t\t\t\tfilter->input.flow_ext.flex_mask[j] =\n+\t\t\t\t\traw_mask->pattern[i];\n \t\t\t}\n \n \t\t\tnext_dst_off += raw_spec->length;\n \t\t\traw_id++;\n+\n+\t\t\tmemcpy(&filter->input.flow_ext.flex_pit[field_idx],\n+\t\t\t &flex_pit, sizeof(struct i40e_fdir_flex_pit));\n+\t\t\tfilter->input.flow_ext.layer_idx = layer_idx;\n+\t\t\tfilter->input.flow_ext.raw_id = raw_id;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VF:\n \t\t\tvf_spec = item->spec;\n@@ -3295,29 +3141,6 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \t\t\t\t\t \"Invalid pattern mask.\");\n \t\t\treturn -rte_errno;\n \t\t}\n-\n-\t\t/* Store flex mask to SW */\n-\t\tret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);\n-\t\tif (ret == -1) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t item,\n-\t\t\t\t\t \"Exceed maximal number of bitmasks\");\n-\t\t\treturn -rte_errno;\n-\t\t} else if (ret == -2) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t item,\n-\t\t\t\t\t \"Conflict with the first flexible rule\");\n-\t\t\treturn -rte_errno;\n-\t\t} else if (ret > 0)\n-\t\t\tcfg_flex_msk = false;\n-\n-\t\tif (cfg_flex_pit)\n-\t\t\ti40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);\n-\n-\t\tif (cfg_flex_msk)\n-\t\t\ti40e_flow_set_fdir_flex_msk(pf, pctype);\n \t}\n \n \tfilter->input.pctype = pctype;\n", "prefixes": [ "v3" ] }