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{
    "id": 83853,
    "url": "http://patches.dpdk.org/api/patches/83853/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1604932142-19900-4-git-send-email-oulijun@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1604932142-19900-4-git-send-email-oulijun@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1604932142-19900-4-git-send-email-oulijun@huawei.com",
    "date": "2020-11-09T14:28:59",
    "name": "[V3,3/6] net/hns3: adjust code style for initial struct",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "46e13b4016164434fd839b580ca14bdc03eb471c",
    "submitter": {
        "id": 1675,
        "url": "http://patches.dpdk.org/api/people/1675/?format=api",
        "name": "Lijun Ou",
        "email": "oulijun@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1604932142-19900-4-git-send-email-oulijun@huawei.com/mbox/",
    "series": [
        {
            "id": 13748,
            "url": "http://patches.dpdk.org/api/series/13748/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13748",
            "date": "2020-11-09T14:29:00",
            "name": "bugfix and cleanups for hns3",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/13748/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/83853/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/83853/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 79A68A0527;\n\tMon,  9 Nov 2020 15:29:45 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 29A259B01;\n\tMon,  9 Nov 2020 15:28:54 +0100 (CET)",
            "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by dpdk.org (Postfix) with ESMTP id 2B9AA7CAE\n for <dev@dpdk.org>; Mon,  9 Nov 2020 15:28:50 +0100 (CET)",
            "from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CVCz426VFzkhYp\n for <dev@dpdk.org>; Mon,  9 Nov 2020 22:28:32 +0800 (CST)",
            "from localhost.localdomain (10.69.192.56) by\n DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id\n 14.3.487.0; Mon, 9 Nov 2020 22:28:34 +0800"
        ],
        "From": "Lijun Ou <oulijun@huawei.com>",
        "To": "<ferruh.yigit@intel.com>",
        "CC": "<dev@dpdk.org>, <linuxarm@huawei.com>",
        "Date": "Mon, 9 Nov 2020 22:28:59 +0800",
        "Message-ID": "<1604932142-19900-4-git-send-email-oulijun@huawei.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1604932142-19900-1-git-send-email-oulijun@huawei.com>",
        "References": "<1604634716-43484-1-git-send-email-oulijun@huawei.com>\n <1604932142-19900-1-git-send-email-oulijun@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.69.192.56]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH V3 3/6] net/hns3: adjust code style for initial\n\tstruct",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Hongbo Zheng <zhenghongbo3@huawei.com>\n\nAccording to the rule of the used static check tool,\neach member is initialized on a separate lines when\nstruct and union members are initialized, here is\ntempting to adjust some code lines in order to remove\nthe warning.\n\nSigned-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\nV2->V3:\n- drop the operation of adjusting whitespace changes\n- update commit log\n\nV1->V2:\n- fix checkpatch warning\n---\n drivers/net/hns3/hns3_intr.c | 873 ++++++++++++++++++++++++++++---------------\n 1 file changed, 582 insertions(+), 291 deletions(-)",
    "diff": "diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex bfd2ba8..99c500d 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -28,201 +28,281 @@ static const char *reset_string[HNS3_MAX_RESET] = {\n };\n \n static const struct hns3_hw_error mac_afifo_tnl_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"egu_cge_afifo_ecc_1bit_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"egu_cge_afifo_ecc_1bit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"egu_cge_afifo_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"egu_cge_afifo_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"egu_lge_afifo_ecc_1bit_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"egu_lge_afifo_ecc_1bit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"egu_lge_afifo_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"egu_lge_afifo_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"cge_igu_afifo_ecc_1bit_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"cge_igu_afifo_ecc_1bit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"cge_igu_afifo_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"cge_igu_afifo_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"lge_igu_afifo_ecc_1bit_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"lge_igu_afifo_ecc_1bit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"lge_igu_afifo_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"lge_igu_afifo_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"cge_igu_afifo_overflow_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"cge_igu_afifo_overflow_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"lge_igu_afifo_overflow_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"lge_igu_afifo_overflow_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"egu_cge_afifo_underrun_err\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"egu_cge_afifo_underrun_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"egu_lge_afifo_underrun_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"egu_lge_afifo_underrun_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"egu_ge_afifo_underrun_err\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"egu_ge_afifo_underrun_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"ge_igu_afifo_overflow_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"ge_igu_afifo_overflow_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {\n-\t{ .int_msk = 0xFFFFFFFF, .msg = \"rpu_rx_pkt_ecc_mbit_err\",\n+\t{ .int_msk = 0xFFFFFFFF,\n+\t  .msg = \"rpu_rx_pkt_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = {\n-\t{ .int_msk = BIT(13), .msg = \"rpu_rx_pkt_bit32_ecc_mbit_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"rpu_rx_pkt_bit32_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"rpu_rx_pkt_bit33_ecc_mbit_err\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"rpu_rx_pkt_bit33_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"rpu_rx_pkt_bit34_ecc_mbit_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"rpu_rx_pkt_bit34_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(16), .msg = \"rpu_rx_pkt_bit35_ecc_mbit_err\",\n+\t{ .int_msk = BIT(16),\n+\t  .msg = \"rpu_rx_pkt_bit35_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"rcb_tx_ring_ecc_mbit_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"rcb_tx_ring_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(18), .msg = \"rcb_rx_ring_ecc_mbit_err\",\n+\t{ .int_msk = BIT(18),\n+\t  .msg = \"rcb_rx_ring_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(19), .msg = \"rcb_tx_fbd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(19),\n+\t  .msg = \"rcb_tx_fbd_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(20), .msg = \"rcb_rx_ebd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(20),\n+\t  .msg = \"rcb_rx_ebd_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(21), .msg = \"rcb_tso_info_ecc_mbit_err\",\n+\t{ .int_msk = BIT(21),\n+\t  .msg = \"rcb_tso_info_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(22), .msg = \"rcb_tx_int_info_ecc_mbit_err\",\n+\t{ .int_msk = BIT(22),\n+\t  .msg = \"rcb_tx_int_info_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(23), .msg = \"rcb_rx_int_info_ecc_mbit_err\",\n+\t{ .int_msk = BIT(23),\n+\t  .msg = \"rcb_rx_int_info_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(24), .msg = \"tpu_tx_pkt_0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(24),\n+\t  .msg = \"tpu_tx_pkt_0_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(25), .msg = \"tpu_tx_pkt_1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(25),\n+\t  .msg = \"tpu_tx_pkt_1_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(26), .msg = \"rd_bus_err\",\n+\t{ .int_msk = BIT(26),\n+\t  .msg = \"rd_bus_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(27), .msg = \"wr_bus_err\",\n+\t{ .int_msk = BIT(27),\n+\t  .msg = \"wr_bus_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(30), .msg = \"ooo_ecc_err_detect\",\n+\t{ .int_msk = BIT(30),\n+\t  .msg = \"ooo_ecc_err_detect\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(31), .msg = \"ooo_ecc_err_multpl\",\n+\t{ .int_msk = BIT(31),\n+\t  .msg = \"ooo_ecc_err_multpl\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = {\n-\t{ .int_msk = BIT(29), .msg = \"rx_q_search_miss\",\n+\t{ .int_msk = BIT(29),\n+\t  .msg = \"rx_q_search_miss\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_port_based_pf_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"roc_pkt_without_key_port\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"roc_pkt_without_key_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"low_water_line_err_port\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"low_water_line_err_port\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppp_pf_abnormal_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"tx_vlan_tag_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"tx_vlan_tag_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"rss_list_tc_unassigned_queue_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"rss_list_tc_unassigned_queue_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = {\n-\t{ .int_msk = BIT(3), .msg = \"tx_rd_fbd_poison\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"tx_rd_fbd_poison\",\n \t  .reset_level = HNS3_FUNC_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"rx_rd_ebd_poison\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"rx_rd_ebd_poison\",\n \t  .reset_level = HNS3_FUNC_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = {\n-\t{ .int_msk = BIT(0), .msg = \"over_8bd_no_fe\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"over_8bd_no_fe\",\n \t  .reset_level = HNS3_FUNC_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"tso_mss_cmp_min_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"tso_mss_cmp_min_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"tso_mss_cmp_max_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"tso_mss_cmp_max_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"buf_wait_timeout\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"buf_wait_timeout\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error imp_tcm_ecc_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"imp_itcm0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"imp_itcm0_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"imp_itcm1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"imp_itcm1_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"imp_itcm2_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"imp_itcm2_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"imp_itcm3_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"imp_itcm3_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"imp_dtcm0_mem0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"imp_dtcm0_mem0_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"imp_dtcm0_mem1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"imp_dtcm0_mem1_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"imp_dtcm1_mem0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"imp_dtcm1_mem0_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"imp_dtcm1_mem1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"imp_dtcm1_mem1_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"imp_itcm4_ecc_mbit_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"imp_itcm4_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error cmdq_mem_ecc_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"cmdq_nic_rx_depth_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"cmdq_nic_rx_depth_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"cmdq_nic_tx_depth_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"cmdq_nic_tx_depth_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"cmdq_nic_rx_tail_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"cmdq_nic_rx_tail_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"cmdq_nic_tx_tail_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"cmdq_nic_tx_tail_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"cmdq_nic_rx_head_ecc_mbit_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"cmdq_nic_rx_head_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"cmdq_nic_tx_head_ecc_mbit_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"cmdq_nic_tx_head_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"cmdq_nic_rx_addr_ecc_mbit_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"cmdq_nic_rx_addr_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"cmdq_nic_tx_addr_ecc_mbit_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"cmdq_nic_tx_addr_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error tqp_int_ecc_int[] = {\n-\t{ .int_msk = BIT(6), .msg = \"tqp_int_cfg_even_ecc_mbit_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"tqp_int_cfg_even_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"tqp_int_cfg_odd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"tqp_int_cfg_odd_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"tqp_int_ctrl_even_ecc_mbit_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"tqp_int_ctrl_even_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"tqp_int_ctrl_odd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"tqp_int_ctrl_odd_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"tx_que_scan_int_ecc_mbit_err\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"tx_queue_scan_int_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"rx_que_scan_int_ecc_mbit_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"rx_queue_scan_int_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error imp_rd_poison_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"imp_rd_poison_int\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"imp_rd_poison_int\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n #define HNS3_SSU_MEM_ECC_ERR(x) \\\n-\t{ .int_msk = BIT(x), .msg = \"ssu_mem\" #x \"_ecc_mbit_err\", \\\n+\t{ .int_msk = BIT(x), \\\n+\t  .msg = \"ssu_mem\" #x \"_ecc_mbit_err\", \\\n \t  .reset_level = HNS3_GLOBAL_RESET }\n \n static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {\n@@ -258,515 +338,726 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {\n \tHNS3_SSU_MEM_ECC_ERR(29),\n \tHNS3_SSU_MEM_ECC_ERR(30),\n \tHNS3_SSU_MEM_ECC_ERR(31),\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {\n-\t{ .int_msk = BIT(0), .msg = \"ssu_mem32_ecc_mbit_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"ssu_mem32_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_common_ecc_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"buf_sum_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"buf_sum_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"ppp_mb_num_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"ppp_mb_num_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"ppp_mbid_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"ppp_mbid_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"ppp_rlt_mac_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"ppp_rlt_mac_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"ppp_rlt_host_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"ppp_rlt_host_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"cks_edit_position_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"cks_edit_position_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"cks_edit_condition_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"cks_edit_condition_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"vlan_edit_condition_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"vlan_edit_condition_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"vlan_num_ot_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"vlan_num_ot_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"vlan_num_in_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"vlan_num_in_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error igu_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"igu_rx_buf0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"igu_rx_buf0_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"igu_rx_buf1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"igu_rx_buf1_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error msix_ecc_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"msix_nic_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"msix_nic_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {\n-\t{ .int_msk = BIT(0), .msg = \"vf_vlan_ad_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"vf_vlan_ad_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"umv_mcast_group_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"umv_mcast_group_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"umv_key_mem0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"umv_key_mem0_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"umv_key_mem1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"umv_key_mem1_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"umv_key_mem2_ecc_mbit_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"umv_key_mem2_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"umv_key_mem3_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"umv_key_mem3_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"umv_ad_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"umv_ad_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"rss_tc_mode_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"rss_tc_mode_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"rss_idt_mem0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"rss_idt_mem0_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"rss_idt_mem1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"rss_idt_mem1_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"rss_idt_mem2_ecc_mbit_err\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"rss_idt_mem2_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"rss_idt_mem3_ecc_mbit_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"rss_idt_mem3_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"rss_idt_mem4_ecc_mbit_err\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"rss_idt_mem4_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"rss_idt_mem5_ecc_mbit_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"rss_idt_mem5_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"rss_idt_mem6_ecc_mbit_err\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"rss_idt_mem6_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"rss_idt_mem7_ecc_mbit_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"rss_idt_mem7_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(16), .msg = \"rss_idt_mem8_ecc_mbit_err\",\n+\t{ .int_msk = BIT(16),\n+\t  .msg = \"rss_idt_mem8_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"rss_idt_mem9_ecc_mbit_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"rss_idt_mem9_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(18), .msg = \"rss_idt_mem10_ecc_m1bit_err\",\n+\t{ .int_msk = BIT(18),\n+\t  .msg = \"rss_idt_mem10_ecc_m1bit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(19), .msg = \"rss_idt_mem11_ecc_mbit_err\",\n+\t{ .int_msk = BIT(19),\n+\t  .msg = \"rss_idt_mem11_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(20), .msg = \"rss_idt_mem12_ecc_mbit_err\",\n+\t{ .int_msk = BIT(20),\n+\t  .msg = \"rss_idt_mem12_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(21), .msg = \"rss_idt_mem13_ecc_mbit_err\",\n+\t{ .int_msk = BIT(21),\n+\t  .msg = \"rss_idt_mem13_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(22), .msg = \"rss_idt_mem14_ecc_mbit_err\",\n+\t{ .int_msk = BIT(22),\n+\t  .msg = \"rss_idt_mem14_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(23), .msg = \"rss_idt_mem15_ecc_mbit_err\",\n+\t{ .int_msk = BIT(23),\n+\t  .msg = \"rss_idt_mem15_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(24), .msg = \"port_vlan_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(24),\n+\t  .msg = \"port_vlan_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(25), .msg = \"mcast_linear_table_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(25),\n+\t  .msg = \"mcast_linear_table_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(26), .msg = \"mcast_result_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(26),\n+\t  .msg = \"mcast_result_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(27), .msg = \"flow_director_ad_mem0_ecc_mbit_err\",\n+\t{ .int_msk = BIT(27),\n+\t  .msg = \"flow_director_ad_mem0_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(28), .msg = \"flow_director_ad_mem1_ecc_mbit_err\",\n+\t{ .int_msk = BIT(28),\n+\t  .msg = \"flow_director_ad_mem1_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(29), .msg = \"rx_vlan_tag_memory_ecc_mbit_err\",\n+\t{ .int_msk = BIT(29),\n+\t  .msg = \"rx_vlan_tag_memory_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(30), .msg = \"Tx_UP_mapping_config_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(30),\n+\t  .msg = \"Tx_UP_mapping_config_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {\n-\t{ .int_msk = BIT(0), .msg = \"hfs_fifo_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"hfs_fifo_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"rslt_descr_fifo_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"rslt_descr_fifo_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"tx_vlan_tag_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"tx_vlan_tag_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"FD_CN0_memory_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"FD_CN0_memory_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"FD_CN1_memory_ecc_mbit_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"FD_CN1_memory_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"GRO_AD_memory_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"GRO_AD_memory_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {\n-\t{ .int_msk = BIT(4), .msg = \"gro_bd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"gro_bd_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"gro_context_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"gro_context_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"rx_stash_cfg_ecc_mbit_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"rx_stash_cfg_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"axi_rd_fbd_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"axi_rd_fbd_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error tm_sch_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"tm_sch_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"tm_sch_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"tm_sch_port_shap_sub_fifo_wr_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"tm_sch_port_shap_sub_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"tm_sch_port_shap_sub_fifo_rd_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"tm_sch_port_shap_sub_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"tm_sch_pg_pshap_sub_fifo_wr_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"tm_sch_pg_pshap_sub_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"tm_sch_pg_pshap_sub_fifo_rd_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"tm_sch_pg_pshap_sub_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"tm_sch_pg_cshap_sub_fifo_wr_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"tm_sch_pg_cshap_sub_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"tm_sch_pg_cshap_sub_fifo_rd_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"tm_sch_pg_cshap_sub_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"tm_sch_pri_pshap_sub_fifo_wr_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"tm_sch_pri_pshap_sub_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"tm_sch_pri_pshap_sub_fifo_rd_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"tm_sch_pri_pshap_sub_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"tm_sch_pri_cshap_sub_fifo_wr_err\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"tm_sch_pri_cshap_sub_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"tm_sch_pri_cshap_sub_fifo_rd_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"tm_sch_pri_cshap_sub_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"tm_sch_port_shap_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"tm_sch_port_shap_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"tm_sch_port_shap_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"tm_sch_port_shap_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"tm_sch_pg_pshap_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"tm_sch_pg_pshap_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"tm_sch_pg_pshap_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"tm_sch_pg_pshap_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(16), .msg = \"tm_sch_pg_cshap_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(16),\n+\t  .msg = \"tm_sch_pg_cshap_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"tm_sch_pg_cshap_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"tm_sch_pg_cshap_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(18), .msg = \"tm_sch_pri_pshap_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(18),\n+\t  .msg = \"tm_sch_pri_pshap_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(19), .msg = \"tm_sch_pri_pshap_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(19),\n+\t  .msg = \"tm_sch_pri_pshap_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(20), .msg = \"tm_sch_pri_cshap_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(20),\n+\t  .msg = \"tm_sch_pri_cshap_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(21), .msg = \"tm_sch_pri_cshap_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(21),\n+\t  .msg = \"tm_sch_pri_cshap_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(22), .msg = \"tm_sch_rq_fifo_wr_err\",\n+\t{ .int_msk = BIT(22),\n+\t  .msg = \"tm_sch_rq_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(23), .msg = \"tm_sch_rq_fifo_rd_err\",\n+\t{ .int_msk = BIT(23),\n+\t  .msg = \"tm_sch_rq_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(24), .msg = \"tm_sch_nq_fifo_wr_err\",\n+\t{ .int_msk = BIT(24),\n+\t  .msg = \"tm_sch_nq_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(25), .msg = \"tm_sch_nq_fifo_rd_err\",\n+\t{ .int_msk = BIT(25),\n+\t  .msg = \"tm_sch_nq_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(26), .msg = \"tm_sch_roce_up_fifo_wr_err\",\n+\t{ .int_msk = BIT(26),\n+\t  .msg = \"tm_sch_roce_up_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(27), .msg = \"tm_sch_roce_up_fifo_rd_err\",\n+\t{ .int_msk = BIT(27),\n+\t  .msg = \"tm_sch_roce_up_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(28), .msg = \"tm_sch_rcb_byte_fifo_wr_err\",\n+\t{ .int_msk = BIT(28),\n+\t  .msg = \"tm_sch_rcb_byte_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(29), .msg = \"tm_sch_rcb_byte_fifo_rd_err\",\n+\t{ .int_msk = BIT(29),\n+\t  .msg = \"tm_sch_rcb_byte_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(30), .msg = \"tm_sch_ssu_byte_fifo_wr_err\",\n+\t{ .int_msk = BIT(30),\n+\t  .msg = \"tm_sch_ssu_byte_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(31), .msg = \"tm_sch_ssu_byte_fifo_rd_err\",\n+\t{ .int_msk = BIT(31),\n+\t  .msg = \"tm_sch_ssu_byte_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error qcn_fifo_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"qcn_shap_gp0_sch_fifo_rd_err\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"qcn_shap_gp0_sch_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"qcn_shap_gp0_sch_fifo_wr_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"qcn_shap_gp0_sch_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"qcn_shap_gp1_sch_fifo_rd_err\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"qcn_shap_gp1_sch_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"qcn_shap_gp1_sch_fifo_wr_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"qcn_shap_gp1_sch_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"qcn_shap_gp2_sch_fifo_rd_err\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"qcn_shap_gp2_sch_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"qcn_shap_gp2_sch_fifo_wr_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"qcn_shap_gp2_sch_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"qcn_shap_gp3_sch_fifo_rd_err\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"qcn_shap_gp3_sch_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"qcn_shap_gp3_sch_fifo_wr_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"qcn_shap_gp3_sch_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"qcn_shap_gp0_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"qcn_shap_gp0_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"qcn_shap_gp0_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"qcn_shap_gp0_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"qcn_shap_gp1_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"qcn_shap_gp1_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"qcn_shap_gp1_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"qcn_shap_gp1_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"qcn_shap_gp2_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"qcn_shap_gp2_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"qcn_shap_gp2_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"qcn_shap_gp2_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"qcn_shap_gp3_offset_fifo_rd_err\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"qcn_shap_gp3_offset_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"qcn_shap_gp3_offset_fifo_wr_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"qcn_shap_gp3_offset_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(16), .msg = \"qcn_byte_info_fifo_rd_err\",\n+\t{ .int_msk = BIT(16),\n+\t  .msg = \"qcn_byte_info_fifo_rd_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"qcn_byte_info_fifo_wr_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"qcn_byte_info_fifo_wr_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error qcn_ecc_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"qcn_byte_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"qcn_byte_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"qcn_time_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"qcn_time_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"qcn_fb_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"qcn_fb_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"qcn_link_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"qcn_link_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"qcn_rate_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"qcn_rate_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"qcn_tmplt_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"qcn_tmplt_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"qcn_shap_cfg_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"qcn_shap_cfg_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"qcn_gp0_barrel_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"qcn_gp0_barrel_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"qcn_gp1_barrel_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"qcn_gp1_barrel_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(19), .msg = \"qcn_gp2_barrel_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(19),\n+\t  .msg = \"qcn_gp2_barrel_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(21), .msg = \"qcn_gp3_barral_mem_ecc_mbit_err\",\n+\t{ .int_msk = BIT(21),\n+\t  .msg = \"qcn_gp3_barral_mem_ecc_mbit_err\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ncsi_ecc_int[] = {\n-\t{ .int_msk = BIT(1), .msg = \"ncsi_tx_ecc_mbit_err\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"ncsi_tx_ecc_mbit_err\",\n \t  .reset_level = HNS3_NONE_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_fifo_overflow_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"ig_mac_inf_int\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"ig_mac_inf_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"ig_host_inf_int\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"ig_host_inf_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"ig_roc_buf_int\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"ig_roc_buf_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"ig_host_data_fifo_int\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"ig_host_data_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"ig_host_key_fifo_int\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"ig_host_key_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"tx_qcn_fifo_int\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"tx_qcn_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"rx_qcn_fifo_int\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"rx_qcn_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"tx_pf_rd_fifo_int\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"tx_pf_rd_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"rx_pf_rd_fifo_int\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"rx_pf_rd_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(9), .msg = \"qm_eof_fifo_int\",\n+\t{ .int_msk = BIT(9),\n+\t  .msg = \"qm_eof_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(10), .msg = \"mb_rlt_fifo_int\",\n+\t{ .int_msk = BIT(10),\n+\t  .msg = \"mb_rlt_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"dup_uncopy_fifo_int\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"dup_uncopy_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"dup_cnt_rd_fifo_int\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"dup_cnt_rd_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"dup_cnt_drop_fifo_int\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"dup_cnt_drop_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"dup_cnt_wrb_fifo_int\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"dup_cnt_wrb_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(15), .msg = \"host_cmd_fifo_int\",\n+\t{ .int_msk = BIT(15),\n+\t  .msg = \"host_cmd_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(16), .msg = \"mac_cmd_fifo_int\",\n+\t{ .int_msk = BIT(16),\n+\t  .msg = \"mac_cmd_fifo_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(17), .msg = \"host_cmd_bitmap_empty_int\",\n+\t{ .int_msk = BIT(17),\n+\t  .msg = \"host_cmd_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(18), .msg = \"mac_cmd_bitmap_empty_int\",\n+\t{ .int_msk = BIT(18),\n+\t  .msg = \"mac_cmd_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(19), .msg = \"dup_bitmap_empty_int\",\n+\t{ .int_msk = BIT(19),\n+\t  .msg = \"dup_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(20), .msg = \"out_queue_bitmap_empty_int\",\n+\t{ .int_msk = BIT(20),\n+\t  .msg = \"out_queue_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(21), .msg = \"bank2_bitmap_empty_int\",\n+\t{ .int_msk = BIT(21),\n+\t  .msg = \"bank2_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(22), .msg = \"bank1_bitmap_empty_int\",\n+\t{ .int_msk = BIT(22),\n+\t  .msg = \"bank1_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(23), .msg = \"bank0_bitmap_empty_int\",\n+\t{ .int_msk = BIT(23),\n+\t  .msg = \"bank0_bitmap_empty_int\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_ets_tcg_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"ets_rd_int_rx_tcg\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"ets_rd_int_rx_tcg\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"ets_wr_int_rx_tcg\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"ets_wr_int_rx_tcg\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"ets_rd_int_tx_tcg\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"ets_rd_int_tx_tcg\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"ets_wr_int_tx_tcg\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"ets_wr_int_tx_tcg\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error igu_egu_tnl_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"rx_buf_overflow\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"rx_buf_overflow\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"rx_stp_fifo_overflow\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"rx_stp_fifo_overflow\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"rx_stp_fifo_underflow\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"rx_stp_fifo_underflow\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"tx_buf_overflow\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"tx_buf_overflow\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"tx_buf_underrun\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"tx_buf_underrun\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"rx_stp_buf_overflow\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"rx_stp_buf_overflow\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error ssu_port_based_err_int[] = {\n-\t{ .int_msk = BIT(0), .msg = \"roc_pkt_without_key_port\",\n+\t{ .int_msk = BIT(0),\n+\t  .msg = \"roc_pkt_without_key_port\",\n \t  .reset_level = HNS3_FUNC_RESET },\n-\t{ .int_msk = BIT(1), .msg = \"tpu_pkt_without_key_port\",\n+\t{ .int_msk = BIT(1),\n+\t  .msg = \"tpu_pkt_without_key_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(2), .msg = \"igu_pkt_without_key_port\",\n+\t{ .int_msk = BIT(2),\n+\t  .msg = \"igu_pkt_without_key_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(3), .msg = \"roc_eof_mis_match_port\",\n+\t{ .int_msk = BIT(3),\n+\t  .msg = \"roc_eof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(4), .msg = \"tpu_eof_mis_match_port\",\n+\t{ .int_msk = BIT(4),\n+\t  .msg = \"tpu_eof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(5), .msg = \"igu_eof_mis_match_port\",\n+\t{ .int_msk = BIT(5),\n+\t  .msg = \"igu_eof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(6), .msg = \"roc_sof_mis_match_port\",\n+\t{ .int_msk = BIT(6),\n+\t  .msg = \"roc_sof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(7), .msg = \"tpu_sof_mis_match_port\",\n+\t{ .int_msk = BIT(7),\n+\t  .msg = \"tpu_sof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(8), .msg = \"igu_sof_mis_match_port\",\n+\t{ .int_msk = BIT(8),\n+\t  .msg = \"igu_sof_mis_match_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(11), .msg = \"ets_rd_int_rx_port\",\n+\t{ .int_msk = BIT(11),\n+\t  .msg = \"ets_rd_int_rx_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(12), .msg = \"ets_wr_int_rx_port\",\n+\t{ .int_msk = BIT(12),\n+\t  .msg = \"ets_wr_int_rx_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(13), .msg = \"ets_rd_int_tx_port\",\n+\t{ .int_msk = BIT(13),\n+\t  .msg = \"ets_rd_int_tx_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = BIT(14), .msg = \"ets_wr_int_tx_port\",\n+\t{ .int_msk = BIT(14),\n+\t  .msg = \"ets_wr_int_tx_port\",\n \t  .reset_level = HNS3_GLOBAL_RESET },\n-\t{ .int_msk = 0, .msg = NULL,\n+\t{ .int_msk = 0,\n+\t  .msg = NULL,\n \t  .reset_level = HNS3_NONE_RESET}\n };\n \n static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = \"IMP_TCM_ECC_INT_STS\",\n \t  .hw_err = imp_tcm_ecc_int },\n-\t{ .desc_offset = 0, .data_offset = 1,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 1,\n \t  .msg = \"CMDQ_MEM_ECC_INT_STS\",\n \t  .hw_err = cmdq_mem_ecc_int },\n-\t{ .desc_offset = 0, .data_offset = 2,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 2,\n \t  .msg = \"IMP_RD_POISON_INT_STS\",\n \t  .hw_err = imp_rd_poison_int },\n-\t{ .desc_offset = 0, .data_offset = 3,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 3,\n \t  .msg = \"TQP_INT_ECC_INT_STS\",\n \t  .hw_err = tqp_int_ecc_int },\n-\t{ .desc_offset = 0, .data_offset = 4,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 4,\n \t  .msg = \"MSIX_ECC_INT_STS\",\n \t  .hw_err = msix_ecc_int },\n-\t{ .desc_offset = 2, .data_offset = 2,\n+\t{ .desc_offset = 2,\n+\t  .data_offset = 2,\n \t  .msg = \"SSU_ECC_MULTI_BIT_INT_0\",\n \t  .hw_err = ssu_ecc_multi_bit_int_0 },\n-\t{ .desc_offset = 2, .data_offset = 3,\n+\t{ .desc_offset = 2,\n+\t  .data_offset = 3,\n \t  .msg = \"SSU_ECC_MULTI_BIT_INT_1\",\n \t  .hw_err = ssu_ecc_multi_bit_int_1 },\n-\t{ .desc_offset = 2, .data_offset = 4,\n+\t{ .desc_offset = 2,\n+\t  .data_offset = 4,\n \t  .msg = \"SSU_COMMON_ERR_INT\",\n \t  .hw_err = ssu_common_ecc_int },\n-\t{ .desc_offset = 3, .data_offset = 0,\n+\t{ .desc_offset = 3,\n+\t  .data_offset = 0,\n \t  .msg = \"IGU_INT_STS\",\n \t  .hw_err = igu_int },\n-\t{ .desc_offset = 4, .data_offset = 1,\n+\t{ .desc_offset = 4,\n+\t  .data_offset = 1,\n \t  .msg = \"PPP_MPF_ABNORMAL_INT_ST1\",\n \t  .hw_err = ppp_mpf_abnormal_int_st1 },\n-\t{ .desc_offset = 4, .data_offset = 3,\n+\t{ .desc_offset = 4,\n+\t  .data_offset = 3,\n \t  .msg = \"PPP_MPF_ABNORMAL_INT_ST3\",\n \t  .hw_err = ppp_mpf_abnormal_int_st3 },\n-\t{ .desc_offset = 5, .data_offset = 1,\n+\t{ .desc_offset = 5,\n+\t  .data_offset = 1,\n \t  .msg = \"PPU_MPF_ABNORMAL_INT_ST1\",\n \t  .hw_err = ppu_mpf_abnormal_int_st1 },\n-\t{ .desc_offset = 5, .data_offset = 2,\n+\t{ .desc_offset = 5,\n+\t  .data_offset = 2,\n \t  .msg = \"PPU_MPF_ABNORMAL_INT_ST2_RAS\",\n \t  .hw_err = ppu_mpf_abnormal_int_st2_ras },\n-\t{ .desc_offset = 5, .data_offset = 3,\n+\t{ .desc_offset = 5,\n+\t  .data_offset = 3,\n \t  .msg = \"PPU_MPF_ABNORMAL_INT_ST3\",\n \t  .hw_err = ppu_mpf_abnormal_int_st3 },\n-\t{ .desc_offset = 6, .data_offset = 0,\n+\t{ .desc_offset = 6,\n+\t  .data_offset = 0,\n \t  .msg = \"TM_SCH_RINT\",\n \t  .hw_err = tm_sch_int },\n-\t{ .desc_offset = 7, .data_offset = 0,\n+\t{ .desc_offset = 7,\n+\t  .data_offset = 0,\n \t  .msg = \"QCN_FIFO_RINT\",\n \t  .hw_err = qcn_fifo_int },\n-\t{ .desc_offset = 7, .data_offset = 1,\n+\t{ .desc_offset = 7,\n+\t  .data_offset = 1,\n \t  .msg = \"QCN_ECC_RINT\",\n \t  .hw_err = qcn_ecc_int },\n-\t{ .desc_offset = 9, .data_offset = 0,\n+\t{ .desc_offset = 9,\n+\t  .data_offset = 0,\n \t  .msg = \"NCSI_ECC_INT_RPT\",\n \t  .hw_err = ncsi_ecc_int },\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = NULL,\n \t  .hw_err = NULL }\n };\n \n static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = \"SSU_PORT_BASED_ERR_INT_RAS\",\n \t  .hw_err = ssu_port_based_err_int },\n-\t{ .desc_offset = 0, .data_offset = 1,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 1,\n \t  .msg = \"SSU_FIFO_OVERFLOW_INT\",\n \t  .hw_err = ssu_fifo_overflow_int },\n-\t{ .desc_offset = 0, .data_offset = 2,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 2,\n \t  .msg = \"SSU_ETS_TCG_INT\",\n \t  .hw_err = ssu_ets_tcg_int },\n-\t{ .desc_offset = 1, .data_offset = 0,\n+\t{ .desc_offset = 1,\n+\t  .data_offset = 0,\n \t  .msg = \"IGU_EGU_TNL_INT_STS\",\n \t  .hw_err = igu_egu_tnl_int },\n-\t{ .desc_offset = 3, .data_offset = 0,\n+\t{ .desc_offset = 3,\n+\t  .data_offset = 0,\n \t  .msg = \"PPU_PF_ABNORMAL_INT_ST_RAS\",\n \t  .hw_err = ppu_pf_abnormal_int_ras },\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = NULL,\n \t  .hw_err = NULL }\n };\n \n static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {\n-\t{ .desc_offset = 1, .data_offset = 0,\n+\t{ .desc_offset = 1,\n+\t  .data_offset = 0,\n \t  .msg = \"MAC_AFIFO_TNL_INT_R\",\n \t  .hw_err = mac_afifo_tnl_int },\n-\t{ .desc_offset = 5, .data_offset = 2,\n+\t{ .desc_offset = 5,\n+\t  .data_offset = 2,\n \t  .msg = \"PPU_MPF_ABNORMAL_INT_ST2_MSIX\",\n \t  .hw_err = ppu_mpf_abnormal_int_st2_msix },\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = NULL,\n \t  .hw_err = NULL }\n };\n \n static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = \"SSU_PORT_BASED_ERR_INT_MSIX\",\n \t  .hw_err = ssu_port_based_pf_int },\n-\t{ .desc_offset = 2, .data_offset = 0,\n+\t{ .desc_offset = 2,\n+\t  .data_offset = 0,\n \t  .msg = \"PPP_PF_ABNORMAL_INT_ST0\",\n \t  .hw_err = ppp_pf_abnormal_int },\n-\t{ .desc_offset = 3, .data_offset = 0,\n+\t{ .desc_offset = 3,\n+\t  .data_offset = 0,\n \t  .msg = \"PPU_PF_ABNORMAL_INT_ST_MSIX\",\n \t  .hw_err = ppu_pf_abnormal_int_msix },\n-\t{ .desc_offset = 0, .data_offset = 0,\n+\t{ .desc_offset = 0,\n+\t  .data_offset = 0,\n \t  .msg = NULL,\n \t  .hw_err = NULL }\n };\n",
    "prefixes": [
        "V3",
        "3/6"
    ]
}