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GET /api/patches/8318/?format=api
{ "id": 8318, "url": "http://patches.dpdk.org/api/patches/8318/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-11-git-send-email-cunming.liang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446182873-28814-11-git-send-email-cunming.liang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446182873-28814-11-git-send-email-cunming.liang@intel.com", "date": "2015-10-30T05:27:52", "name": "[dpdk-dev,v2,10/11] i40evf: add rx interrupt support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "585d76095736032b1536471adb7a66309e672b3f", "submitter": { "id": 46, "url": "http://patches.dpdk.org/api/people/46/?format=api", "name": "Cunming Liang", "email": "cunming.liang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-11-git-send-email-cunming.liang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8318/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8318/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id E74C58E96;\n\tFri, 30 Oct 2015 06:28:28 +0100 (CET)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 92DC78E6A\n\tfor <dev@dpdk.org>; Fri, 30 Oct 2015 06:28:25 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga103.jf.intel.com with ESMTP; 29 Oct 2015 22:28:25 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 29 Oct 2015 22:28:25 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9U5SMkl023357;\n\tFri, 30 Oct 2015 13:28:22 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9U5SJh8028933; Fri, 30 Oct 2015 13:28:21 +0800", "(from cliang18@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U5SJdP028929; \n\tFri, 30 Oct 2015 13:28:19 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,217,1444719600\"; d=\"scan'208\";a=\"807195659\"", "From": "Cunming Liang <cunming.liang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 30 Oct 2015 13:27:52 +0800", "Message-Id": "<1446182873-28814-11-git-send-email-cunming.liang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1446182873-28814-1-git-send-email-cunming.liang@intel.com>", "References": "<1443072831-19065-1-git-send-email-cunming.liang@intel.com>\n\t<1446182873-28814-1-git-send-email-cunming.liang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 10/11] i40evf: add rx interrupt support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "v2 changes:\n - turn on intr only when rxq flag is set\n - rework base on patch http://dpdk.org/dev/patchwork/patch/7504/\n\nThe patch enables rx interrupt support on i40e VF and some necessary change on PF IOV mode to support VF.\nOn PF side, running in IOV mode via uio won't allow rx interrupt which is exclusive with mbox interrupt\nin single vector competition.\nOn VF side, one single vector is shared for all the rx queues.\n\nSigned-off-by: Cunming Liang <cunming.liang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 38 +++++-----\n drivers/net/i40e/i40e_ethdev.h | 15 ++++\n drivers/net/i40e/i40e_ethdev_vf.c | 143 +++++++++++++++++++++++++++++++++++---\n drivers/net/i40e/i40e_pf.c | 5 --\n 4 files changed, 166 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex d4a663c..40ed852 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -75,11 +75,6 @@\n /* Maximun number of VSI */\n #define I40E_MAX_NUM_VSIS (384UL)\n \n-/* Default queue interrupt throttling time in microseconds */\n-#define I40E_ITR_INDEX_DEFAULT 0\n-#define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */\n-#define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */\n-\n #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */\n \n /* Mask of PF interrupt causes */\n@@ -762,16 +757,6 @@ i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)\n \tI40E_WRITE_FLUSH(hw);\n }\n \n-static inline uint16_t\n-i40e_calc_itr_interval(int16_t interval)\n-{\n-\tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)\n-\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n-\n-\t/* Convert to hardware count, as writing each 1 represents 2 us */\n-\treturn (interval/2);\n-}\n-\n static void\n __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \t\t int base_queue, int nb_queue)\n@@ -822,13 +807,24 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n \t} else {\n \t\tuint32_t reg;\n \n-\t\t/* num_msix_vectors_vf needs to minus irq0 */\n-\t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n-\t\t\tvsi->user_param + (msix_vect - 1);\n+\t\tif (msix_vect == MISC_VEC_ID) {\n+\t\t\tI40E_WRITE_REG(hw,\n+\t\t\t\t I40E_VPINT_LNKLST0(vsi->user_param),\n+\t\t\t\t (base_queue <<\n+\t\t\t\t\tI40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |\n+\t\t\t\t (0x0 <<\n+\t\t\t\t\tI40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));\n+\t\t} else {\n+\t\t\t/* num_msix_vectors_vf needs to minus irq0 */\n+\t\t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n+\t\t\t\tvsi->user_param + (msix_vect - 1);\n \n-\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (base_queue <<\n-\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n-\t\t\t\t(0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n+\t\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),\n+\t\t\t\t (base_queue <<\n+\t\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n+\t\t\t\t (0x0 <<\n+\t\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n+\t\t}\n \t}\n \n \tI40E_WRITE_FLUSH(hw);\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 20d52f8..eeff6d7 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -156,6 +156,11 @@ enum i40e_flxpld_layer_idx {\n \t(1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \\\n \t(1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n+/* Default queue interrupt throttling time in microseconds */\n+#define I40E_ITR_INDEX_DEFAULT 0\n+#define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */\n+#define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */\n+\n struct i40e_adapter;\n \n /**\n@@ -578,6 +583,16 @@ i40e_align_floor(int n)\n \treturn 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));\n }\n \n+static inline uint16_t\n+i40e_calc_itr_interval(int16_t interval)\n+{\n+\tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)\n+\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n+\n+\t/* Convert to hardware count, as writing each 1 represents 2 us */\n+\treturn (interval / 2);\n+}\n+\n #define I40E_VALID_FLOW(flow_type) \\\n \t((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \\\n \t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \\\ndiff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\nindex 176a2f6..4fdb401 100644\n--- a/drivers/net/i40e/i40e_ethdev_vf.c\n+++ b/drivers/net/i40e/i40e_ethdev_vf.c\n@@ -145,6 +145,10 @@ static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_rss_conf *rss_conf);\n static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n+static int\n+i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);\n+static int\n+i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);\n \n /* Default hash key buffer for RSS */\n static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];\n@@ -170,6 +174,9 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {\n \t.tx_queue_stop = i40evf_dev_tx_queue_stop,\n \t.rx_queue_setup = i40e_dev_rx_queue_setup,\n \t.rx_queue_release = i40e_dev_rx_queue_release,\n+\t.rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,\n+\t.rx_descriptor_done = i40e_dev_rx_descriptor_done,\n \t.tx_queue_setup = i40e_dev_tx_queue_setup,\n \t.tx_queue_release = i40e_dev_tx_queue_release,\n \t.reta_update = i40evf_dev_rss_reta_update,\n@@ -712,22 +719,33 @@ i40evf_config_irq_map(struct rte_eth_dev *dev)\n \tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \\\n \t\tsizeof(struct i40e_virtchnl_vector_map)];\n \tstruct i40e_virtchnl_irq_map_info *map_info;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tuint32_t vector_id;\n \tint i, err;\n+\n+\tif (rte_intr_allow_others(intr_handle)) {\n+\t\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n+\t\t\tvector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;\n+\t\telse\n+\t\t\tvector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;\n+\t} else {\n+\t\tvector_id = MISC_VEC_ID;\n+\t}\n+\n \tmap_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;\n \tmap_info->num_vectors = 1;\n \tmap_info->vecmap[0].rxitr_idx = I40E_QINT_RQCTL_MSIX_INDX_NOITR;\n \tmap_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;\n \t/* Alway use default dynamic MSIX interrupt */\n-\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n-\t\tmap_info->vecmap[0].vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;\n-\telse\n-\t\tmap_info->vecmap[0].vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;\n-\n+\tmap_info->vecmap[0].vector_id = vector_id;\n \t/* Don't map any tx queue */\n \tmap_info->vecmap[0].txq_map = 0;\n \tmap_info->vecmap[0].rxq_map = 0;\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tmap_info->vecmap[0].rxq_map |= 1 << i;\n+\t\tif (rte_intr_dp_is_en(intr_handle))\n+\t\t\tintr_handle->intr_vec[i] = vector_id;\n+\t}\n \n \targs.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;\n \targs.in_args = (u8 *)cmd_buffer;\n@@ -1565,6 +1583,16 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev)\n {\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\n+\tif (!rte_intr_allow_others(intr_handle)) {\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_VFINT_DYN_CTL01,\n+\t\t\t I40E_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\treturn;\n+\t}\n \n \tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n \t\t/* To support DPDK PF host */\n@@ -1577,6 +1605,8 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev)\n \t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n \t\t\t\tI40E_VFINT_DYN_CTL01_INTENA_MASK |\n \t\t\t\tI40E_VFINT_DYN_CTL01_CLEARPBA_MASK);\n+\n+\tI40E_WRITE_FLUSH(hw);\n }\n \n static inline void\n@@ -1584,14 +1614,76 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev)\n {\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\n+\tif (!rte_intr_allow_others(intr_handle)) {\n+\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);\n+\t\tI40E_WRITE_FLUSH(hw);\n+\t\treturn;\n+\t}\n \n \tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n \t\tI40E_WRITE_REG(hw,\n-\t\t\tI40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),\n-\t\t\t0);\n+\t\t\t I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR\n+\t\t\t\t\t\t - 1),\n+\t\t\t 0);\n \telse\n \t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);\n \n+\tI40E_WRITE_FLUSH(hw);\n+}\n+\n+static int\n+i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t interval =\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = intr_handle->intr_vec[queue_id];\n+\tif (msix_intr == MISC_VEC_ID)\n+\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,\n+\t\t\t I40E_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |\n+\t\t\t (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n+\t\t\t (interval <<\n+\t\t\t\tI40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));\n+\telse\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_VFINT_DYN_CTLN1(msix_intr - RX_VEC_START),\n+\t\t\t I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n+\t\t\t (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n+\t\t\t (interval <<\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\trte_intr_enable(&dev->pci_dev->intr_handle);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = intr_handle->intr_vec[queue_id];\n+\tif (msix_intr == MISC_VEC_ID)\n+\t\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);\n+\telse\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_VFINT_DYN_CTLN1(msix_intr - RX_VEC_START),\n+\t\t\t 0);\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n }\n \n static int\n@@ -1599,7 +1691,9 @@ i40evf_dev_start(struct rte_eth_dev *dev)\n {\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct ether_addr mac_addr;\n+\tuint32_t intr_vector = 0;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -1609,6 +1703,24 @@ i40evf_dev_start(struct rte_eth_dev *dev)\n \tvf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,\n \t\t\t\t\tdev->data->nb_tx_queues);\n \n+\t/* check and configure queue intr-vector mapping */\n+\tif (dev->data->dev_conf.intr_conf.rxq != 0) {\n+\t\tintr_vector = dev->data->nb_rx_queues;\n+\t\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n+\t\t\treturn -1;\n+\t}\n+\n+\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n+\t\tintr_handle->intr_vec =\n+\t\t\trte_zmalloc(\"intr_vec\",\n+\t\t\t\t dev->data->nb_rx_queues * sizeof(int), 0);\n+\t\tif (!intr_handle->intr_vec) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n+\t\t\t\t \" intr_vec\\n\", dev->data->nb_rx_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n \tif (i40evf_rx_init(dev) != 0){\n \t\tPMD_DRV_LOG(ERR, \"failed to do RX init\");\n \t\treturn -1;\n@@ -1638,6 +1750,10 @@ i40evf_dev_start(struct rte_eth_dev *dev)\n \t\tgoto err_mac;\n \t}\n \n+\t/* vf don't allow intr except for rxq intr */\n+\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n+\t\trte_intr_enable(intr_handle);\n+\n \ti40evf_enable_queues_intr(dev);\n \treturn 0;\n \n@@ -1650,11 +1766,20 @@ err_queue:\n static void\n i40evf_dev_stop(struct rte_eth_dev *dev)\n {\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n-\ti40evf_disable_queues_intr(dev);\n \ti40evf_stop_queues(dev);\n+\ti40evf_disable_queues_intr(dev);\n \ti40e_dev_clear_queues(dev);\n+\n+\t/* Clean datapath event and queue/vec mapping */\n+\trte_intr_efd_disable(intr_handle);\n+\tif (intr_handle->intr_vec) {\n+\t\trte_free(intr_handle->intr_vec);\n+\t\tintr_handle->intr_vec = NULL;\n+\t}\n }\n \n static int\ndiff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c\nindex c1d58a8..cbf4e5b 100644\n--- a/drivers/net/i40e/i40e_pf.c\n+++ b/drivers/net/i40e/i40e_pf.c\n@@ -547,11 +547,6 @@ i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,\n \t\tgoto send_msg;\n \t}\n \n-\tif (irqmap->vecmap[0].vector_id == 0) {\n-\t\tPMD_DRV_LOG(ERR, \"DPDK host don't support use IRQ0\");\n-\t\tret = I40E_ERR_PARAM;\n-\t\tgoto send_msg;\n-\t}\n \t/* This MSIX intr store the intr in VF range */\n \tvf->vsi->msix_intr = irqmap->vecmap[0].vector_id;\n \tvf->vsi->nb_msix = irqmap->num_vectors;\n", "prefixes": [ "dpdk-dev", "v2", "10/11" ] }