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GET /api/patches/8317/?format=api
{ "id": 8317, "url": "http://patches.dpdk.org/api/patches/8317/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-10-git-send-email-cunming.liang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446182873-28814-10-git-send-email-cunming.liang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446182873-28814-10-git-send-email-cunming.liang@intel.com", "date": "2015-10-30T05:27:51", "name": "[dpdk-dev,v2,09/11] i40e: add rx interrupt support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "729b019af966a5460cf1b951fee9ab3341ae391b", "submitter": { "id": 46, "url": "http://patches.dpdk.org/api/people/46/?format=api", "name": "Cunming Liang", "email": "cunming.liang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-10-git-send-email-cunming.liang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8317/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8317/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DA9558E91;\n\tFri, 30 Oct 2015 06:28:27 +0100 (CET)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 5C5FA8E6A\n\tfor <dev@dpdk.org>; Fri, 30 Oct 2015 06:28:24 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP; 29 Oct 2015 22:28:23 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 29 Oct 2015 22:28:22 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9U5SK4J023354;\n\tFri, 30 Oct 2015 13:28:20 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9U5SGqD028926; Fri, 30 Oct 2015 13:28:18 +0800", "(from cliang18@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U5SGTU028922; \n\tFri, 30 Oct 2015 13:28:16 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,217,1444719600\"; d=\"scan'208\";a=\"839040091\"", "From": "Cunming Liang <cunming.liang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 30 Oct 2015 13:27:51 +0800", "Message-Id": "<1446182873-28814-10-git-send-email-cunming.liang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1446182873-28814-1-git-send-email-cunming.liang@intel.com>", "References": "<1443072831-19065-1-git-send-email-cunming.liang@intel.com>\n\t<1446182873-28814-1-git-send-email-cunming.liang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 09/11] i40e: add rx interrupt support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "v2 changes:\n - add write flush\n - always set DIS_AUTOMASK_* bit\n\nThe patch enables rx interrupt support on i40e PF non-IOV mode.\nPer queue rx interrupt works on vfio, however on uio, all rx queues share one interrupt vector.\n\nSigned-off-by: Cunming Liang <cunming.liang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 342 +++++++++++++++++++++++++++++++++++------\n drivers/net/i40e/i40e_ethdev.h | 2 +\n drivers/net/i40e/i40e_pf.c | 2 +\n 3 files changed, 298 insertions(+), 48 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 2dd9fdc..d4a663c 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -39,6 +39,7 @@\n #include <unistd.h>\n #include <stdarg.h>\n #include <inttypes.h>\n+#include <assert.h>\n \n #include <rte_string_fns.h>\n #include <rte_pci.h>\n@@ -174,7 +175,7 @@ static void i40e_stat_update_48(struct i40e_hw *hw,\n \t\t\t bool offset_loaded,\n \t\t\t uint64_t *offset,\n \t\t\t uint64_t *stat);\n-static void i40e_pf_config_irq0(struct i40e_hw *hw);\n+static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);\n static void i40e_dev_interrupt_handler(\n \t\t__rte_unused struct rte_intr_handle *handle, void *param);\n static int i40e_res_pool_init(struct i40e_res_pool_info *pool,\n@@ -232,6 +233,10 @@ static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t flags);\n static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t struct timespec *timestamp);\n+static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,\n+\t\t\t\t\t uint16_t queue_id);\n+static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,\n+\t\t\t\t\t uint16_t queue_id);\n \n static const struct rte_pci_id pci_id_i40e_map[] = {\n #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n@@ -265,6 +270,8 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.tx_queue_start = i40e_dev_tx_queue_start,\n \t.tx_queue_stop = i40e_dev_tx_queue_stop,\n \t.rx_queue_setup = i40e_dev_rx_queue_setup,\n+\t.rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,\n \t.rx_queue_release = i40e_dev_rx_queue_release,\n \t.rx_queue_count = i40e_dev_rx_queue_count,\n \t.rx_descriptor_done = i40e_dev_rx_descriptor_done,\n@@ -579,7 +586,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \t\ti40e_dev_interrupt_handler, (void *)dev);\n \n \t/* configure and enable device interrupt */\n-\ti40e_pf_config_irq0(hw);\n+\ti40e_pf_config_irq0(hw, TRUE);\n \ti40e_pf_enable_irq0(hw);\n \n \t/* enable uio intr after callback register */\n@@ -718,6 +725,8 @@ err:\n void\n i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)\n {\n+\tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n \tuint16_t msix_vect = vsi->msix_intr;\n \tuint16_t i;\n@@ -729,15 +738,26 @@ i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)\n \t}\n \n \tif (vsi->type != I40E_VSI_SRIOV) {\n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);\n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n-\t\t\t\tmsix_vect - 1), 0);\n+\t\tif (!rte_intr_allow_others(intr_handle)) {\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n+\t\t\t\t I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);\n+\t\t\tI40E_WRITE_REG(hw,\n+\t\t\t\t I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),\n+\t\t\t\t 0);\n+\t\t} else {\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),\n+\t\t\t\t I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);\n+\t\t\tI40E_WRITE_REG(hw,\n+\t\t\t\t I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n+\t\t\t\t\t\t msix_vect - 1), 0);\n+\t\t}\n \t} else {\n \t\tuint32_t reg;\n \t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n \t\t\tvsi->user_param + (msix_vect - 1);\n \n-\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);\n+\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),\n+\t\t\t I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);\n \t}\n \tI40E_WRITE_FLUSH(hw);\n }\n@@ -752,29 +772,26 @@ i40e_calc_itr_interval(int16_t interval)\n \treturn (interval/2);\n }\n \n-void\n-i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n+static void\n+__vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,\n+\t\t int base_queue, int nb_queue)\n {\n+\tint i;\n \tuint32_t val;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tuint16_t msix_vect = vsi->msix_intr;\n-\tint i;\n-\n-\tfor (i = 0; i < vsi->nb_qps; i++)\n-\t\tI40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);\n \n \t/* Bind all RX queues to allocated MSIX interrupt */\n-\tfor (i = 0; i < vsi->nb_qps; i++) {\n+\tfor (i = 0; i < nb_queue; i++) {\n \t\tval = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |\n \t\t\tI40E_QINT_RQCTL_ITR_INDX_MASK |\n-\t\t\t((vsi->base_queue + i + 1) <<\n-\t\t\tI40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |\n+\t\t\t((base_queue + i + 1) <<\n+\t\t\t I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |\n \t\t\t(0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |\n \t\t\tI40E_QINT_RQCTL_CAUSE_ENA_MASK;\n \n-\t\tif (i == vsi->nb_qps - 1)\n+\t\tif (i == nb_queue - 1)\n \t\t\tval |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;\n-\t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);\n+\t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);\n \t}\n \n \t/* Write first RX queue to Link list register as the head element */\n@@ -782,21 +799,26 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n \t\tuint16_t interval =\n \t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n \n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),\n-\t\t\t\t\t\t(vsi->base_queue <<\n-\t\t\t\tI40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n-\t\t\t(0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n-\n-\t\tI40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n-\t\t\t\t\t\tmsix_vect - 1), interval);\n-\n-#ifndef I40E_GLINT_CTL\n-#define I40E_GLINT_CTL 0x0003F800\n-#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4\n-#endif\n-\t\t/* Disable auto-mask on enabling of all none-zero interrupt */\n-\t\tI40E_WRITE_REG(hw, I40E_GLINT_CTL,\n-\t\t\tI40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);\n+\t\tif (msix_vect == MISC_VEC_ID) {\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n+\t\t\t\t (base_queue <<\n+\t\t\t\t\tI40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |\n+\t\t\t\t (0x0 <<\n+\t\t\t\t\tI40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));\n+\t\t\tI40E_WRITE_REG(hw,\n+\t\t\t\t I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),\n+\t\t\t\t interval);\n+\t\t} else {\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),\n+\t\t\t\t (base_queue <<\n+\t\t\t\t\tI40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n+\t\t\t\t (0x0 <<\n+\t\t\t\t\tI40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n+\t\t\tI40E_WRITE_REG(hw,\n+\t\t\t\t I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n+\t\t\t\t\t\t msix_vect - 1),\n+\t\t\t\t interval);\n+\t\t}\n \t} else {\n \t\tuint32_t reg;\n \n@@ -804,34 +826,134 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n \t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n \t\t\tvsi->user_param + (msix_vect - 1);\n \n-\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<\n-\t\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n+\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (base_queue <<\n+\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n \t\t\t\t(0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n \t}\n \n \tI40E_WRITE_FLUSH(hw);\n }\n \n+void\n+i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n+{\n+\tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tuint16_t msix_vect = vsi->msix_intr;\n+\tuint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);\n+\tuint16_t queue_idx = 0;\n+\tint record = 0;\n+\tuint32_t val;\n+\tint i;\n+\n+\tfor (i = 0; i < vsi->nb_qps; i++) {\n+\t\tI40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);\n+\t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);\n+\t}\n+\n+\t/* INTENA flag is not auto-cleared for interrupt */\n+\tval = I40E_READ_REG(hw, I40E_GLINT_CTL);\n+\tval |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |\n+\t\tI40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |\n+\t\tI40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;\n+\tI40E_WRITE_REG(hw, I40E_GLINT_CTL, val);\n+\n+\t/* VF bind interrupt */\n+\tif (vsi->type == I40E_VSI_SRIOV) {\n+\t\t__vsi_queues_bind_intr(vsi, msix_vect,\n+\t\t\t\t vsi->base_queue, vsi->nb_qps);\n+\t\treturn;\n+\t}\n+\n+\t/* PF & VMDq bind interrupt */\n+\tif (rte_intr_dp_is_en(intr_handle)) {\n+\t\tif (vsi->type == I40E_VSI_MAIN) {\n+\t\t\tqueue_idx = 0;\n+\t\t\trecord = 1;\n+\t\t} else if (vsi->type == I40E_VSI_VMDQ2) {\n+\t\t\tstruct i40e_vsi *main_vsi =\n+\t\t\t\tI40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);\n+\t\t\tqueue_idx = vsi->base_queue - main_vsi->nb_qps;\n+\t\t\trecord = 1;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < vsi->nb_used_qps; i++) {\n+\t\tif (nb_msix <= 1) {\n+\t\t\tif (!rte_intr_allow_others(intr_handle))\n+\t\t\t\t/* allow to share MISC_VEC_ID */\n+\t\t\t\tmsix_vect = MISC_VEC_ID;\n+\n+\t\t\t/* no enough msix_vect, map all to one */\n+\t\t\t__vsi_queues_bind_intr(vsi, msix_vect,\n+\t\t\t\t\t vsi->base_queue + i,\n+\t\t\t\t\t vsi->nb_used_qps - i);\n+\t\t\tfor (; !!record && i < vsi->nb_used_qps; i++)\n+\t\t\t\tintr_handle->intr_vec[queue_idx + i] =\n+\t\t\t\t\tmsix_vect;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* 1:1 queue/msix_vect mapping */\n+\t\t__vsi_queues_bind_intr(vsi, msix_vect,\n+\t\t\t\t vsi->base_queue + i, 1);\n+\t\tif (!!record)\n+\t\t\tintr_handle->intr_vec[queue_idx + i] = msix_vect;\n+\n+\t\tmsix_vect++;\n+\t\tnb_msix--;\n+\t}\n+}\n+\n static void\n i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)\n {\n+\tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n \tuint16_t interval = i40e_calc_itr_interval(\\\n-\t\t\tRTE_LIBRTE_I40E_ITR_INTERVAL);\n-\n-\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),\n-\t\t\t\t\tI40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\tRTE_LIBRTE_I40E_ITR_INTERVAL);\n+\tuint16_t msix_intr, i;\n+\n+\tif (rte_intr_allow_others(intr_handle))\n+\t\tfor (i = 0; i < vsi->nb_msix; i++) {\n+\t\t\tmsix_intr = vsi->msix_intr + i;\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n+\t\t\t\tI40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n \t\t\t\t(0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t\t\t(interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\t\t\t\t(interval <<\n+\t\t\t\t I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\t\t}\n+\telse\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t\t I40E_PFINT_DYN_CTL0_INTENA_MASK |\n+\t\t\t I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |\n+\t\t\t (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |\n+\t\t\t (interval <<\n+\t\t\t\tI40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));\n+\n+\tI40E_WRITE_FLUSH(hw);\n }\n \n static void\n i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)\n {\n+\tstruct rte_eth_dev *dev = vsi->adapter->eth_dev;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n+\tuint16_t msix_intr, i;\n \n-\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);\n+\tif (rte_intr_allow_others(intr_handle))\n+\t\tfor (i = 0; i < vsi->nb_msix; i++) {\n+\t\t\tmsix_intr = vsi->msix_intr + i;\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),\n+\t\t\t\t 0);\n+\t\t}\n+\telse\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\n+\tI40E_WRITE_FLUSH(hw);\n }\n \n static inline uint8_t\n@@ -941,6 +1063,8 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct i40e_vsi *main_vsi = pf->main_vsi;\n \tint ret, i;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tuint32_t intr_vector = 0;\n \n \thw->adapter_stopped = 0;\n \n@@ -952,6 +1076,29 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \t\treturn -EINVAL;\n \t}\n \n+\trte_intr_disable(intr_handle);\n+\n+\tif (((RTE_ETH_DEV_SRIOV(dev).active &&\n+\t rte_intr_cap_multiple(intr_handle)) ||\n+\t !RTE_ETH_DEV_SRIOV(dev).active) &&\n+\t dev->data->dev_conf.intr_conf.rxq != 0) {\n+\t\tintr_vector = dev->data->nb_rx_queues;\n+\t\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n+\t\t\treturn -1;\n+\t}\n+\n+\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n+\t\tintr_handle->intr_vec =\n+\t\t\trte_zmalloc(\"intr_vec\",\n+\t\t\t\t dev->data->nb_rx_queues * sizeof(int),\n+\t\t\t\t 0);\n+\t\tif (!intr_handle->intr_vec) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n+\t\t\t\t \" intr_vec\\n\", dev->data->nb_rx_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n \t/* Initialize VSI */\n \tret = i40e_dev_rxtx_init(pf);\n \tif (ret != I40E_SUCCESS) {\n@@ -960,11 +1107,14 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \t}\n \n \t/* Map queues with MSIX interrupt */\n+\tmain_vsi->nb_used_qps = dev->data->nb_rx_queues -\n+\t\tpf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;\n \ti40e_vsi_queues_bind_intr(main_vsi);\n \ti40e_vsi_enable_queues_intr(main_vsi);\n \n \t/* Map VMDQ VSI queues with MSIX interrupt */\n \tfor (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {\n+\t\tpf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;\n \t\ti40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);\n \t\ti40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);\n \t}\n@@ -1001,6 +1151,22 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \t\tgoto err_up;\n \t}\n \n+\tif (!rte_intr_allow_others(intr_handle)) {\n+\t\trte_intr_callback_unregister(intr_handle,\n+\t\t\t\t\t i40e_dev_interrupt_handler,\n+\t\t\t\t\t (void *)dev);\n+\t\t/* configure and enable device interrupt */\n+\t\ti40e_pf_config_irq0(hw, FALSE);\n+\t\ti40e_pf_enable_irq0(hw);\n+\n+\t\tif (dev->data->dev_conf.intr_conf.lsc != 0)\n+\t\t\tPMD_INIT_LOG(INFO, \"lsc won't enable because of\"\n+\t\t\t\t \" no intr multiplex\\n\");\n+\t}\n+\n+\t/* enable uio intr after callback register */\n+\trte_intr_enable(intr_handle);\n+\n \treturn I40E_SUCCESS;\n \n err_up:\n@@ -1016,6 +1182,7 @@ i40e_dev_stop(struct rte_eth_dev *dev)\n \tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_vsi *main_vsi = pf->main_vsi;\n \tstruct i40e_mirror_rule *p_mirror;\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \tint i;\n \n \t/* Disable all queues */\n@@ -1047,6 +1214,18 @@ i40e_dev_stop(struct rte_eth_dev *dev)\n \t}\n \tpf->nb_mirror_rule = 0;\n \n+\tif (!rte_intr_allow_others(intr_handle))\n+\t\t/* resume to the default handler */\n+\t\trte_intr_callback_register(intr_handle,\n+\t\t\t\t\t i40e_dev_interrupt_handler,\n+\t\t\t\t\t (void *)dev);\n+\n+\t/* Clean datapath event and queue/vec mapping */\n+\trte_intr_efd_disable(intr_handle);\n+\tif (intr_handle->intr_vec) {\n+\t\trte_free(intr_handle->intr_vec);\n+\t\tintr_handle->intr_vec = NULL;\n+\t}\n }\n \n static void\n@@ -3073,15 +3252,30 @@ i40e_vsi_setup(struct i40e_pf *pf,\n \t\tvsi->base_queue = I40E_FDIR_QUEUE_ID;\n \n \t/* VF has MSIX interrupt in VF range, don't allocate here */\n-\tif (type != I40E_VSI_SRIOV) {\n+\tif (type == I40E_VSI_MAIN) {\n+\t\tret = i40e_res_pool_alloc(&pf->msix_pool,\n+\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n+\t\tif (ret < 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"VSI MAIN %d get heap failed %d\",\n+\t\t\t\t vsi->seid, ret);\n+\t\t\tgoto fail_queue_alloc;\n+\t\t}\n+\t\tvsi->msix_intr = ret;\n+\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);\n+\t} else if (type != I40E_VSI_SRIOV) {\n \t\tret = i40e_res_pool_alloc(&pf->msix_pool, 1);\n \t\tif (ret < 0) {\n \t\t\tPMD_DRV_LOG(ERR, \"VSI %d get heap failed %d\", vsi->seid, ret);\n \t\t\tgoto fail_queue_alloc;\n \t\t}\n \t\tvsi->msix_intr = ret;\n-\t} else\n+\t\tvsi->nb_msix = 1;\n+\t} else {\n \t\tvsi->msix_intr = 0;\n+\t\tvsi->nb_msix = 0;\n+\t}\n+\n \t/* Add VSI */\n \tif (type == I40E_VSI_MAIN) {\n \t\t/* For main VSI, no need to add since it's default one */\n@@ -3919,7 +4113,7 @@ i40e_pf_enable_irq0(struct i40e_hw *hw)\n }\n \n static void\n-i40e_pf_config_irq0(struct i40e_hw *hw)\n+i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)\n {\n \t/* read pending request and disable first */\n \ti40e_pf_disable_irq0(hw);\n@@ -3927,9 +4121,10 @@ i40e_pf_config_irq0(struct i40e_hw *hw)\n \tI40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,\n \t\tI40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);\n \n-\t/* Link no queues with irq0 */\n-\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n-\t\tI40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);\n+\tif (no_queue)\n+\t\t/* Link no queues with irq0 */\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n+\t\t\t I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);\n }\n \n static void\n@@ -6298,3 +6493,54 @@ i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \n \treturn 0;\n }\n+\n+static int\n+i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t interval =\n+\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = intr_handle->intr_vec[queue_id];\n+\tif (msix_intr == MISC_VEC_ID)\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n+\t\t\t I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t (interval <<\n+\t\t\t\tI40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\telse\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_PFINT_DYN_CTLN(msix_intr - RX_VEC_START),\n+\t\t\t I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t (interval <<\n+\t\t\t\tI40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\trte_intr_enable(&dev->pci_dev->intr_handle);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = intr_handle->intr_vec[queue_id];\n+\tif (msix_intr == MISC_VEC_ID)\n+\t\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n+\telse\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_PFINT_DYN_CTLN(msix_intr - RX_VEC_START),\n+\t\t\t 0);\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex d42487d..20d52f8 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -240,6 +240,7 @@ struct i40e_vsi {\n \tuint16_t seid; /* The seid of VSI itself */\n \tuint16_t uplink_seid; /* The uplink seid of this VSI */\n \tuint16_t nb_qps; /* Number of queue pairs VSI can occupy */\n+\tuint16_t nb_used_qps; /* Number of queue pairs VSI uses */\n \tuint16_t max_macaddrs; /* Maximum number of MAC addresses */\n \tuint16_t base_queue; /* The first queue index of this VSI */\n \t/*\n@@ -248,6 +249,7 @@ struct i40e_vsi {\n \t */\n \tuint16_t vsi_id;\n \tuint16_t msix_intr; /* The MSIX interrupt binds to VSI */\n+\tuint16_t nb_msix; /* The max number of msix vector */\n \tuint8_t enabled_tc; /* The traffic class enabled */\n };\n \ndiff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c\nindex 95c960c..c1d58a8 100644\n--- a/drivers/net/i40e/i40e_pf.c\n+++ b/drivers/net/i40e/i40e_pf.c\n@@ -554,6 +554,8 @@ i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,\n \t}\n \t/* This MSIX intr store the intr in VF range */\n \tvf->vsi->msix_intr = irqmap->vecmap[0].vector_id;\n+\tvf->vsi->nb_msix = irqmap->num_vectors;\n+\tvf->vsi->nb_used_qps = vf->vsi->nb_qps;\n \n \t/* Don't care how the TX/RX queue mapping with this vector.\n \t * Link all VF RX queues together. Only did mapping work.\n", "prefixes": [ "dpdk-dev", "v2", "09/11" ] }