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GET /api/patches/8308/?format=api
{ "id": 8308, "url": "http://patches.dpdk.org/api/patches/8308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446181055-28611-1-git-send-email-zhe.tao@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446181055-28611-1-git-send-email-zhe.tao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446181055-28611-1-git-send-email-zhe.tao@intel.com", "date": "2015-10-30T04:57:35", "name": "[dpdk-dev,v3] i40e: add link flow control support for FVL", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fe50505cce22eb222e285667e41cba1ac66bc505", "submitter": { "id": 276, "url": "http://patches.dpdk.org/api/people/276/?format=api", "name": "Zhe Tao", "email": "zhe.tao@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446181055-28611-1-git-send-email-zhe.tao@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8308/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8308/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 9A5E05A53;\n\tFri, 30 Oct 2015 05:57:48 +0100 (CET)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 8A8B05A4F\n\tfor <dev@dpdk.org>; Fri, 30 Oct 2015 05:57:46 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga103.fm.intel.com with ESMTP; 29 Oct 2015 21:57:45 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 29 Oct 2015 21:57:45 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9U4vh35028384;\n\tFri, 30 Oct 2015 12:57:43 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9U4veZT028645; Fri, 30 Oct 2015 12:57:42 +0800", "(from zhetao@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U4vdcu028641; \n\tFri, 30 Oct 2015 12:57:39 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,217,1444719600\"; d=\"scan'208\";a=\"590788737\"", "From": "Zhe Tao <zhe.tao@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 30 Oct 2015 12:57:35 +0800", "Message-Id": "<1446181055-28611-1-git-send-email-zhe.tao@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1446123397-18828-1-git-send-email-zhe.tao@intel.com>", "References": "<1446123397-18828-1-git-send-email-zhe.tao@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] i40e: add link flow control support for FVL", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Feature Add: Rx/Tx flow control support for the i40e\n\nAll the Rx/Tx LFC enable/disable operation is done by the F/W, \nso PMD driver need to use the Set PHY Config AD command to trigger the PHY \nto do the auto-negotiation, after the Tx/Rx pause ability is negotiated, \nthe F/W will help us to set the related LFC enable/disable registers.\nPMD driver also need to configure the related registers to control \nhow often to send the pause frame and what the value in the pause frame.\n\nSigned-off-by: Zhe Tao <zhe.tao@intel.com>\n---\n\nPATCH V1: add the LFC support for i40e\n\nPATCH v2: move the LFC parameters init to the i40e_pf_parameter_init\n\nPATCH v3: update the release note\n\n doc/guides/rel_notes/release_2_2.rst | 4 +\n drivers/net/i40e/i40e_ethdev.c | 170 ++++++++++++++++++++++++++++++++++-\n drivers/net/i40e/i40e_ethdev.h | 12 +++\n 3 files changed, 183 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst\nindex bc9b00f..3475aa7 100644\n--- a/doc/guides/rel_notes/release_2_2.rst\n+++ b/doc/guides/rel_notes/release_2_2.rst\n@@ -39,6 +39,10 @@ Drivers\n Fixed i40e issue that occurred when a DPDK application didn't initialize\n ports if memory wasn't available on socket 0.\n \n+* **i40e: Add the support for link flow control.**\n+\n+ Add the support for link flow control on FVL.\n+\n * **vhost: Fixed Qemu shutdown.**\n \n Fixed issue with libvirt ``virsh destroy`` not killing the VM.\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 2dd9fdc..e68e0b7 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -81,6 +81,27 @@\n \n #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */\n \n+/* Flow control default timer */\n+#define I40E_DEFAULT_PAUSE_TIME 0xFFFFU\n+\n+/* Flow control default high water */\n+#define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)\n+\n+/* Flow control default low water */\n+#define I40E_DEFAULT_LOW_WATER (0x1A40/1024)\n+\n+/* Flow control enable fwd bit */\n+#define I40E_PRTMAC_FWD_CTRL 0x00000001\n+\n+/* Receive Packet Buffer size */\n+#define I40E_RXPBSIZE (968 * 1024)\n+\n+/* Kilobytes shift */\n+#define I40E_KILOSHIFT 10\n+\n+/* Receive Average Packet Size in Byte*/\n+#define I40E_PACKET_AVERAGE_SIZE 128\n+\n /* Mask of PF interrupt causes */\n #define I40E_PFINT_ICR0_ENA_MASK ( \\\n \t\tI40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \\\n@@ -145,6 +166,8 @@ static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,\n static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);\n static int i40e_dev_led_on(struct rte_eth_dev *dev);\n static int i40e_dev_led_off(struct rte_eth_dev *dev);\n+static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_fc_conf *fc_conf);\n static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,\n@@ -272,6 +295,7 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.tx_queue_release = i40e_dev_tx_queue_release,\n \t.dev_led_on = i40e_dev_led_on,\n \t.dev_led_off = i40e_dev_led_off,\n+\t.flow_ctrl_get = i40e_flow_ctrl_get,\n \t.flow_ctrl_set = i40e_flow_ctrl_set,\n \t.priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,\n \t.mac_addr_add = i40e_macaddr_add,\n@@ -1782,12 +1806,148 @@ i40e_dev_led_off(struct rte_eth_dev *dev)\n }\n \n static int\n-i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,\n-\t\t __rte_unused struct rte_eth_fc_conf *fc_conf)\n+i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n {\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\n+\tfc_conf->pause_time = pf->fc_conf.pause_time;\n+\tfc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];\n+\tfc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];\n+\n+\t /* Return current mode according to actual setting*/\n+\tswitch (hw->fc.current_mode) {\n+\tcase I40E_FC_FULL:\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\t\tbreak;\n+\tcase I40E_FC_TX_PAUSE:\n+\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n+\t\tbreak;\n+\tcase I40E_FC_RX_PAUSE:\n+\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n+\t\tbreak;\n+\tcase I40E_FC_NONE:\n+\tdefault:\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\t};\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tuint32_t mflcn_reg, fctrl_reg, reg;\n+\tuint32_t max_high_water;\n+\tuint8_t i, aq_failure;\n+\tint err;\n+\tstruct i40e_hw *hw;\n+\tstruct i40e_pf *pf;\n+\tenum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {\n+\t\t[RTE_FC_NONE] = I40E_FC_NONE,\n+\t\t[RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,\n+\t\t[RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,\n+\t\t[RTE_FC_FULL] = I40E_FC_FULL\n+\t};\n+\n+\t/* high_water field in the rte_eth_fc_conf using the kilobytes unit */\n+\n+\tmax_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;\n+\tif ((fc_conf->high_water > max_high_water) ||\n+\t\t\t(fc_conf->high_water < fc_conf->low_water)) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid high/low water setup value in KB, \"\n+\t\t\t\"High_water must <= %d.\", max_high_water);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tpf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\thw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];\n+\n+\tpf->fc_conf.pause_time = fc_conf->pause_time;\n+\tpf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;\n+\tpf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n-\treturn -ENOSYS;\n+\t/* All the link flow control related enable/disable register\n+\t * configuration is handle by the F/W\n+\t */\n+\terr = i40e_set_fc(hw, &aq_failure, true);\n+\tif (err < 0)\n+\t\treturn -ENOSYS;\n+\n+\tif (i40e_is_40G_device(hw->device_id)) {\n+\t\t/* Configure flow control refresh threshold,\n+\t\t * the value for stat_tx_pause_refresh_timer[8]\n+\t\t * is used for global pause operation.\n+\t\t */\n+\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\t I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),\n+\t\t\t pf->fc_conf.pause_time);\n+\n+\t\t/* configure the timer value included in transmitted pause\n+\t\t * frame,\n+\t\t * the value for stat_tx_pause_quanta[8] is used for global\n+\t\t * pause operation\n+\t\t */\n+\t\tI40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),\n+\t\t\t pf->fc_conf.pause_time);\n+\n+\t\tfctrl_reg = I40E_READ_REG(hw,\n+\t\t\t\t\t I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);\n+\n+\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n+\t\t\tfctrl_reg |= I40E_PRTMAC_FWD_CTRL;\n+\t\telse\n+\t\t\tfctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,\n+\t\t\t fctrl_reg);\n+\t} else {\n+\t\t/* Configure pause time (2 TCs per register) */\n+\t\treg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;\n+\t\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)\n+\t\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);\n+\n+\t\t/* Configure flow control refresh threshold value */\n+\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,\n+\t\t\t pf->fc_conf.pause_time / 2);\n+\n+\t\tmflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);\n+\n+\t\t/* set or clear MFLCN.PMCF & MFLCN.DPF bits\n+\t\t *depending on configuration\n+\t\t */\n+\t\tif (fc_conf->mac_ctrl_frame_fwd != 0) {\n+\t\t\tmflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;\n+\t\t\tmflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;\n+\t\t} else {\n+\t\t\tmflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;\n+\t\t\tmflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;\n+\t\t}\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);\n+\t}\n+\n+\t/* config the water marker both based on the packets and bytes */\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_PHW,\n+\t\t (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_PLW,\n+\t\t (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_GHW,\n+\t\t pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t << I40E_KILOSHIFT);\n+\tI40E_WRITE_REG(hw, I40E_GLRPB_GLW,\n+\t\t pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]\n+\t\t << I40E_KILOSHIFT);\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n }\n \n static int\n@@ -2247,6 +2407,10 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev)\n \t\tPMD_INIT_LOG(ERR, \"HW configuration doesn't support SRIOV\");\n \t\treturn -EINVAL;\n \t}\n+\t/* Add the parameter init for LFC */\n+\tpf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;\n+\tpf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;\n+\tpf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;\n \n \tpf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;\n \tpf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 6185657..8707a98 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -282,6 +282,17 @@ struct i40e_pf_vf {\n };\n \n /*\n+ * Structure to store private data for flow control.\n+ */\n+struct i40e_fc_conf {\n+\tuint16_t pause_time; /* Flow control pause timer */\n+\t/* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */\n+\tuint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];\n+\t/* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */\n+\tuint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];\n+};\n+\n+/*\n * Structure to store private data for VMDQ instance\n */\n struct i40e_vmdq_info {\n@@ -385,6 +396,7 @@ struct i40e_pf {\n \tstruct i40e_vmdq_info *vmdq;\n \n \tstruct i40e_fdir_info fdir; /* flow director info */\n+\tstruct i40e_fc_conf fc_conf; /* Flow control conf */\n \tstruct i40e_mirror_rule_list mirror_list;\n \tuint16_t nb_mirror_rule; /* The number of mirror rules */\n };\n", "prefixes": [ "dpdk-dev", "v3" ] }