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GET /api/patches/82610/?format=api
{ "id": 82610, "url": "http://patches.dpdk.org/api/patches/82610/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201028095935.27855-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201028095935.27855-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201028095935.27855-1-getelson@nvidia.com", "date": "2020-10-28T09:59:34", "name": "[1/2] drivers/net/mlx5: fix representor interrupts handler", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e88dfe8d76a5c9f75a1753c7434fbc539ba3c4c3", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201028095935.27855-1-getelson@nvidia.com/mbox/", "series": [ { "id": 13414, "url": "http://patches.dpdk.org/api/series/13414/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13414", "date": "2020-10-28T09:59:34", "name": "[1/2] drivers/net/mlx5: fix representor interrupts handler", "version": 1, "mbox": "http://patches.dpdk.org/series/13414/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/82610/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/82610/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0BC38A04DD;\n\tWed, 28 Oct 2020 11:00:07 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3B86FC954;\n\tWed, 28 Oct 2020 11:00:05 +0100 (CET)", "from hqnvemgate24.nvidia.com (hqnvemgate24.nvidia.com\n [216.228.121.143]) by dpdk.org (Postfix) with ESMTP id F07C4C92C\n for <dev@dpdk.org>; Wed, 28 Oct 2020 11:00:01 +0100 (CET)", "from hqmail.nvidia.com (Not Verified[216.228.121.13]) by\n hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA)\n id <B5f9941270002>; Wed, 28 Oct 2020 03:00:07 -0700", "from nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13)\n with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n Wed, 28 Oct 2020 09:59:51 +0000" ], "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Shahaf Shuler\n <shahafs@nvidia.com>, Adrien Mazarguil <adrien.mazarguil@6wind.com>, \"Xueming\n Li\" <xuemingl@mellanox.com>", "Date": "Wed, 28 Oct 2020 11:59:34 +0200", "Message-ID": "<20201028095935.27855-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.28.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "quoted-printable", "Content-Type": "text/plain", "X-Originating-IP": "[10.124.1.5]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n t=1603879207; bh=S5/HHly3ORR0/HwxVeAGkAQhZIIGTSoyMVGMxiOQ9O0=;\n h=From:To:CC:Subject:Date:Message-ID:X-Mailer:MIME-Version:\n Content-Transfer-Encoding:Content-Type:X-Originating-IP:\n X-ClientProxiedBy;\n b=JUoMWOM0LbOTCgW8sNwzmqAF6PJ8F1ZDmdkYSEY2dk/OZeF8LEIMl7PLIAIPUVFxD\n gX8wz07k//NMRfHt0u2XApKqGYtDsmDv46ktJ9jeJP6Z7+3UPBnNGl6XlLOawikC6y\n /YG98HA0xAVajWul88moETznTwSm5ac9QHOq2tckN1HluoXtu83NgWRzE/8WstfbLo\n o+le/larJD3CBrHBy3VHjqDMpfeVLqTR/BypDsOaN6qq8KJncAhrQQGuua7gZ8PG/i\n WqZ2eTez9+0FHlLI13rh949prHzuqC+W2Moe/qSS2B9hO4y7UyTEdKIlA1dyZbJ67A\n QQ/XCjLGCgJAw==", "Subject": "[dpdk-dev] [PATCH 1/2] drivers/net/mlx5: fix representor interrupts\n\thandler", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Representor is a port in DPDK that is connected to a VF in such a way\nthat assuming there are no offload flows, each packet that is sent\nfrom the VF will be received by the corresponding representor. While\neach packet that is sent to a representor will be received by the VF.\nThis is very useful in case of SRIOV mode, where the first packet that\nis sent by the VF will be received by the DPDK application which will\ndecide if this flow should be offloaded to the E-Switch.\n\nRepresentor shares interrupts handler with host PF over the PCI\naddress. Therefore after PF completes it's interrupts handler\ninitialization no additional actions required for representor.\n\nFixes: 26c08b979d26 (\"net/mlx5: add port representor awareness\")\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 8d05315e61..df8542f7db 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -902,6 +902,11 @@ mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)\n \tunsigned int count = 0;\n \tstruct rte_intr_handle *intr_handle = dev->intr_handle;\n \n+\t/**\n+\t * representor shares dev->intr_handle with PF\n+\t */\n+\tif (priv->representor)\n+\t\treturn 0;\n \tif (!dev->data->dev_conf.intr_conf.rxq)\n \t\treturn 0;\n \tmlx5_rx_intr_vec_disable(dev);\n@@ -982,6 +987,11 @@ mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)\n \tunsigned int rxqs_n = priv->rxqs_n;\n \tunsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);\n \n+\t/**\n+\t * representor shares dev->intr_handle with PF\n+\t */\n+\tif (priv->representor)\n+\t\treturn;\n \tif (!dev->data->dev_conf.intr_conf.rxq)\n \t\treturn;\n \tif (!intr_handle->intr_vec)\n", "prefixes": [ "1/2" ] }