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GET /api/patches/82358/?format=api
{ "id": 82358, "url": "http://patches.dpdk.org/api/patches/82358/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-2-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027152824.15232-2-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027152824.15232-2-akozyrev@nvidia.com", "date": "2020-10-27T15:28:21", "name": "[1/4] common/mlx5: use C11 atomics for memory allocation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "321b4268b9a93707cbc162a9a6b40836725d6e36", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-2-akozyrev@nvidia.com/mbox/", "series": [ { "id": 13387, "url": "http://patches.dpdk.org/api/series/13387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13387", "date": "2020-10-27T15:28:20", "name": "net/mlx5: use C11 atomic builtins", "version": 1, "mbox": "http://patches.dpdk.org/series/13387/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/82358/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/82358/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E73EEA04B5;\n\tTue, 27 Oct 2020 16:30:07 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DA301BE4B;\n\tTue, 27 Oct 2020 16:28:46 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 92DCB6A1B\n for <dev@dpdk.org>; Tue, 27 Oct 2020 16:28:34 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n akozyrev@nvidia.com) with SMTP; 27 Oct 2020 17:28:28 +0200", "from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RFSSeb029461;\n Tue, 27 Oct 2020 17:28:28 +0200" ], "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "dev@dpdk.org", "Cc": "rasland@nvidia.com, matan@nvidia.com, viacheslavo@nvidia.com", "Date": "Tue, 27 Oct 2020 15:28:21 +0000", "Message-Id": "<20201027152824.15232-2-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.24.1", "In-Reply-To": "<20201027152824.15232-1-akozyrev@nvidia.com>", "References": "<20201027152824.15232-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 1/4] common/mlx5: use C11 atomics for memory\n\tallocation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The rte_atomic API is deprecated and needs to be replaced with\nC11 atomic builtins. Use the relaxed ordering for mlx5 mallocs.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_malloc.c | 91 ++++++++++++++++---------------\n 1 file changed, 47 insertions(+), 44 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_malloc.c b/drivers/common/mlx5/mlx5_malloc.c\nindex 44899717e0..f64c15fceb 100644\n--- a/drivers/common/mlx5/mlx5_malloc.c\n+++ b/drivers/common/mlx5/mlx5_malloc.c\n@@ -8,8 +8,6 @@\n #include <stdbool.h>\n #include <string.h>\n \n-#include <rte_atomic.h>\n-\n #include \"mlx5_common_utils.h\"\n #include \"mlx5_malloc.h\"\n \n@@ -17,27 +15,24 @@ struct mlx5_sys_mem {\n \tuint32_t init:1; /* Memory allocator initialized. */\n \tuint32_t enable:1; /* System memory select. */\n \tuint32_t reserve:30; /* Reserve. */\n-\tunion {\n-\t\tstruct rte_memseg_list *last_msl;\n-\t\trte_atomic64_t a64_last_msl;\n-\t};\n+\tstruct rte_memseg_list *last_msl;\n \t/* last allocated rte memory memseg list. */\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\trte_atomic64_t malloc_sys;\n+\tuint64_t malloc_sys;\n \t/* Memory allocated from system count. */\n-\trte_atomic64_t malloc_rte;\n+\tuint64_t malloc_rte;\n \t/* Memory allocated from hugepage count. */\n-\trte_atomic64_t realloc_sys;\n+\tuint64_t realloc_sys;\n \t/* Memory reallocate from system count. */\n-\trte_atomic64_t realloc_rte;\n+\tuint64_t realloc_rte;\n \t/* Memory reallocate from hugepage count. */\n-\trte_atomic64_t free_sys;\n+\tuint64_t free_sys;\n \t/* Memory free to system count. */\n-\trte_atomic64_t free_rte;\n+\tuint64_t free_rte;\n \t/* Memory free to hugepage count. */\n-\trte_atomic64_t msl_miss;\n+\tuint64_t msl_miss;\n \t/* MSL miss count. */\n-\trte_atomic64_t msl_update;\n+\tuint64_t msl_update;\n \t/* MSL update count. */\n #endif\n };\n@@ -47,14 +42,14 @@ static struct mlx5_sys_mem mlx5_sys_mem = {\n \t.init = 0,\n \t.enable = 0,\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\t.malloc_sys = RTE_ATOMIC64_INIT(0),\n-\t.malloc_rte = RTE_ATOMIC64_INIT(0),\n-\t.realloc_sys = RTE_ATOMIC64_INIT(0),\n-\t.realloc_rte = RTE_ATOMIC64_INIT(0),\n-\t.free_sys = RTE_ATOMIC64_INIT(0),\n-\t.free_rte = RTE_ATOMIC64_INIT(0),\n-\t.msl_miss = RTE_ATOMIC64_INIT(0),\n-\t.msl_update = RTE_ATOMIC64_INIT(0),\n+\t.malloc_sys = 0,\n+\t.malloc_rte = 0,\n+\t.realloc_sys = 0,\n+\t.realloc_rte = 0,\n+\t.free_sys = 0,\n+\t.free_rte = 0,\n+\t.msl_miss = 0,\n+\t.msl_update = 0,\n #endif\n };\n \n@@ -97,12 +92,14 @@ mlx5_mem_update_msl(void *addr)\n \t * different with the cached msl.\n \t */\n \tif (addr && !mlx5_mem_check_msl(addr,\n-\t (struct rte_memseg_list *)(uintptr_t)rte_atomic64_read\n-\t (&mlx5_sys_mem.a64_last_msl))) {\n-\t\trte_atomic64_set(&mlx5_sys_mem.a64_last_msl,\n-\t\t\t(int64_t)(uintptr_t)rte_mem_virt2memseg_list(addr));\n+\t (struct rte_memseg_list *)__atomic_load_n\n+\t (&mlx5_sys_mem.last_msl, __ATOMIC_RELAXED))) {\n+\t\t__atomic_store_n(&mlx5_sys_mem.last_msl,\n+\t\t\trte_mem_virt2memseg_list(addr),\n+\t\t\t__ATOMIC_RELAXED);\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\t\trte_atomic64_inc(&mlx5_sys_mem.msl_update);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem.msl_update, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \t}\n }\n@@ -123,12 +120,12 @@ mlx5_mem_is_rte(void *addr)\n \t * Check if the last cache msl matches. Drop to slow path\n \t * to check if the memory belongs to rte memory.\n \t */\n-\tif (!mlx5_mem_check_msl(addr, (struct rte_memseg_list *)(uintptr_t)\n-\t rte_atomic64_read(&mlx5_sys_mem.a64_last_msl))) {\n+\tif (!mlx5_mem_check_msl(addr, (struct rte_memseg_list *)\n+\t __atomic_load_n(&mlx5_sys_mem.last_msl, __ATOMIC_RELAXED))) {\n \t\tif (!rte_mem_virt2memseg_list(addr))\n \t\t\treturn false;\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\t\trte_atomic64_inc(&mlx5_sys_mem.msl_miss);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem.msl_miss, 1, __ATOMIC_RELAXED);\n #endif\n \t}\n \treturn true;\n@@ -190,7 +187,8 @@ mlx5_malloc(uint32_t flags, size_t size, unsigned int align, int socket)\n \t\tmlx5_mem_update_msl(addr);\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n \t\tif (addr)\n-\t\t\trte_atomic64_inc(&mlx5_sys_mem.malloc_rte);\n+\t\t\t__atomic_add_fetch(&mlx5_sys_mem->malloc_rte, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \t\treturn addr;\n \t}\n@@ -203,7 +201,8 @@ mlx5_malloc(uint32_t flags, size_t size, unsigned int align, int socket)\n \t\taddr = malloc(size);\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n \tif (addr)\n-\t\trte_atomic64_inc(&mlx5_sys_mem.malloc_sys);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem->malloc_sys, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \treturn addr;\n }\n@@ -236,7 +235,8 @@ mlx5_realloc(void *addr, uint32_t flags, size_t size, unsigned int align,\n \t\tmlx5_mem_update_msl(new_addr);\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n \t\tif (new_addr)\n-\t\t\trte_atomic64_inc(&mlx5_sys_mem.realloc_rte);\n+\t\t\t__atomic_add_fetch(&mlx5_sys_mem->realloc_rte, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \t\treturn new_addr;\n \t}\n@@ -248,7 +248,8 @@ mlx5_realloc(void *addr, uint32_t flags, size_t size, unsigned int align,\n \tnew_addr = realloc(addr, size);\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n \tif (new_addr)\n-\t\trte_atomic64_inc(&mlx5_sys_mem.realloc_sys);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem->realloc_sys, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \treturn new_addr;\n }\n@@ -260,12 +261,14 @@ mlx5_free(void *addr)\n \t\treturn;\n \tif (!mlx5_mem_is_rte(addr)) {\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\t\trte_atomic64_inc(&mlx5_sys_mem.free_sys);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem->free_sys, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \t\tfree(addr);\n \t} else {\n #ifdef RTE_LIBRTE_MLX5_DEBUG\n-\t\trte_atomic64_inc(&mlx5_sys_mem.free_rte);\n+\t\t__atomic_add_fetch(&mlx5_sys_mem->free_rte, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n #endif\n \t\trte_free(addr);\n \t}\n@@ -279,14 +282,14 @@ mlx5_memory_stat_dump(void)\n \t\t\" free:%\"PRIi64\"\\nRTE memory malloc:%\"PRIi64\",\"\n \t\t\" realloc:%\"PRIi64\", free:%\"PRIi64\"\\nMSL miss:%\"PRIi64\",\"\n \t\t\" update:%\"PRIi64\"\",\n-\t\trte_atomic64_read(&mlx5_sys_mem.malloc_sys),\n-\t\trte_atomic64_read(&mlx5_sys_mem.realloc_sys),\n-\t\trte_atomic64_read(&mlx5_sys_mem.free_sys),\n-\t\trte_atomic64_read(&mlx5_sys_mem.malloc_rte),\n-\t\trte_atomic64_read(&mlx5_sys_mem.realloc_rte),\n-\t\trte_atomic64_read(&mlx5_sys_mem.free_rte),\n-\t\trte_atomic64_read(&mlx5_sys_mem.msl_miss),\n-\t\trte_atomic64_read(&mlx5_sys_mem.msl_update));\n+\t\t__atomic_load_n(&mlx5_sys_mem.malloc_sys, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.realloc_sys, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.free_sys, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.malloc_rte, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.realloc_rte, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.free_rte, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.msl_miss, __ATOMIC_RELAXED),\n+\t\t__atomic_load_n(&mlx5_sys_mem.msl_update, __ATOMIC_RELAXED));\n #endif\n }\n \n", "prefixes": [ "1/4" ] }