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GET /api/patches/82356/?format=api
{ "id": 82356, "url": "http://patches.dpdk.org/api/patches/82356/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-5-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027152824.15232-5-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027152824.15232-5-akozyrev@nvidia.com", "date": "2020-10-27T15:28:24", "name": "[4/4] net/mlx5: use C11 atomics for RTE flow tables", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3bd9595921ea9a1c7ab68b7078afdd93f11e5499", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-5-akozyrev@nvidia.com/mbox/", "series": [ { "id": 13387, "url": "http://patches.dpdk.org/api/series/13387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13387", "date": "2020-10-27T15:28:20", "name": "net/mlx5: use C11 atomic builtins", "version": 1, "mbox": "http://patches.dpdk.org/series/13387/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/82356/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/82356/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8E228A04B5;\n\tTue, 27 Oct 2020 16:29:19 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A01F472EE;\n\tTue, 27 Oct 2020 16:28:39 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A99146CAB\n for <dev@dpdk.org>; Tue, 27 Oct 2020 16:28:34 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n akozyrev@nvidia.com) with SMTP; 27 Oct 2020 17:28:29 +0200", "from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RFSSee029461;\n Tue, 27 Oct 2020 17:28:29 +0200" ], "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "dev@dpdk.org", "Cc": "rasland@nvidia.com, matan@nvidia.com, viacheslavo@nvidia.com", "Date": "Tue, 27 Oct 2020 15:28:24 +0000", "Message-Id": "<20201027152824.15232-5-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.24.1", "In-Reply-To": "<20201027152824.15232-1-akozyrev@nvidia.com>", "References": "<20201027152824.15232-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 4/4] net/mlx5: use C11 atomics for RTE flow tables", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The rte_atomic API is deprecated and needs to be replaced with\nC11 atomic builtins. Use the relaxed ordering for RTE flow tables.\nEnforce Acquire/Release model for managing DevX pools.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 9 +--\n drivers/net/mlx5/mlx5_flow.h | 15 ++--\n drivers/net/mlx5/mlx5_flow_dv.c | 123 ++++++++++++++++++--------------\n 3 files changed, 78 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0141c0670e..1bd8cd4b63 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -402,10 +402,7 @@ TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);\n struct mlx5_flow_counter_pool {\n \tTAILQ_ENTRY(mlx5_flow_counter_pool) next;\n \tstruct mlx5_counters counters[2]; /* Free counter list. */\n-\tunion {\n-\t\tstruct mlx5_devx_obj *min_dcs;\n-\t\trte_atomic64_t a64_dcs;\n-\t};\n+\tstruct mlx5_devx_obj *min_dcs;\n \t/* The devx object of the minimum counter ID. */\n \tuint64_t time_of_last_age_check;\n \t/* System time (from rte_rdtsc()) read in the last aging check. */\n@@ -464,7 +461,7 @@ struct mlx5_flow_counter_mng {\n /* Default miss action resource structure. */\n struct mlx5_flow_default_miss_resource {\n \tvoid *action; /* Pointer to the rdma-core action. */\n-\trte_atomic32_t refcnt; /* Default miss action reference counter. */\n+\tuint32_t refcnt; /* Default miss action reference counter. */\n };\n \n #define MLX5_AGE_EVENT_NEW\t\t1\n@@ -515,7 +512,7 @@ union mlx5_flow_tbl_key {\n /* Table structure. */\n struct mlx5_flow_tbl_resource {\n \tvoid *obj; /**< Pointer to DR table object. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n };\n \n #define MLX5_MAX_TABLES UINT16_MAX\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 8b5a93f173..ce315758ad 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -11,7 +11,6 @@\n #include <stdint.h>\n #include <string.h>\n \n-#include <rte_atomic.h>\n #include <rte_alarm.h>\n #include <rte_mtr.h>\n \n@@ -396,7 +395,7 @@ struct mlx5_flow_dv_matcher {\n \t/**< Pointer to the next element. */\n \tstruct mlx5_flow_tbl_resource *tbl;\n \t/**< Pointer to the table(group) the matcher associated with. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tvoid *matcher_object; /**< Pointer to DV matcher */\n \tuint16_t crc; /**< CRC of key. */\n \tuint16_t priority; /**< Priority of matcher. */\n@@ -421,7 +420,7 @@ union mlx5_flow_encap_decap_key {\n struct mlx5_flow_dv_encap_decap_resource {\n \tstruct mlx5_hlist_entry entry;\n \t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tvoid *action;\n \t/**< Encap/decap action object. */\n \tuint8_t buf[MLX5_ENCAP_MAX_LEN];\n@@ -438,7 +437,7 @@ struct mlx5_flow_dv_tag_resource {\n \t/**< hash list entry for tag resource, tag value as the key. */\n \tvoid *action;\n \t/**< Tag action object. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tuint32_t idx; /**< Index for the index memory pool. */\n };\n \n@@ -459,7 +458,7 @@ struct mlx5_flow_dv_tag_resource {\n struct mlx5_flow_dv_modify_hdr_resource {\n \tstruct mlx5_hlist_entry entry;\n \t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tvoid *action;\n \t/**< Modify header action object. */\n \tuint8_t ft_type; /**< Flow table type, Rx or Tx. */\n@@ -482,7 +481,7 @@ union mlx5_flow_modify_hdr_key {\n \n /* Jump action resource structure. */\n struct mlx5_flow_dv_jump_tbl_resource {\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tuint8_t ft_type; /**< Flow table type, Rx or Tx. */\n \tvoid *action; /**< Pointer to the rdma core action. */\n };\n@@ -491,7 +490,7 @@ struct mlx5_flow_dv_jump_tbl_resource {\n struct mlx5_flow_dv_port_id_action_resource {\n \tILIST_ENTRY(uint32_t)next;\n \t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tvoid *action;\n \t/**< Action object. */\n \tuint32_t port_id; /**< Port ID value. */\n@@ -501,7 +500,7 @@ struct mlx5_flow_dv_port_id_action_resource {\n struct mlx5_flow_dv_push_vlan_action_resource {\n \tILIST_ENTRY(uint32_t)next;\n \t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \tvoid *action; /**< Action object. */\n \tuint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */\n \trte_be32_t vlan_tag; /**< VLAN tag value. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 3f1ccf8fe0..caa85e87a4 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2873,8 +2873,10 @@ flow_dv_encap_decap_resource_register\n \t\t\tstruct mlx5_flow_dv_encap_decap_resource, entry);\n \t\tDRV_LOG(DEBUG, \"encap/decap resource %p: refcnt %d++\",\n \t\t\t(void *)cache_resource,\n-\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\t\trte_atomic32_inc(&cache_resource->refcnt);\n+\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t__ATOMIC_RELAXED));\n+\t\t__atomic_fetch_add(&cache_resource->refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\tdev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;\n \t\tdev_flow->dv.encap_decap = cache_resource;\n \t\treturn 0;\n@@ -2897,8 +2899,7 @@ flow_dv_encap_decap_resource_register\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL, \"cannot create action\");\n \t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);\n \tif (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,\n \t\t\t\t flow_dv_encap_decap_resource_match,\n \t\t\t\t (void *)cache_resource)) {\n@@ -2913,7 +2914,7 @@ flow_dv_encap_decap_resource_register\n \tdev_flow->dv.encap_decap = cache_resource;\n \tDRV_LOG(DEBUG, \"new encap/decap resource %p: refcnt %d++\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n \n@@ -2944,7 +2945,7 @@ flow_dv_jump_tbl_resource_register\n \tint cnt, ret;\n \n \tMLX5_ASSERT(tbl);\n-\tcnt = rte_atomic32_read(&tbl_data->jump.refcnt);\n+\tcnt = __atomic_load_n(&tbl_data->jump.refcnt, __ATOMIC_ACQUIRE);\n \tif (!cnt) {\n \t\tret = mlx5_flow_os_create_flow_action_dest_flow_tbl\n \t\t\t\t(tbl->obj, &tbl_data->jump.action);\n@@ -2961,7 +2962,7 @@ flow_dv_jump_tbl_resource_register\n \t\tDRV_LOG(DEBUG, \"existed jump table resource %p: refcnt %d++\",\n \t\t\t(void *)&tbl_data->jump, cnt);\n \t}\n-\trte_atomic32_inc(&tbl_data->jump.refcnt);\n+\t__atomic_fetch_add(&tbl_data->jump.refcnt, 1, __ATOMIC_RELEASE);\n \tdev_flow->handle->rix_jump = tbl_data->idx;\n \tdev_flow->dv.jump = &tbl_data->jump;\n \treturn 0;\n@@ -2986,7 +2987,7 @@ flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tstruct mlx5_flow_default_miss_resource *cache_resource =\n \t\t\t&sh->default_miss;\n-\tint cnt = rte_atomic32_read(&cache_resource->refcnt);\n+\tint cnt = __atomic_load_n(&cache_resource->refcnt, __ATOMIC_ACQUIRE);\n \n \tif (!cnt) {\n \t\tMLX5_ASSERT(cache_resource->action);\n@@ -2999,7 +3000,7 @@ flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,\n \t\tDRV_LOG(DEBUG, \"new default miss resource %p: refcnt %d++\",\n \t\t\t\t(void *)cache_resource->action, cnt);\n \t}\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_fetch_add(&cache_resource->refcnt, 1, __ATOMIC_RELEASE);\n \treturn 0;\n }\n \n@@ -3038,8 +3039,10 @@ flow_dv_port_id_action_resource_register\n \t\t\tDRV_LOG(DEBUG, \"port id action resource resource %p: \"\n \t\t\t\t\"refcnt %d++\",\n \t\t\t\t(void *)cache_resource,\n-\t\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\t\t\trte_atomic32_inc(&cache_resource->refcnt);\n+\t\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t\t__ATOMIC_RELAXED));\n+\t\t\t__atomic_fetch_add(&cache_resource->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t\tdev_flow->handle->rix_port_id_action = idx;\n \t\t\tdev_flow->dv.port_id_action = cache_resource;\n \t\t\treturn 0;\n@@ -3062,15 +3065,14 @@ flow_dv_port_id_action_resource_register\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL, \"cannot create action\");\n \t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);\n \tILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,\n \t\t dev_flow->handle->rix_port_id_action, cache_resource,\n \t\t next);\n \tdev_flow->dv.port_id_action = cache_resource;\n \tDRV_LOG(DEBUG, \"new port id action resource %p: refcnt %d++\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n \n@@ -3111,8 +3113,10 @@ flow_dv_push_vlan_action_resource_register\n \t\t\tDRV_LOG(DEBUG, \"push-VLAN action resource resource %p: \"\n \t\t\t\t\"refcnt %d++\",\n \t\t\t\t(void *)cache_resource,\n-\t\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\t\t\trte_atomic32_inc(&cache_resource->refcnt);\n+\t\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t\t__ATOMIC_RELAXED));\n+\t\t\t__atomic_fetch_add(&cache_resource->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t\tdev_flow->handle->dvh.rix_push_vlan = idx;\n \t\t\tdev_flow->dv.push_vlan_res = cache_resource;\n \t\t\treturn 0;\n@@ -3141,8 +3145,7 @@ flow_dv_push_vlan_action_resource_register\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL, \"cannot create action\");\n \t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);\n \tILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],\n \t\t &sh->push_vlan_action_list,\n \t\t dev_flow->handle->dvh.rix_push_vlan,\n@@ -3150,7 +3153,7 @@ flow_dv_push_vlan_action_resource_register\n \tdev_flow->dv.push_vlan_res = cache_resource;\n \tDRV_LOG(DEBUG, \"new push vlan action resource %p: refcnt %d++\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n /**\n@@ -4550,8 +4553,10 @@ flow_dv_modify_hdr_resource_register\n \t\t\t\t\tentry);\n \t\tDRV_LOG(DEBUG, \"modify-header resource %p: refcnt %d++\",\n \t\t\t(void *)cache_resource,\n-\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\t\trte_atomic32_inc(&cache_resource->refcnt);\n+\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t__ATOMIC_RELAXED));\n+\t\t__atomic_fetch_add(&cache_resource->refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\tdev_flow->handle->dvh.modify_hdr = cache_resource;\n \t\treturn 0;\n \n@@ -4575,8 +4580,7 @@ flow_dv_modify_hdr_resource_register\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL, \"cannot create action\");\n \t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);\n \tif (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,\n \t\t\t\t flow_dv_modify_hdr_resource_match,\n \t\t\t\t (void *)cache_resource)) {\n@@ -4590,7 +4594,7 @@ flow_dv_modify_hdr_resource_register\n \tdev_flow->handle->dvh.modify_hdr = cache_resource;\n \tDRV_LOG(DEBUG, \"new modify-header resource %p: refcnt %d++\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n \n@@ -8021,7 +8025,7 @@ flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n \t\ttbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,\n \t\t\t\t\tentry);\n \t\ttbl = &tbl_data->tbl;\n-\t\trte_atomic32_inc(&tbl->refcnt);\n+\t\t__atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);\n \t\treturn tbl;\n \t}\n \ttbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);\n@@ -8056,9 +8060,9 @@ flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n \t * No multi-threads now, but still better to initialize the reference\n \t * count before insert it into the hash list.\n \t */\n-\trte_atomic32_init(&tbl->refcnt);\n+\t__atomic_store_n(&tbl->refcnt, 0, __ATOMIC_RELAXED);\n \t/* Jump action reference count is initialized here. */\n-\trte_atomic32_init(&tbl_data->jump.refcnt);\n+\t__atomic_store_n(&tbl_data->jump.refcnt, 0, __ATOMIC_RELAXED);\n \tpos->key = table_key.v64;\n \tret = mlx5_hlist_insert(sh->flow_tbls, pos);\n \tif (ret < 0) {\n@@ -8068,7 +8072,7 @@ flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n \t\tmlx5_flow_os_destroy_flow_tbl(tbl->obj);\n \t\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);\n \t}\n-\trte_atomic32_inc(&tbl->refcnt);\n+\t__atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);\n \treturn tbl;\n }\n \n@@ -8094,7 +8098,7 @@ flow_dv_tbl_resource_release(struct rte_eth_dev *dev,\n \n \tif (!tbl)\n \t\treturn 0;\n-\tif (rte_atomic32_dec_and_test(&tbl->refcnt)) {\n+\tif (__atomic_sub_fetch(&tbl->refcnt, 1, __ATOMIC_RELAXED) == 0) {\n \t\tstruct mlx5_hlist_entry *pos = &tbl_data->entry;\n \n \t\tmlx5_flow_os_destroy_flow_tbl(tbl->obj);\n@@ -8197,8 +8201,10 @@ flow_dv_matcher_register(struct rte_eth_dev *dev,\n \t\t\t\tcache_matcher->priority,\n \t\t\t\tkey->direction ? \"tx\" : \"rx\",\n \t\t\t\t(void *)cache_matcher,\n-\t\t\t\trte_atomic32_read(&cache_matcher->refcnt));\n-\t\t\trte_atomic32_inc(&cache_matcher->refcnt);\n+\t\t\t\t__atomic_load_n(&cache_matcher->refcnt,\n+\t\t\t\t\t\t__ATOMIC_RELAXED));\n+\t\t\t__atomic_fetch_add(&cache_matcher->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t\tdev_flow->handle->dvh.matcher = cache_matcher;\n \t\t\t/* old matcher should not make the table ref++. */\n \t\t\tflow_dv_tbl_resource_release(dev, tbl);\n@@ -8233,16 +8239,15 @@ flow_dv_matcher_register(struct rte_eth_dev *dev,\n \t}\n \t/* Save the table information */\n \tcache_matcher->tbl = tbl;\n-\trte_atomic32_init(&cache_matcher->refcnt);\n \t/* only matcher ref++, table ref++ already done above in get API. */\n-\trte_atomic32_inc(&cache_matcher->refcnt);\n+\t__atomic_store_n(&cache_matcher->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);\n \tdev_flow->handle->dvh.matcher = cache_matcher;\n \tDRV_LOG(DEBUG, \"%s group %u priority %hd new %s matcher %p: refcnt %d\",\n \t\tkey->domain ? \"FDB\" : \"NIC\", key->table_id,\n \t\tcache_matcher->priority,\n \t\tkey->direction ? \"tx\" : \"rx\", (void *)cache_matcher,\n-\t\trte_atomic32_read(&cache_matcher->refcnt));\n+\t\t__atomic_load_n(&cache_matcher->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n \n@@ -8279,12 +8284,14 @@ flow_dv_tag_resource_register\n \tif (entry) {\n \t\tcache_resource = container_of\n \t\t\t(entry, struct mlx5_flow_dv_tag_resource, entry);\n-\t\trte_atomic32_inc(&cache_resource->refcnt);\n+\t\t__atomic_fetch_add(&cache_resource->refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\tdev_flow->handle->dvh.rix_tag = cache_resource->idx;\n \t\tdev_flow->dv.tag_resource = cache_resource;\n \t\tDRV_LOG(DEBUG, \"cached tag resource %p: refcnt now %d++\",\n \t\t\t(void *)cache_resource,\n-\t\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t__ATOMIC_RELAXED));\n \t\treturn 0;\n \t}\n \t/* Register new resource. */\n@@ -8303,8 +8310,7 @@ flow_dv_tag_resource_register\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t\t NULL, \"cannot create action\");\n \t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n+\t__atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);\n \tif (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {\n \t\tmlx5_flow_os_destroy_flow_action(cache_resource->action);\n \t\tmlx5_free(cache_resource);\n@@ -8315,7 +8321,7 @@ flow_dv_tag_resource_register\n \tdev_flow->dv.tag_resource = cache_resource;\n \tDRV_LOG(DEBUG, \"new tag resource %p: refcnt now %d++\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n \treturn 0;\n }\n \n@@ -8343,8 +8349,8 @@ flow_dv_tag_release(struct rte_eth_dev *dev,\n \t\treturn 0;\n \tDRV_LOG(DEBUG, \"port %u tag %p: refcnt %d--\",\n \t\tdev->data->port_id, (void *)tag,\n-\t\trte_atomic32_read(&tag->refcnt));\n-\tif (rte_atomic32_dec_and_test(&tag->refcnt)) {\n+\t\t__atomic_load_n(&tag->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&tag->refcnt, 1, __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action(tag->action));\n \t\tmlx5_hlist_remove(sh->tag_table, &tag->entry);\n \t\tDRV_LOG(DEBUG, \"port %u tag %p: removed\",\n@@ -10463,8 +10469,8 @@ flow_dv_matcher_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(matcher->matcher_object);\n \tDRV_LOG(DEBUG, \"port %u matcher %p: refcnt %d--\",\n \t\tdev->data->port_id, (void *)matcher,\n-\t\trte_atomic32_read(&matcher->refcnt));\n-\tif (rte_atomic32_dec_and_test(&matcher->refcnt)) {\n+\t\t__atomic_load_n(&matcher->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&matcher->refcnt, 1, __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_matcher\n \t\t\t (matcher->matcher_object));\n \t\tLIST_REMOVE(matcher, next);\n@@ -10504,8 +10510,9 @@ flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"encap/decap resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t\t(cache_resource->action));\n \t\tmlx5_hlist_remove(priv->sh->encaps_decaps,\n@@ -10545,8 +10552,9 @@ flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"jump table resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t\t(cache_resource->action));\n \t\t/* jump action memory free is inside the table release. */\n@@ -10577,8 +10585,10 @@ flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"default miss resource %p: refcnt %d--\",\n \t\t\t(void *)cache_resource->action,\n-\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t\t__atomic_load_n(&cache_resource->refcnt,\n+\t\t\t\t\t__ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_glue->destroy_flow_action\n \t\t\t\t(cache_resource->action));\n \t\tDRV_LOG(DEBUG, \"default miss resource %p: removed\",\n@@ -10610,8 +10620,9 @@ flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"modify-header resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t\t__ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t\t(cache_resource->action));\n \t\tmlx5_hlist_remove(priv->sh->modify_cmds,\n@@ -10650,8 +10661,9 @@ flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"port ID action resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t\t(cache_resource->action));\n \t\tILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],\n@@ -10691,8 +10703,9 @@ flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"push VLAN action resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\t__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));\n+\tif (__atomic_sub_fetch(&cache_resource->refcnt, 1,\n+\t\t\t __ATOMIC_RELAXED) == 0) {\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n \t\t\t\t\t\t(cache_resource->action));\n \t\tILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],\n", "prefixes": [ "4/4" ] }