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GET /api/patches/82355/?format=api
{ "id": 82355, "url": "http://patches.dpdk.org/api/patches/82355/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-4-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027152824.15232-4-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027152824.15232-4-akozyrev@nvidia.com", "date": "2020-10-27T15:28:23", "name": "[3/4] net/mlx5: use C11 atomics for RxQ/TxQ refcounts", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "becb4cdbc956907c5092b4609c95ce3b979a21ca", "submitter": { "id": 1873, "url": "http://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201027152824.15232-4-akozyrev@nvidia.com/mbox/", "series": [ { "id": 13387, "url": "http://patches.dpdk.org/api/series/13387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13387", "date": "2020-10-27T15:28:20", "name": "net/mlx5: use C11 atomic builtins", "version": 1, "mbox": "http://patches.dpdk.org/series/13387/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/82355/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/82355/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0316EA04B5;\n\tTue, 27 Oct 2020 16:28:58 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BD2D172DF;\n\tTue, 27 Oct 2020 16:28:37 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A51886CA9\n for <dev@dpdk.org>; Tue, 27 Oct 2020 16:28:34 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n akozyrev@nvidia.com) with SMTP; 27 Oct 2020 17:28:29 +0200", "from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RFSSed029461;\n Tue, 27 Oct 2020 17:28:28 +0200" ], "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "dev@dpdk.org", "Cc": "rasland@nvidia.com, matan@nvidia.com, viacheslavo@nvidia.com", "Date": "Tue, 27 Oct 2020 15:28:23 +0000", "Message-Id": "<20201027152824.15232-4-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.24.1", "In-Reply-To": "<20201027152824.15232-1-akozyrev@nvidia.com>", "References": "<20201027152824.15232-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 3/4] net/mlx5: use C11 atomics for RxQ/TxQ\n\trefcounts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The rte_atomic API is deprecated and needs to be replaced with\nC11 atomic builtins. Use the relaxed ordering for RxQ/TxQ refcounts.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 1 -\n drivers/net/mlx5/mlx5.c | 9 +++-----\n drivers/net/mlx5/mlx5.h | 6 +++---\n drivers/net/mlx5/mlx5_ethdev.c | 1 -\n drivers/net/mlx5/mlx5_flow_dv.c | 3 ++-\n drivers/net/mlx5/mlx5_rxq.c | 28 ++++++++++++-------------\n drivers/net/mlx5/mlx5_txq.c | 8 +++----\n 7 files changed, 26 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex 593b0d08ac..19b281925f 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -24,7 +24,6 @@\n #include <sys/un.h>\n #include <time.h>\n \n-#include <rte_atomic.h>\n #include <rte_ethdev_driver.h>\n #include <rte_bus_pci.h>\n #include <rte_mbuf.h>\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 91aaee3d8c..27c9c2abb6 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1232,8 +1232,7 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv)\n \terr = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);\n \tif (err)\n \t\tgoto error;\n-\trte_atomic32_init(&tbl_data->tbl.refcnt);\n-\trte_atomic32_inc(&tbl_data->tbl.refcnt);\n+\t__atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);\n \ttable_key.direction = 1;\n \ttbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,\n \t\t\t SOCKET_ID_ANY);\n@@ -1245,8 +1244,7 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv)\n \terr = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);\n \tif (err)\n \t\tgoto error;\n-\trte_atomic32_init(&tbl_data->tbl.refcnt);\n-\trte_atomic32_inc(&tbl_data->tbl.refcnt);\n+\t__atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);\n \ttable_key.direction = 0;\n \ttable_key.domain = 1;\n \ttbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,\n@@ -1259,8 +1257,7 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv)\n \terr = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);\n \tif (err)\n \t\tgoto error;\n-\trte_atomic32_init(&tbl_data->tbl.refcnt);\n-\trte_atomic32_inc(&tbl_data->tbl.refcnt);\n+\t__atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);\n \treturn err;\n error:\n \tmlx5_free_table_hash_list(priv);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 74298115fc..0141c0670e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -719,7 +719,7 @@ struct mlx5_rxq_obj {\n /* Indirection table. */\n struct mlx5_ind_table_obj {\n \tLIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */\n-\trte_atomic32_t refcnt; /* Reference counter. */\n+\tuint32_t refcnt; /* Reference counter. */\n \tRTE_STD_C11\n \tunion {\n \t\tvoid *ind_table; /**< Indirection table. */\n@@ -733,7 +733,7 @@ struct mlx5_ind_table_obj {\n __extension__\n struct mlx5_hrxq {\n \tILIST_ENTRY(uint32_t)next; /* Index to the next element. */\n-\trte_atomic32_t refcnt; /* Reference counter. */\n+\tuint32_t refcnt; /* Reference counter. */\n \tuint32_t shared:1; /* This object used in shared action. */\n \tstruct mlx5_ind_table_obj *ind_table; /* Indirection table. */\n \tRTE_STD_C11\n@@ -872,7 +872,7 @@ struct mlx5_priv {\n \t/* Indirection tables. */\n \tLIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;\n \t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n+\tuint32_t refcnt; /**< Reference counter. */\n \t/**< Verbs modify header action object. */\n \tuint8_t ft_type; /**< Flow table type, Rx or Tx. */\n \tuint8_t max_lro_msg_size;\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex fc04fc8224..8f39e84e08 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -10,7 +10,6 @@\n #include <stdlib.h>\n #include <errno.h>\n \n-#include <rte_atomic.h>\n #include <rte_ethdev_driver.h>\n #include <rte_bus_pci.h>\n #include <rte_mbuf.h>\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex dafe07f42e..3f1ccf8fe0 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -10283,7 +10283,8 @@ __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,\n \t\tif (hrxq_idx) {\n \t\t\t*hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],\n \t\t\t\t\t hrxq_idx);\n-\t\t\trte_atomic32_inc(&(*hrxq)->refcnt);\n+\t\t\t__atomic_fetch_add(&(*hrxq)->refcnt, 1,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \t\t}\n \t} else {\n \t\tstruct mlx5_flow_rss_desc *rss_desc =\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex ddd5df7c37..8d05315e61 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -461,7 +461,6 @@ mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)\n \t}\n \trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n \treturn (__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED) == 1);\n-\n }\n \n /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */\n@@ -1669,7 +1668,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \ttmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;\n #endif\n \ttmpl->rxq.idx = idx;\n-\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n error:\n@@ -1716,7 +1715,7 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \ttmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };\n \ttmpl->hairpin_conf = *hairpin_conf;\n \ttmpl->rxq.idx = idx;\n-\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n }\n@@ -1741,7 +1740,7 @@ mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)\n \n \tif (rxq_data) {\n \t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\t\t__atomic_add_fetch(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED);\n+\t\t__atomic_fetch_add(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED);\n \t}\n \treturn rxq_ctrl;\n }\n@@ -1916,7 +1915,7 @@ mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,\n \tif (ind_tbl) {\n \t\tunsigned int i;\n \n-\t\trte_atomic32_inc(&ind_tbl->refcnt);\n+\t\t__atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);\n \t\tfor (i = 0; i != ind_tbl->queues_n; ++i)\n \t\t\tmlx5_rxq_get(dev, ind_tbl->queues[i]);\n \t}\n@@ -1941,11 +1940,11 @@ mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunsigned int i;\n \n-\tif (rte_atomic32_dec_and_test(&ind_tbl->refcnt))\n+\tif (__atomic_sub_fetch(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED) == 0)\n \t\tpriv->obj_ops.ind_table_destroy(ind_tbl);\n \tfor (i = 0; i != ind_tbl->queues_n; ++i)\n \t\tclaim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));\n-\tif (!rte_atomic32_read(&ind_tbl->refcnt)) {\n+\tif (__atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED) == 0) {\n \t\tLIST_REMOVE(ind_tbl, next);\n \t\tmlx5_free(ind_tbl);\n \t\treturn 0;\n@@ -2019,7 +2018,7 @@ mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n \tret = priv->obj_ops.ind_table_new(dev, n, ind_tbl);\n \tif (ret < 0)\n \t\tgoto error;\n-\trte_atomic32_inc(&ind_tbl->refcnt);\n+\t__atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);\n \treturn ind_tbl;\n error:\n@@ -2078,7 +2077,7 @@ mlx5_hrxq_get(struct rte_eth_dev *dev,\n \t\t\tmlx5_ind_table_obj_release(dev, ind_tbl);\n \t\t\tcontinue;\n \t\t}\n-\t\trte_atomic32_inc(&hrxq->refcnt);\n+\t\t__atomic_fetch_add(&hrxq->refcnt, 1, __ATOMIC_RELAXED);\n \t\treturn idx;\n \t}\n \treturn 0;\n@@ -2184,7 +2183,7 @@ mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)\n \thrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n \tif (!hrxq)\n \t\treturn 0;\n-\tif (rte_atomic32_dec_and_test(&hrxq->refcnt)) {\n+\tif (__atomic_sub_fetch(&hrxq->refcnt, 1, __ATOMIC_RELAXED) == 0) {\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t\tmlx5_glue->destroy_flow_action(hrxq->action);\n #endif\n@@ -2257,7 +2256,7 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\trte_atomic32_inc(&hrxq->refcnt);\n+\t__atomic_fetch_add(&hrxq->refcnt, 1, __ATOMIC_RELAXED);\n \tILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,\n \t\t hrxq, next);\n \treturn hrxq_idx;\n@@ -2287,7 +2286,8 @@ mlx5_drop_action_create(struct rte_eth_dev *dev)\n \tint ret;\n \n \tif (priv->drop_queue.hrxq) {\n-\t\trte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);\n+\t\t__atomic_fetch_add(&priv->drop_queue.hrxq->refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\treturn priv->drop_queue.hrxq;\n \t}\n \thrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);\n@@ -2308,7 +2308,7 @@ mlx5_drop_action_create(struct rte_eth_dev *dev)\n \tret = priv->obj_ops.drop_action_create(dev);\n \tif (ret < 0)\n \t\tgoto error;\n-\trte_atomic32_set(&hrxq->refcnt, 1);\n+\t__atomic_store_n(&hrxq->refcnt, 1, __ATOMIC_RELAXED);\n \treturn hrxq;\n error:\n \tif (hrxq) {\n@@ -2332,7 +2332,7 @@ mlx5_drop_action_destroy(struct rte_eth_dev *dev)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;\n \n-\tif (rte_atomic32_dec_and_test(&hrxq->refcnt)) {\n+\tif (__atomic_sub_fetch(&hrxq->refcnt, 1, __ATOMIC_RELAXED) == 0) {\n \t\tpriv->obj_ops.drop_action_destroy(dev);\n \t\tmlx5_free(priv->drop_queue.rxq);\n \t\tmlx5_free(hrxq->ind_table);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex dca9c05951..7cd100813c 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -1141,7 +1141,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \ttmpl->type = MLX5_TXQ_TYPE_STANDARD;\n \tLIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);\n \treturn tmpl;\n@@ -1185,7 +1185,7 @@ mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \ttmpl->txq.idx = idx;\n \ttmpl->hairpin_conf = *hairpin_conf;\n \ttmpl->type = MLX5_TXQ_TYPE_HAIRPIN;\n-\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);\n \treturn tmpl;\n }\n@@ -1210,7 +1210,7 @@ mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)\n \n \tif (txq_data) {\n \t\tctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\t\t__atomic_add_fetch(&ctrl->refcnt, 1, __ATOMIC_RELAXED);\n+\t\t__atomic_fetch_add(&ctrl->refcnt, 1, __ATOMIC_RELAXED);\n \t}\n \treturn ctrl;\n }\n@@ -1235,7 +1235,7 @@ mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)\n \tif (!(*priv->txqs)[idx])\n \t\treturn 0;\n \ttxq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);\n-\tif (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)\n+\tif (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) != 0)\n \t\treturn 1;\n \tif (txq_ctrl->obj) {\n \t\tpriv->obj_ops.txq_obj_release(txq_ctrl->obj);\n", "prefixes": [ "3/4" ] }