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GET /api/patches/82080/?format=api
{ "id": 82080, "url": "http://patches.dpdk.org/api/patches/82080/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201025002953.1680999-14-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201025002953.1680999-14-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201025002953.1680999-14-qi.z.zhang@intel.com", "date": "2020-10-25T00:29:45", "name": "[v2,13/21] net/ice/base: implement shared rate limiter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b5979122321fe14bbf4bd10b3768c137e35f1f14", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201025002953.1680999-14-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 13297, "url": "http://patches.dpdk.org/api/series/13297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13297", "date": "2020-10-25T00:29:32", "name": "ice: update base code", "version": 2, "mbox": "http://patches.dpdk.org/series/13297/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/82080/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/82080/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8ED32A04DD;\n\tSun, 25 Oct 2020 02:30:15 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 416052C1A;\n\tSun, 25 Oct 2020 02:26:33 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 4F23A2B81\n for <dev@dpdk.org>; Sun, 25 Oct 2020 02:26:18 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Oct 2020 17:26:16 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by FMSMGA003.fm.intel.com with ESMTP; 24 Oct 2020 17:26:14 -0700" ], "IronPort-SDR": [ "\n GWV0NYw/iAuQaYnrg86qnGaTbVb7+tUButpOWwSdB25a181bYiaRsiLQKsBYAv61H9UljQ3n7m\n ACvBrzu4vx7Q==", "\n NPaHefCJAuPdqdQHyU2GxrrSQrQkQCLh0BCe/bojKGqDLHPNqC9l+nfhbXradaxxRjFzEoBwEF\n mEELWx7iO3dw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9784\"; a=\"167927041\"", "E=Sophos;i=\"5.77,414,1596524400\"; d=\"scan'208\";a=\"167927041\"", "E=Sophos;i=\"5.77,414,1596524400\"; d=\"scan'208\";a=\"359984082\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Tarun Singh <tarun.k.singh@intel.com>", "Date": "Sun, 25 Oct 2020 08:29:45 +0800", "Message-Id": "<20201025002953.1680999-14-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.4", "In-Reply-To": "<20201025002953.1680999-1-qi.z.zhang@intel.com>", "References": "<20201025002953.1680999-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 13/21] net/ice/base: implement shared rate\n\tlimiter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Implemented shared bandwidth rate limit functionality to account for\ndedicated bandwidth and minimum bandwidth. It requires non default\nprofile be programmed for CIR, EIR/PIR, and SRL.\n\nSigned-off-by: Tarun Singh <tarun.k.singh@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_sched.c | 484 +++++++++++++++++++++----------\n drivers/net/ice/base/ice_sched.h | 21 +-\n 2 files changed, 343 insertions(+), 162 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 7867d4fda8..ac48bbe279 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -3132,12 +3132,6 @@ static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw)\n \t\tice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n \t\tbw_t_info->eir_bw.bw = 0;\n \t} else {\n-\t\t/* EIR BW and Shared BW profiles are mutually exclusive and\n-\t\t * hence only one of them may be set for any given element.\n-\t\t * First clear earlier saved shared BW information.\n-\t\t */\n-\t\tice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n-\t\tbw_t_info->shared_bw = 0;\n \t\t/* save EIR BW information */\n \t\tice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n \t\tbw_t_info->eir_bw.bw = bw;\n@@ -3157,12 +3151,6 @@ static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw)\n \t\tice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n \t\tbw_t_info->shared_bw = 0;\n \t} else {\n-\t\t/* EIR BW and Shared BW profiles are mutually exclusive and\n-\t\t * hence only one of them may be set for any given element.\n-\t\t * First clear earlier saved EIR BW information.\n-\t\t */\n-\t\tice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n-\t\tbw_t_info->eir_bw.bw = 0;\n \t\t/* save shared BW information */\n \t\tice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n \t\tbw_t_info->shared_bw = bw;\n@@ -3435,15 +3423,19 @@ ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n * ice_cfg_vsi_bw_shared_lmt - configure VSI BW shared limit\n * @pi: port information structure\n * @vsi_handle: software VSI handle\n- * @bw: bandwidth in Kbps\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n *\n- * This function Configures shared rate limiter(SRL) of all VSI type nodes\n- * across all traffic classes for VSI matching handle.\n+ * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic\n+ * classes for VSI matching handle.\n */\n enum ice_status\n-ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw)\n+ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw,\n+\t\t\t u32 max_bw, u32 shared_bw)\n {\n-\treturn ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, bw);\n+\treturn ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, min_bw, max_bw,\n+\t\t\t\t\t shared_bw);\n }\n \n /**\n@@ -3458,6 +3450,8 @@ enum ice_status\n ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle)\n {\n \treturn ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle,\n+\t\t\t\t\t ICE_SCHED_DFLT_BW,\n+\t\t\t\t\t ICE_SCHED_DFLT_BW,\n \t\t\t\t\t ICE_SCHED_DFLT_BW);\n }\n \n@@ -3465,15 +3459,19 @@ ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle)\n * ice_cfg_agg_bw_shared_lmt - configure aggregator BW shared limit\n * @pi: port information structure\n * @agg_id: aggregator ID\n- * @bw: bandwidth in Kbps\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n *\n * This function configures the shared rate limiter(SRL) of all aggregator type\n * nodes across all traffic classes for aggregator matching agg_id.\n */\n enum ice_status\n-ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n+ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw,\n+\t\t\t u32 max_bw, u32 shared_bw)\n {\n-\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, bw);\n+\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, min_bw, max_bw,\n+\t\t\t\t\t shared_bw);\n }\n \n /**\n@@ -3487,7 +3485,47 @@ ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n enum ice_status\n ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id)\n {\n-\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW);\n+\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW,\n+\t\t\t\t\t ICE_SCHED_DFLT_BW,\n+\t\t\t\t\t ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_shared_lmt_per_tc - configure aggregator BW shared limit per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @tc: traffic class\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of all aggregator type\n+ * nodes across all traffic classes for aggregator matching agg_id.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t\t u32 min_bw, u32 max_bw, u32 shared_bw)\n+{\n+\treturn ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, min_bw,\n+\t\t\t\t\t\t max_bw, shared_bw);\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_shared_lmt_per_tc - configure aggregator BW shared limit per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @tc: traffic class\n+ *\n+ * This function configures the shared rate limiter(SRL) of all aggregator type\n+ * nodes across all traffic classes for aggregator matching agg_id.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc)\n+{\n+\treturn ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc,\n+\t\t\t\t\t\t ICE_SCHED_DFLT_BW,\n+\t\t\t\t\t\t ICE_SCHED_DFLT_BW,\n+\t\t\t\t\t\t ICE_SCHED_DFLT_BW);\n }\n \n /**\n@@ -3946,37 +3984,10 @@ ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node,\n \t\tdata->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);\n \t\tbreak;\n \tcase ICE_MAX_BW:\n-\t\t/* EIR BW and Shared BW profiles are mutually exclusive and\n-\t\t * hence only one of them may be set for any given element\n-\t\t */\n-\t\tif (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)\n-\t\t\treturn ICE_ERR_CFG;\n \t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_EIR;\n \t\tdata->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);\n \t\tbreak;\n \tcase ICE_SHARED_BW:\n-\t\t/* Check for removing shared BW */\n-\t\tif (rl_prof_id == ICE_SCHED_NO_SHARED_RL_PROF_ID) {\n-\t\t\t/* remove shared profile */\n-\t\t\tdata->valid_sections &= ~ICE_AQC_ELEM_VALID_SHARED;\n-\t\t\tdata->srl_id = 0; /* clear SRL field */\n-\n-\t\t\t/* enable back EIR to default profile */\n-\t\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_EIR;\n-\t\t\tdata->eir_bw.bw_profile_idx =\n-\t\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n-\t\t\tbreak;\n-\t\t}\n-\t\t/* EIR BW and Shared BW profiles are mutually exclusive and\n-\t\t * hence only one of them may be set for any given element\n-\t\t */\n-\t\tif ((data->valid_sections & ICE_AQC_ELEM_VALID_EIR) &&\n-\t\t (LE16_TO_CPU(data->eir_bw.bw_profile_idx) !=\n-\t\t\t ICE_SCHED_DFLT_RL_PROF_ID))\n-\t\t\treturn ICE_ERR_CFG;\n-\t\t/* EIR BW is set to default, disable it */\n-\t\tdata->valid_sections &= ~ICE_AQC_ELEM_VALID_EIR;\n-\t\t/* Okay to enable shared BW now */\n \t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_SHARED;\n \t\tdata->srl_id = CPU_TO_LE16(rl_prof_id);\n \t\tbreak;\n@@ -4187,51 +4198,6 @@ ice_sched_set_node_bw_dflt(struct ice_port_info *pi,\n \treturn ice_sched_rm_rl_profile(hw, layer_num, profile_type, old_id);\n }\n \n-/**\n- * ice_sched_set_eir_srl_excl - set EIR/SRL exclusiveness\n- * @pi: port information structure\n- * @node: pointer to node structure\n- * @layer_num: layer number where rate limit profiles are saved\n- * @rl_type: rate limit type min, max, or shared\n- * @bw: bandwidth value\n- *\n- * This function prepares node element's bandwidth to SRL or EIR exclusively.\n- * EIR BW and Shared BW profiles are mutually exclusive and hence only one of\n- * them may be set for any given element. This function needs to be called\n- * with the scheduler lock held.\n- */\n-static enum ice_status\n-ice_sched_set_eir_srl_excl(struct ice_port_info *pi,\n-\t\t\t struct ice_sched_node *node,\n-\t\t\t u8 layer_num, enum ice_rl_type rl_type, u32 bw)\n-{\n-\tif (rl_type == ICE_SHARED_BW) {\n-\t\t/* SRL node passed in this case, it may be different node */\n-\t\tif (bw == ICE_SCHED_DFLT_BW)\n-\t\t\t/* SRL being removed, ice_sched_cfg_node_bw_lmt()\n-\t\t\t * enables EIR to default. EIR is not set in this\n-\t\t\t * case, so no additional action is required.\n-\t\t\t */\n-\t\t\treturn ICE_SUCCESS;\n-\n-\t\t/* SRL being configured, set EIR to default here.\n-\t\t * ice_sched_cfg_node_bw_lmt() disables EIR when it\n-\t\t * configures SRL\n-\t\t */\n-\t\treturn ice_sched_set_node_bw_dflt(pi, node, ICE_MAX_BW,\n-\t\t\t\t\t\t layer_num);\n-\t} else if (rl_type == ICE_MAX_BW &&\n-\t\t node->info.data.valid_sections & ICE_AQC_ELEM_VALID_SHARED) {\n-\t\t/* Remove Shared profile. Set default shared BW call\n-\t\t * removes shared profile for a node.\n-\t\t */\n-\t\treturn ice_sched_set_node_bw_dflt(pi, node,\n-\t\t\t\t\t\t ICE_SHARED_BW,\n-\t\t\t\t\t\t layer_num);\n-\t}\n-\treturn ICE_SUCCESS;\n-}\n-\n /**\n * ice_sched_set_node_bw - set node's bandwidth\n * @pi: port information structure\n@@ -4289,14 +4255,14 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n *\n * It updates node's BW limit parameters like BW RL profile ID of type CIR,\n * EIR, or SRL. The caller needs to hold scheduler lock.\n+ *\n+ * NOTE: Caller provides the correct SRL node in case of shared profile\n+ * settings.\n */\n static enum ice_status\n ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n \t\t\t enum ice_rl_type rl_type, u32 bw)\n {\n-\tstruct ice_sched_node *cfg_node = node;\n-\tenum ice_status status;\n-\n \tstruct ice_hw *hw;\n \tu8 layer_num;\n \n@@ -4305,28 +4271,15 @@ ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n \thw = pi->hw;\n \t/* Remove unused RL profile IDs from HW and SW DB */\n \tice_sched_rm_unused_rl_prof(hw);\n+\n \tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n-\t\t\t\t\t\tnode->tx_sched_layer);\n+\t\tnode->tx_sched_layer);\n \tif (layer_num >= hw->num_tx_sched_layers)\n \t\treturn ICE_ERR_PARAM;\n \n-\tif (rl_type == ICE_SHARED_BW) {\n-\t\t/* SRL node may be different */\n-\t\tcfg_node = ice_sched_get_srl_node(node, layer_num);\n-\t\tif (!cfg_node)\n-\t\t\treturn ICE_ERR_CFG;\n-\t}\n-\t/* EIR BW and Shared BW profiles are mutually exclusive and\n-\t * hence only one of them may be set for any given element\n-\t */\n-\tstatus = ice_sched_set_eir_srl_excl(pi, cfg_node, layer_num, rl_type,\n-\t\t\t\t\t bw);\n-\tif (status)\n-\t\treturn status;\n \tif (bw == ICE_SCHED_DFLT_BW)\n-\t\treturn ice_sched_set_node_bw_dflt(pi, cfg_node, rl_type,\n-\t\t\t\t\t\t layer_num);\n-\treturn ice_sched_set_node_bw(pi, cfg_node, rl_type, bw, layer_num);\n+\t\treturn ice_sched_set_node_bw_dflt(pi, node, rl_type, layer_num);\n+\treturn ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num);\n }\n \n /**\n@@ -4886,19 +4839,108 @@ ice_sched_validate_vsi_srl_node(struct ice_port_info *pi, u16 vsi_handle)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_sched_set_save_vsi_srl_node_bw - set VSI shared limit values\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: traffic class\n+ * @srl_node: sched node to configure\n+ * @rl_type: rate limit type minimum, maximum, or shared\n+ * @bw: minimum, maximum, or shared bandwidth in Kbps\n+ *\n+ * Configure shared rate limiter(SRL) of VSI type nodes across given traffic\n+ * class, and saves those value for later use for replaying purposes. The\n+ * caller holds the scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_set_save_vsi_srl_node_bw(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\t u8 tc, struct ice_sched_node *srl_node,\n+\t\t\t\t enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status;\n+\n+\tif (bw == ICE_SCHED_DFLT_BW) {\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type);\n+\t} else {\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t\tstatus = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_vsi_node_srl_per_tc - set VSI node BW shared limit for tc\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: traffic class\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n+ *\n+ * Configure shared rate limiter(SRL) of VSI type nodes across requested\n+ * traffic class for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW\n+ * is passed, it removes the corresponding bw from the node. The caller\n+ * holds scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_set_vsi_node_srl_per_tc(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\t u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw)\n+{\n+\tstruct ice_sched_node *tc_node, *vsi_node, *cfg_node;\n+\tenum ice_status status;\n+\tu8 layer_num;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tvsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle);\n+\tif (!vsi_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tlayer_num = ice_sched_get_rl_prof_layer(pi, ICE_SHARED_BW,\n+\t\t\t\t\t\tvsi_node->tx_sched_layer);\n+\tif (layer_num >= pi->hw->num_tx_sched_layers)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* SRL node may be different */\n+\tcfg_node = ice_sched_get_srl_node(vsi_node, layer_num);\n+\tif (!cfg_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tstatus = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc,\n+\t\t\t\t\t\t cfg_node, ICE_MIN_BW,\n+\t\t\t\t\t\t min_bw);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc,\n+\t\t\t\t\t\t cfg_node, ICE_MAX_BW,\n+\t\t\t\t\t\t max_bw);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, cfg_node,\n+\t\t\t\t\t\t ICE_SHARED_BW, shared_bw);\n+}\n+\n /**\n * ice_sched_set_vsi_bw_shared_lmt - set VSI BW shared limit\n * @pi: port information structure\n * @vsi_handle: software VSI handle\n- * @bw: bandwidth in Kbps\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n *\n- * This function Configures shared rate limiter(SRL) of all VSI type nodes\n- * across all traffic classes for VSI matching handle. When BW value of\n- * ICE_SCHED_DFLT_BW is passed, it removes the SRL from the node.\n+ * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic\n+ * classes for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW is\n+ * passed, it removes those value(s) from the node.\n */\n enum ice_status\n ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n-\t\t\t\tu32 bw)\n+\t\t\t\tu32 min_bw, u32 max_bw, u32 shared_bw)\n {\n \tenum ice_status status = ICE_SUCCESS;\n \tu8 tc;\n@@ -4916,7 +4958,6 @@ ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n \t/* Return success if no nodes are present across TC */\n \tice_for_each_traffic_class(tc) {\n \t\tstruct ice_sched_node *tc_node, *vsi_node;\n-\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n \n \t\ttc_node = ice_sched_get_tc_node(pi, tc);\n \t\tif (!tc_node)\n@@ -4926,16 +4967,9 @@ ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n \t\tif (!vsi_node)\n \t\t\tcontinue;\n \n-\t\tif (bw == ICE_SCHED_DFLT_BW)\n-\t\t\t/* It removes existing SRL from the node */\n-\t\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, vsi_node,\n-\t\t\t\t\t\t\t\trl_type);\n-\t\telse\n-\t\t\tstatus = ice_sched_set_node_bw_lmt(pi, vsi_node,\n-\t\t\t\t\t\t\t rl_type, bw);\n-\t\tif (status)\n-\t\t\tbreak;\n-\t\tstatus = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);\n+\t\tstatus = ice_sched_set_vsi_node_srl_per_tc(pi, vsi_handle, tc,\n+\t\t\t\t\t\t\t min_bw, max_bw,\n+\t\t\t\t\t\t\t shared_bw);\n \t\tif (status)\n \t\t\tbreak;\n \t}\n@@ -5003,32 +5037,23 @@ ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id)\n }\n \n /**\n- * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit\n+ * ice_sched_validate_agg_id - Validate aggregator id\n * @pi: port information structure\n * @agg_id: aggregator ID\n- * @bw: bandwidth in Kbps\n *\n- * This function configures the shared rate limiter(SRL) of all aggregator type\n- * nodes across all traffic classes for aggregator matching agg_id. When\n- * BW value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the\n- * node(s).\n+ * This function validates aggregator id. Caller holds the scheduler lock.\n */\n-enum ice_status\n-ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n+static enum ice_status\n+ice_sched_validate_agg_id(struct ice_port_info *pi, u32 agg_id)\n {\n \tstruct ice_sched_agg_info *agg_info;\n \tstruct ice_sched_agg_info *tmp;\n \tbool agg_id_present = false;\n-\tenum ice_status status = ICE_SUCCESS;\n-\tu8 tc;\n-\n-\tif (!pi)\n-\t\treturn ICE_ERR_PARAM;\n+\tenum ice_status status;\n \n-\tice_acquire_lock(&pi->sched_lock);\n \tstatus = ice_sched_validate_agg_srl_node(pi, agg_id);\n \tif (status)\n-\t\tgoto exit_agg_bw_shared_lmt;\n+\t\treturn status;\n \n \tLIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list,\n \t\t\t\t ice_sched_agg_info, list_entry)\n@@ -5037,14 +5062,129 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n \t\t\tbreak;\n \t\t}\n \n-\tif (!agg_id_present) {\n-\t\tstatus = ICE_ERR_PARAM;\n-\t\tgoto exit_agg_bw_shared_lmt;\n+\tif (!agg_id_present)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_save_agg_srl_node_bw - set aggregator shared limit values\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @tc: traffic class\n+ * @srl_node: sched node to configure\n+ * @rl_type: rate limit type minimum, maximum, or shared\n+ * @bw: minimum, maximum, or shared bandwidth in Kbps\n+ *\n+ * Configure shared rate limiter(SRL) of aggregator type nodes across\n+ * requested traffic class, and saves those value for later use for\n+ * replaying purposes. The caller holds the scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_set_save_agg_srl_node_bw(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t\t struct ice_sched_node *srl_node,\n+\t\t\t\t enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status;\n+\n+\tif (bw == ICE_SCHED_DFLT_BW) {\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type);\n+\t} else {\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t\tstatus = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);\n \t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_agg_node_srl_per_tc - set aggregator SRL per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @tc: traffic class\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of aggregator type\n+ * node for a given traffic class for aggregator matching agg_id. When BW\n+ * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. Caller\n+ * holds the scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_set_agg_node_srl_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\t u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw)\n+{\n+\tstruct ice_sched_node *tc_node, *agg_node, *cfg_node;\n+\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n+\tenum ice_status status = ICE_ERR_CFG;\n+\tu8 layer_num;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tagg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);\n+\tif (!agg_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n+\t\t\t\t\t\tagg_node->tx_sched_layer);\n+\tif (layer_num >= pi->hw->num_tx_sched_layers)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* SRL node may be different */\n+\tcfg_node = ice_sched_get_srl_node(agg_node, layer_num);\n+\tif (!cfg_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tstatus = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node,\n+\t\t\t\t\t\t ICE_MIN_BW, min_bw);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node,\n+\t\t\t\t\t\t ICE_MAX_BW, max_bw);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node,\n+\t\t\t\t\t\t ICE_SHARED_BW, shared_bw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of all aggregator type\n+ * nodes across all traffic classes for aggregator matching agg_id. When\n+ * BW value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the\n+ * node(s).\n+ */\n+enum ice_status\n+ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\tu32 min_bw, u32 max_bw, u32 shared_bw)\n+{\n+\tenum ice_status status;\n+\tu8 tc;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_validate_agg_id(pi, agg_id);\n+\tif (status)\n+\t\tgoto exit_agg_bw_shared_lmt;\n \n \t/* Return success if no nodes are present across TC */\n \tice_for_each_traffic_class(tc) {\n-\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n \t\tstruct ice_sched_node *tc_node, *agg_node;\n \n \t\ttc_node = ice_sched_get_tc_node(pi, tc);\n@@ -5055,16 +5195,9 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n \t\tif (!agg_node)\n \t\t\tcontinue;\n \n-\t\tif (bw == ICE_SCHED_DFLT_BW)\n-\t\t\t/* It removes existing SRL from the node */\n-\t\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, agg_node,\n-\t\t\t\t\t\t\t\trl_type);\n-\t\telse\n-\t\t\tstatus = ice_sched_set_node_bw_lmt(pi, agg_node,\n-\t\t\t\t\t\t\t rl_type, bw);\n-\t\tif (status)\n-\t\t\tbreak;\n-\t\tstatus = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);\n+\t\tstatus = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc,\n+\t\t\t\t\t\t\t min_bw, max_bw,\n+\t\t\t\t\t\t\t shared_bw);\n \t\tif (status)\n \t\t\tbreak;\n \t}\n@@ -5074,6 +5207,41 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n \treturn status;\n }\n \n+/**\n+ * ice_sched_set_agg_bw_shared_lmt_per_tc - set aggregator BW shared lmt per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator ID\n+ * @tc: traffic class\n+ * @min_bw: minimum bandwidth in Kbps\n+ * @max_bw: maximum bandwidth in Kbps\n+ * @shared_bw: shared bandwidth in Kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of aggregator type\n+ * node for a given traffic class for aggregator matching agg_id. When BW\n+ * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node.\n+ */\n+enum ice_status\n+ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\t u8 tc, u32 min_bw, u32 max_bw,\n+\t\t\t\t u32 shared_bw)\n+{\n+\tenum ice_status status;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_validate_agg_id(pi, agg_id);\n+\tif (status)\n+\t\tgoto exit_agg_bw_shared_lmt_per_tc;\n+\n+\tstatus = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, min_bw,\n+\t\t\t\t\t\t max_bw, shared_bw);\n+\n+exit_agg_bw_shared_lmt_per_tc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n /**\n * ice_sched_cfg_sibl_node_prio - configure node sibling priority\n * @pi: port information structure\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nindex 501a4c499e..8b275637a4 100644\n--- a/drivers/net/ice/base/ice_sched.h\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -153,14 +153,22 @@ enum ice_status\n ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n \t\t\t enum ice_rl_type rl_type);\n enum ice_status\n-ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw);\n+ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw,\n+\t\t\t u32 max_bw, u32 shared_bw);\n enum ice_status\n ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle);\n enum ice_status\n-ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);\n+ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw,\n+\t\t\t u32 max_bw, u32 shared_bw);\n enum ice_status\n ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id);\n enum ice_status\n+ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t\t u32 min_bw, u32 max_bw, u32 shared_bw);\n+enum ice_status\n+ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\t u8 tc);\n+enum ice_status\n ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,\n \t\t u8 *q_prio);\n enum ice_status\n@@ -184,9 +192,14 @@ ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,\n \t\t\t\t enum ice_rl_type rl_type, u32 bw);\n enum ice_status\n ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n-\t\t\t\tu32 bw);\n+\t\t\t\tu32 min_bw, u32 max_bw, u32 shared_bw);\n+enum ice_status\n+ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw,\n+\t\t\t\tu32 max_bw, u32 shared_bw);\n enum ice_status\n-ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);\n+ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\t u8 tc, u32 min_bw, u32 max_bw,\n+\t\t\t\t u32 shared_bw);\n enum ice_status\n ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,\n \t\t\t struct ice_sched_node *node, u8 priority);\n", "prefixes": [ "v2", "13/21" ] }