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{
    "id": 81793,
    "url": "http://patches.dpdk.org/api/patches/81793/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603375597-430528-5-git-send-email-bingz@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1603375597-430528-5-git-send-email-bingz@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1603375597-430528-5-git-send-email-bingz@nvidia.com",
    "date": "2020-10-22T14:06:35",
    "name": "[v2,4/6] net/mlx5: conditional hairpin auto bind",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7e3c44dd1476b8241a81d9296e28645ced97cca4",
    "submitter": {
        "id": 1976,
        "url": "http://patches.dpdk.org/api/people/1976/?format=api",
        "name": "Bing Zhao",
        "email": "bingz@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603375597-430528-5-git-send-email-bingz@nvidia.com/mbox/",
    "series": [
        {
            "id": 13215,
            "url": "http://patches.dpdk.org/api/series/13215/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13215",
            "date": "2020-10-22T14:06:31",
            "name": "add two ports hairpin mode support in mlx5 PMD",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/13215/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/81793/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/81793/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 03425A04DD;\n\tThu, 22 Oct 2020 16:08:21 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 35A42AA12;\n\tThu, 22 Oct 2020 16:07:08 +0200 (CEST)",
            "from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130])\n by dpdk.org (Postfix) with ESMTP id 627C8AA09\n for <dev@dpdk.org>; Thu, 22 Oct 2020 16:06:55 +0200 (CEST)"
        ],
        "From": "Bing Zhao <bingz@nvidia.com>",
        "To": "viacheslavo@mellanox.com,\n\tmatan@mellanox.com",
        "Cc": "dev@dpdk.org,\n\torika@nvidia.com,\n\trasland@nvidia.com",
        "Date": "Thu, 22 Oct 2020 22:06:35 +0800",
        "Message-Id": "<1603375597-430528-5-git-send-email-bingz@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1603375597-430528-1-git-send-email-bingz@nvidia.com>",
        "References": "<1602166620-46303-1-git-send-email-bingz@nvidia.com>\n <1603375597-430528-1-git-send-email-bingz@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v2 4/6] net/mlx5: conditional hairpin auto bind",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "In single port hairpin mode, after the queues are configured during\nstart up. The binding process will be enabled automatically in the\nport start phase and the default control flow for egress will be\ncreated.\n\nWhen switching to two ports hairpin mode, the auto binding process\nshould be skipped if there is no TX queue with the peer RX queue on\nthe same device, and it should be skipped also if the queues are\nconfigured with manual bind attribute.\n\nIf the explicit TX flow rule mode is configured or hairpin is\nbetween two ports, the default control flows for TX queues should\nnot be created.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5_trigger.c | 33 +++++++++++++++++++++++++++++++--\n 1 file changed, 31 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 497f731..27bd3e9 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -214,6 +214,8 @@\n \tstruct mlx5_devx_obj *rq;\n \tunsigned int i;\n \tint ret = 0;\n+\tbool need_auto = false;\n+\tuint16_t self_port = dev->data->port_id;\n \n \tfor (i = 0; i != priv->txqs_n; ++i) {\n \t\ttxq_ctrl = mlx5_txq_get(dev, i);\n@@ -223,6 +225,25 @@\n \t\t\tmlx5_txq_release(dev, i);\n \t\t\tcontinue;\n \t\t}\n+\t\tif (txq_ctrl->hairpin_conf.peers[0].port != self_port)\n+\t\t\tcontinue;\n+\t\tif (txq_ctrl->hairpin_conf.manual_bind) {\n+\t\t\tmlx5_txq_release(dev, i);\n+\t\t\treturn 0;\n+\t\t}\n+\t\tneed_auto = true;\n+\t\tmlx5_txq_release(dev, i);\n+\t}\n+\tif (!need_auto)\n+\t\treturn 0;\n+\tfor (i = 0; i != priv->txqs_n; ++i) {\n+\t\ttxq_ctrl = mlx5_txq_get(dev, i);\n+\t\tif (!txq_ctrl)\n+\t\t\tcontinue;\n+\t\tif (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {\n+\t\t\tmlx5_txq_release(dev, i);\n+\t\t\tcontinue;\n+\t\t}\n \t\tif (!txq_ctrl->obj) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tDRV_LOG(ERR, \"port %u no txq object found: %d\",\n@@ -1028,9 +1049,13 @@\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n+\t/*\n+\t * Such step will be skipped if there is no hairpin TX queue configured\n+\t * with RX peer queue from the same device.\n+\t */\n \tret = mlx5_hairpin_auto_bind(dev);\n \tif (ret) {\n-\t\tDRV_LOG(ERR, \"port %u hairpin binding failed: %s\",\n+\t\tDRV_LOG(ERR, \"port %u hairpin auto binding failed: %s\",\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n@@ -1181,7 +1206,11 @@\n \t\tstruct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);\n \t\tif (!txq_ctrl)\n \t\t\tcontinue;\n-\t\tif (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {\n+\t\t/* Only Tx implicit mode requires the default Tx flow. */\n+\t\tif (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN &&\n+\t\t    txq_ctrl->hairpin_conf.tx_explicit == 0 &&\n+\t\t    txq_ctrl->hairpin_conf.peers[0].port ==\n+\t\t    priv->dev_data->port_id) {\n \t\t\tret = mlx5_ctrl_flow_source_queue(dev, i);\n \t\t\tif (ret) {\n \t\t\t\tmlx5_txq_release(dev, i);\n",
    "prefixes": [
        "v2",
        "4/6"
    ]
}