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GET /api/patches/81620/?format=api
{ "id": 81620, "url": "http://patches.dpdk.org/api/patches/81620/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201020215538.59242-2-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201020215538.59242-2-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201020215538.59242-2-ajit.khaparde@broadcom.com", "date": "2020-10-20T21:55:28", "name": "[v2,01/11] net/bnxt: add stingray support to core layer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "caee5fcf79cd6827141f0487de6dff0ba6a3f682", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201020215538.59242-2-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 13155, "url": "http://patches.dpdk.org/api/series/13155/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13155", "date": "2020-10-20T21:55:27", "name": "bnxt fixes and enhancements to TRUFLOW support", "version": 2, "mbox": "http://patches.dpdk.org/series/13155/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81620/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81620/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 47E7CA04DD;\n\tTue, 20 Oct 2020 23:56:05 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9889AAC97;\n\tTue, 20 Oct 2020 23:55:49 +0200 (CEST)", "from mail-pg1-f170.google.com (mail-pg1-f170.google.com\n [209.85.215.170]) by dpdk.org (Postfix) with ESMTP id 54E70AC93\n for <dev@dpdk.org>; Tue, 20 Oct 2020 23:55:46 +0200 (CEST)", "by mail-pg1-f170.google.com with SMTP id o3so148405pgr.11\n for <dev@dpdk.org>; Tue, 20 Oct 2020 14:55:46 -0700 (PDT)", "from localhost.localdomain ([192.19.223.252])\n by smtp.gmail.com with ESMTPSA id e6sm24113pfn.190.2020.10.20.14.55.42\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Tue, 20 Oct 2020 14:55:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version; bh=ZMnx+hNpS2yFRptUbxuK1rTdazvRAc84f4LDSJXpTwg=;\n b=VmBhFTdFhp0a9Sy/lRDVOxx1Ib7QQuvMEt5nfYO8iqYzsGtNyhM55HBMCa5BF1rj0d\n 7o5aoOKM1WnyMISMg96d5KtB6n3hbbOC+HuC0q8TKXowQo3g+ATiFWd43im+3byRqXhX\n GzviSjnxSVTJzt/exkbaihk137xiWBcerLq5k=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version;\n bh=ZMnx+hNpS2yFRptUbxuK1rTdazvRAc84f4LDSJXpTwg=;\n b=fQlQtwT65NZETIAP9j0zEktFDdM66QC1JY4U/HqzyUgJW1KX0qhdTK5xbwXwEh0LZ8\n PUlFRco0ynj2/5s+4SRl/HuMVdaCMyzXpMg5KuFbcAXAZQfHl3s9Ss/pdmIP0yA5AwSq\n 12ywRkl31Snntn5j5i7l/Ct9bYxD+wTvOQE4vfnPAY/8/Ddz8vJMiUyDiWQK/R4rIn4+\n GuPEJF0xaId0rtzws2JbSHT8grin0uBk6tlO32sKZCgMOLh0tOTXXiUzD++We5yNSAh6\n Zj/8evnuMZyRy2ZvIt9r8Oc/a8x0A5bDkOWFmtjMOJdfoLX/RvXxVO7R2P3ntZqGx5n0\n iJhA==", "X-Gm-Message-State": "AOAM532EhPSmgJYkQsKpnI3/vw/LaqE4RU5S1ErFv47ifLZttjKzjAeF\n ZsmGYaLMZcPNyt7iLnBY7le+/vsc2ACW+0zUNZLBX3XozCzRgpv1l237Z5Krkr5dChwf1byxkmX\n zl6wmJQGgpansnBXhXvZ2htL4OgOP6/QpdWhTe3vyyECdGFmFRvy9h39qmxM/UgbkQw==", "X-Google-Smtp-Source": "\n ABdhPJzGyhbL75Hab5sL1GXyp2k58C3JvR4RS/CRFTogfc8NE4/Dzh5gJMfV3Iqfo9HA2HgaeIEPrA==", "X-Received": "by 2002:a63:3588:: with SMTP id c130mr306641pga.200.1603230943764;\n Tue, 20 Oct 2020 14:55:43 -0700 (PDT)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Peter Spreadborough <peter.spreadborough@broadcom.com>,\n Jay Ding <jay.ding@broadcom.com>, Farah Smith <farah.smith@broadcom.com>", "Date": "Tue, 20 Oct 2020 14:55:28 -0700", "Message-Id": "<20201020215538.59242-2-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20201020215538.59242-1-ajit.khaparde@broadcom.com>", "References": "\n <1602916089-18576-1-git-send-email-venkatkumar.duvvuru@broadcom.com>\n <20201020215538.59242-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "Content-Transfer-Encoding": "8bit", "X-Content-Filtered-By": "Mailman/MimeDel 2.1.15", "Subject": "[dpdk-dev] [PATCH v2 01/11] net/bnxt: add stingray support to core\n\tlayer", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Peter Spreadborough <peter.spreadborough@broadcom.com>\n\n- Moved P4 specific code under the P4 directory\n- Added P45 skeleton code for SR to build on\n- Add SR support in truflow core layer\n\nSigned-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>\nSigned-off-by: Jay Ding <jay.ding@broadcom.com>\nReviewed-by: Farah Smith <farah.smith@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/hcapi/hcapi_cfa.h | 39 +++++--\n drivers/net/bnxt/tf_core/cfa_resource_types.h | 95 ++++++----------\n drivers/net/bnxt/tf_core/tf_core.c | 3 +-\n drivers/net/bnxt/tf_core/tf_core.h | 2 +-\n drivers/net/bnxt/tf_core/tf_device.c | 9 +-\n drivers/net/bnxt/tf_core/tf_device_p4.c | 25 ++++-\n drivers/net/bnxt/tf_core/tf_device_p4.h | 6 +\n drivers/net/bnxt/tf_core/tf_device_p45.h | 105 ++++++++++++++++++\n drivers/net/bnxt/tf_core/tf_em.h | 6 -\n 9 files changed, 207 insertions(+), 83 deletions(-)\n create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h", "diff": "diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/hcapi_cfa.h\nindex c7d87dec7..aa218d714 100644\n--- a/drivers/net/bnxt/hcapi/hcapi_cfa.h\n+++ b/drivers/net/bnxt/hcapi/hcapi_cfa.h\n@@ -14,7 +14,15 @@\n \n #include \"hcapi_cfa_defs.h\"\n \n+#if CHIP_CFG == SR_A\n+#define SUPPORT_CFA_HW_P45 1\n+#undef SUPPORT_CFA_HW_P4\n+#define SUPPORT_CFA_HW_P4 0\n+#elif CHIP_CFG == CMB_A\n #define SUPPORT_CFA_HW_P4 1\n+#else\n+#error \"Chip not supported\"\n+#endif\n \n #if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59\n #define SUPPORT_CFA_HW_ALL 1\n@@ -81,17 +89,20 @@ struct hcapi_cfa_key_result {\n /* common CFA register access macros */\n #define CFA_REG(x)\t\tOFFSETOF(cfa_reg_t, cfa_##x)\n \n-#ifndef REG_WR\n-#define REG_WR(_p, x, y) (*((uint32_t volatile *)(x)) = (y))\n+#ifndef TF_REG_WR\n+#define TF_REG_WR(_p, x, y) (*((uint32_t volatile *)(x)) = (y))\n #endif\n-#ifndef REG_RD\n-#define REG_RD(_p, x) (*((uint32_t volatile *)(x)))\n+#ifndef TF_REG_RD\n+#define TF_REG_RD(_p, x) (*((uint32_t volatile *)(x)))\n+#endif\n+#ifndef TF_CFA_REG_RD\n+#define TF_CFA_REG_RD(_p, x)\t\\\n+\tTF_REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))\n+#endif\n+#ifndef TF_CFA_REG_WR\n+#define TF_CFA_REG_WR(_p, x, y)\t\\\n+\tTF_REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)\n #endif\n-#define CFA_REG_RD(_p, x)\t\\\n-\tREG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))\n-#define CFA_REG_WR(_p, x, y)\t\\\n-\tREG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)\n-\n \n /* Constants used by Resource Manager Registration*/\n #define RM_CLIENT_NAME_MAX_LEN 32\n@@ -248,7 +259,15 @@ int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op,\n int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op,\n \t\t\t\t uint32_t type,\n \t\t\t\t struct hcapi_cfa_data *config);\n-#endif /* SUPPORT_CFA_HW_P4 */\n+/* SUPPORT_CFA_HW_P4 */\n+#elif SUPPORT_CFA_HW_P45\n+int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op,\n+\t\t\t struct hcapi_cfa_data *mirror);\n+int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op,\n+\t\t\t\t uint32_t type,\n+\t\t\t\t struct hcapi_cfa_data *config);\n+/* SUPPORT_CFA_HW_P45 */\n+#endif\n /**\n * HCAPI CFA device HW operation function callback definition\n * This is standardized function callback hook to install different\ndiff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h\nindex 19838c393..a62063b0e 100644\n--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h\n+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h\n@@ -1,6 +1,13 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019-2020 Broadcom\n- * All rights reserved.\n+/*\n+ * Copyright(c) 2001-2020, Broadcom. All rights reserved. The\n+ * term Broadcom refers to Broadcom Inc. and/or its subsidiaries.\n+ * Proprietary and Confidential Information.\n+ *\n+ * This source file is the property of Broadcom Corporation, and\n+ * may not be copied or distributed in any isomorphic form without\n+ * the prior written consent of Broadcom Corporation.\n+ *\n+ * DO NOT MODIFY!!! This file is automatically generated.\n */\n \n #ifndef _CFA_RESOURCE_TYPES_H_\n@@ -64,79 +71,47 @@\n #define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM\n \n \n-/* Multicast Group */\n-#define CFA_RESOURCE_TYPE_P58_MCG 0x0UL\n-/* Encap 8 byte record */\n-#define CFA_RESOURCE_TYPE_P58_ENCAP_8B 0x1UL\n-/* Encap 16 byte record */\n-#define CFA_RESOURCE_TYPE_P58_ENCAP_16B 0x2UL\n-/* Encap 64 byte record */\n-#define CFA_RESOURCE_TYPE_P58_ENCAP_64B 0x3UL\n-/* Source Property MAC */\n-#define CFA_RESOURCE_TYPE_P58_SP_MAC 0x4UL\n-/* Source Property MAC and IPv4 */\n-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4 0x5UL\n-/* Source Property MAC and IPv6 */\n-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6 0x6UL\n-/* Network Address Translation Port */\n-#define CFA_RESOURCE_TYPE_P58_NAT_PORT 0x7UL\n-/* Network Address Translation IPv4 address */\n-#define CFA_RESOURCE_TYPE_P58_NAT_IPV4 0x8UL\n /* Meter */\n-#define CFA_RESOURCE_TYPE_P58_METER 0x9UL\n-/* Flow State */\n-#define CFA_RESOURCE_TYPE_P58_FLOW_STATE 0xaUL\n-/* Full Action Records */\n-#define CFA_RESOURCE_TYPE_P58_FULL_ACTION 0xbUL\n-/* Action Record Format 0 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION 0xcUL\n-/* Action Record Ext Format 0 */\n-#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL\n-/* Action Record Format 1 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION 0xeUL\n-/* Action Record Format 2 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION 0xfUL\n-/* Action Record Format 3 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION 0x10UL\n-/* Action Record Format 4 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION 0x11UL\n-/* Action Record Format 5 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION 0x12UL\n-/* Action Record Format 6 */\n-#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION 0x13UL\n+#define CFA_RESOURCE_TYPE_P58_METER 0x0UL\n+/* SRAM_Bank_0 */\n+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 0x1UL\n+/* SRAM_Bank_1 */\n+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 0x2UL\n+/* SRAM_Bank_2 */\n+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 0x3UL\n+/* SRAM_Bank_3 */\n+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 0x4UL\n /* L2 Context TCAM High priority entries */\n-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x14UL\n+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x5UL\n /* L2 Context TCAM Low priority entries */\n-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x15UL\n+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x6UL\n /* L2 Context REMAP high priority entries */\n-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x16UL\n+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x7UL\n /* L2 Context REMAP Low priority entries */\n-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x17UL\n+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x8UL\n /* Profile Func */\n-#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x18UL\n+#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x9UL\n /* Profile TCAM */\n-#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0x19UL\n+#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0xaUL\n /* Exact Match Profile Id */\n-#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0x1aUL\n+#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0xbUL\n /* Wildcard Profile Id */\n-#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0x1bUL\n+#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0xcUL\n /* Exact Match Record */\n-#define CFA_RESOURCE_TYPE_P58_EM_REC 0x1cUL\n+#define CFA_RESOURCE_TYPE_P58_EM_REC 0xdUL\n /* Wildcard TCAM */\n-#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0x1dUL\n+#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0xeUL\n /* Meter profile */\n-#define CFA_RESOURCE_TYPE_P58_METER_PROF 0x1eUL\n+#define CFA_RESOURCE_TYPE_P58_METER_PROF 0xfUL\n /* Meter */\n-#define CFA_RESOURCE_TYPE_P58_MIRROR 0x1fUL\n-/* Source Property TCAM */\n-#define CFA_RESOURCE_TYPE_P58_SP_TCAM 0x20UL\n+#define CFA_RESOURCE_TYPE_P58_MIRROR 0x10UL\n /* Exact Match Flexible Key Builder */\n-#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x21UL\n+#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x11UL\n /* Wildcard Flexible Key Builder */\n-#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x22UL\n+#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL\n /* VEB TCAM */\n-#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x23UL\n-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM\n+#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL\n+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM\n \n \n /* Multicast Group */\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex 0dbde1de2..788335b81 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -34,7 +34,8 @@ tf_open_session(struct tf *tfp,\n \t * side. It is assumed that the Firmware will be supported if\n \t * firmware open session succeeds.\n \t */\n-\tif (parms->device_type != TF_DEVICE_TYPE_WH) {\n+\tif (parms->device_type != TF_DEVICE_TYPE_WH &&\n+\t parms->device_type != TF_DEVICE_TYPE_SR) {\n \t\tTFP_DRV_LOG(ERR,\n \t\t\t \"Unsupported device type %d\\n\",\n \t\t\t parms->device_type);\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex db1093515..65be8f54a 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -10,7 +10,7 @@\n #include <stdlib.h>\n #include <stdbool.h>\n #include <stdio.h>\n-#include \"hcapi/hcapi_cfa.h\"\n+#include \"hcapi/hcapi_cfa_defs.h\"\n #include \"tf_project.h\"\n \n /**\ndiff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c\nindex 112944095..838982801 100644\n--- a/drivers/net/bnxt/tf_core/tf_device.c\n+++ b/drivers/net/bnxt/tf_core/tf_device.c\n@@ -47,7 +47,6 @@ tf_dev_bind_p4(struct tf *tfp,\n \tstruct tf_if_tbl_cfg_parms if_tbl_cfg;\n \tstruct tf_global_cfg_cfg_parms global_cfg;\n \n-\tdev_handle->type = TF_DEVICE_TYPE_WH;\n \t/* Initial function initialization */\n \tdev_handle->ops = &tf_dev_ops_p4_init;\n \n@@ -90,7 +89,10 @@ tf_dev_bind_p4(struct tf *tfp,\n \t * EEM\n \t */\n \tem_cfg.num_elements = TF_EM_TBL_TYPE_MAX;\n-\tem_cfg.cfg = tf_em_ext_p4;\n+\tif (dev_handle->type == TF_DEVICE_TYPE_WH)\n+\t\tem_cfg.cfg = tf_em_ext_p4;\n+\telse\n+\t\tem_cfg.cfg = tf_em_ext_p45;\n \tem_cfg.resources = resources;\n \tem_cfg.mem_type = TF_EEM_MEM_TYPE_HOST;\n \trc = tf_em_ext_common_bind(tfp, &em_cfg);\n@@ -241,6 +243,8 @@ tf_dev_bind(struct tf *tfp __rte_unused,\n {\n \tswitch (type) {\n \tcase TF_DEVICE_TYPE_WH:\n+\tcase TF_DEVICE_TYPE_SR:\n+\t\tdev_handle->type = type;\n \t\treturn tf_dev_bind_p4(tfp,\n \t\t\t\t shadow_copy,\n \t\t\t\t resources,\n@@ -258,6 +262,7 @@ tf_dev_unbind(struct tf *tfp,\n {\n \tswitch (dev_handle->type) {\n \tcase TF_DEVICE_TYPE_WH:\n+\tcase TF_DEVICE_TYPE_SR:\n \t\treturn tf_dev_unbind_p4(tfp);\n \tdefault:\n \t\tTFP_DRV_LOG(ERR,\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c\nindex fe8dec3af..0344565d7 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c\n@@ -28,13 +28,32 @@\n * - (-EINVAL) on failure.\n */\n static int\n-tf_dev_p4_get_max_types(struct tf *tfp __rte_unused,\n+tf_dev_p4_get_max_types(struct tf *tfp,\n \t\t\tuint16_t *max_types)\n {\n-\tif (max_types == NULL)\n+\tstruct tf_session *tfs;\n+\tstruct tf_dev_info *dev;\n+\tint rc;\n+\n+\tif (max_types == NULL || tfp == NULL)\n \t\treturn -EINVAL;\n \n-\t*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;\n+\t/* Retrieve the session information */\n+\trc = tf_session_get_session(tfp, &tfs);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Retrieve the device information */\n+\trc = tf_session_get_device(tfs, &dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (dev->type == TF_DEVICE_TYPE_WH)\n+\t\t*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;\n+\telse if (dev->type == TF_DEVICE_TYPE_SR)\n+\t\t*max_types = CFA_RESOURCE_TYPE_P45_LAST + 1;\n+\telse\n+\t\treturn -ENODEV;\n \n \treturn 0;\n }\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h\nindex 7e58469a0..aba28fe5f 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.h\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h\n@@ -83,6 +83,12 @@ struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n \t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },\n };\n \n+struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {\n+\t/* CFA_RESOURCE_TYPE_P4_EM_REC */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },\n+};\n+\n struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {\n \t{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },\n \t/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h\nnew file mode 100644\nindex 000000000..016d6e254\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_core/tf_device_p45.h\n@@ -0,0 +1,105 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+#ifndef _TF_DEVICE_P45_H_\n+#define _TF_DEVICE_P45_H_\n+\n+#include <cfa_resource_types.h>\n+\n+#include \"tf_core.h\"\n+#include \"tf_rm.h\"\n+#include \"tf_if_tbl.h\"\n+#include \"tf_global_cfg.h\"\n+\n+struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },\n+\t/* CFA_RESOURCE_TYPE_P45_L2_FUNC */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n+};\n+\n+struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },\n+\t/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n+};\n+\n+struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },\n+\t/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },\n+\t/* CFA_RESOURCE_TYPE_P45_UPAR */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_EPOC */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_METADATA */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_CT_STATE */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_LAG */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_EM_FBK */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_WC_FKB */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t/* CFA_RESOURCE_TYPE_P45_EXT */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n+};\n+\n+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n+\t/* CFA_RESOURCE_TYPE_P45_EM_REC */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },\n+};\n+\n+struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {\n+\t{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },\n+\t/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */\n+\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+};\n+\n+struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {\n+\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },\n+\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },\n+\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },\n+\t{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },\n+\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },\n+\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }\n+};\n+\n+struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {\n+\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },\n+\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },\n+};\n+#endif /* _TF_DEVICE_P45_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h\nindex 2a67e4760..51b08138e 100644\n--- a/drivers/net/bnxt/tf_core/tf_em.h\n+++ b/drivers/net/bnxt/tf_core/tf_em.h\n@@ -9,12 +9,6 @@\n #include \"tf_core.h\"\n #include \"tf_session.h\"\n \n-\n-#define SUPPORT_CFA_HW_P4 1\n-#define SUPPORT_CFA_HW_P58 0\n-#define SUPPORT_CFA_HW_P59 0\n-#define SUPPORT_CFA_HW_ALL 0\n-\n #include \"hcapi/hcapi_cfa_defs.h\"\n \n #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */\n", "prefixes": [ "v2", "01/11" ] }