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GET /api/patches/81569/?format=api
{ "id": 81569, "url": "http://patches.dpdk.org/api/patches/81569/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603185222-14831-44-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603185222-14831-44-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603185222-14831-44-git-send-email-arybchenko@solarflare.com", "date": "2020-10-20T09:13:23", "name": "[v2,43/62] net/sfc: support the concept of RTE switch domains/ports", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b87def1e59e0061fb2e6e72491dbe9aadd3a7960", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603185222-14831-44-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 13137, "url": "http://patches.dpdk.org/api/series/13137/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13137", "date": "2020-10-20T09:12:44", "name": "net/sfc: support flow API transfer rules", "version": 2, "mbox": "http://patches.dpdk.org/series/13137/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81569/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81569/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6513EA04DD;\n\tTue, 20 Oct 2020 11:40:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 67372FCDD;\n\tTue, 20 Oct 2020 11:16:09 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 32930AD39\n for <dev@dpdk.org>; Tue, 20 Oct 2020 11:14:21 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.62])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n B1F6360061 for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:19 +0000 (UTC)", "from us4-mdac16-30.ut7.mdlocal (unknown [10.7.66.140])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id B1FC58009B\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:19 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.66.34])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n E0AF7280059\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:14 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 9686860005B\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:14 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 20 Oct 2020 10:14:01 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 10:14:01 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09K9E1kF028488;\n Tue, 20 Oct 2020 10:14:01 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 2B47E1613AB;\n Tue, 20 Oct 2020 10:14:01 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Ivan Malov <ivan.malov@oktetlabs.ru>", "Date": "Tue, 20 Oct 2020 10:13:23 +0100", "Message-ID": "<1603185222-14831-44-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "References": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>\n <1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-TM-AS-Result": "No-6.415900-8.000000-10", "X-TMASE-MatchedRID": "uf0j0HzgYrMfKML5AJtfLf3HILfxLV/9S6mvV++TKmlxhjGz7lumrwgI\n aaSer6PCk/P0B8S1IYLKHBviWj0QRj09o8PhVkSdW1M77Gh1ugZzmB71otxffG82zvsXichaNF9\n CGqne0yx9o40ln6gi8cGddr3VWQDjIvi8tYxfenGolIr4dI9j7+lUxvXGcRIyBph69XjMbdmAec\n OigRAlta3aC25avUua+WHc8RqHeHV/GxHOvf6lEub3p4cnIXGN2csA2In0nraPiMW+3YzkggTqf\n /Dg2cz8JORm1qaXr4cidYoCHucQNWiqvF73selK9Jn/ZrGuc8HdXhRKGhNdp+ZMicrOlIVJsskC\n J7yz5Px0dwyXsNLGVLSJSoi4LGd3LDvpFRH1bkIPe5gzF3TVt3Hv4qNcyiZVY7Fv3XBzv+HK1N5\n uMH+VUP5er2rP1IKr79lqEzYHnGwEGNruDgdTzRzsdVXXq/9LsGJsaKyZd0TplCKCpVh6EOyrhS\n 15CsznvUaRai4wxazMUkPBkCEgxDpCGMf9ktTQSszr2nuUNKwvXkmKVNgrflTFKQBe714nChY+H\n tJZ2GPE+nTdM2Xui1twxqU1OpW/rFMDyJP7G26a+cpJvTbSHDtwRuVgSp+1RjHvrQ40NxZ+4PU2\n eqLaIsId/fzQe6Zn7+ab+FAmr9v5+oRgEhP056am63kopwnT3WFaxVW7M2ged11F9IsKFK6vdXP\n rzehX5J+kpDMEvF1szYb0YTsqVyQYHMLagAMBngIgpj8eDcAZ1CdBJOsoY8RB0bsfrpPIx1FPlN\n AAmcAkz69GaAoQFqvM9ZiezkVQkc7fz1ZZZHZ0zqrhnMSJ2J6oP1a0mRIj", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--6.415900-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-MDID": "1603185255-ZP00-iT3pe5S", "X-PPE-DISP": "1603185255;ZP00-iT3pe5S", "Subject": "[dpdk-dev] [PATCH v2 43/62] net/sfc: support the concept of RTE\n\tswitch domains/ports", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ivan Malov <ivan.malov@oktetlabs.ru>\n\nA later patch will add support for RTE flow action PORT_ID\nto MAE backend. The driver has to ensure that such actions\nrefer to RTE ethdev instances deployed on top of the same\nphysical device. Also, the driver needs a means to find\nsibling RTE ethdev instances when parsing such actions.\n\nIn order to solve these problems, add a switch infrastructure\nwhich allocates switch domains based on persistence of device\nserial number string across switch ports included in a domain.\nExplain mapping between RTE switch port IDs and MAE endpoints.\n\nSigned-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/net/sfc/meson.build | 1 +\n drivers/net/sfc/sfc_ethdev.c | 7 +\n drivers/net/sfc/sfc_mae.c | 35 +++++\n drivers/net/sfc/sfc_mae.h | 6 +\n drivers/net/sfc/sfc_switch.c | 276 +++++++++++++++++++++++++++++++++++\n drivers/net/sfc/sfc_switch.h | 47 ++++++\n 6 files changed, 372 insertions(+)\n create mode 100644 drivers/net/sfc/sfc_switch.c\n create mode 100644 drivers/net/sfc/sfc_switch.h", "diff": "diff --git a/drivers/net/sfc/meson.build b/drivers/net/sfc/meson.build\nindex 7a893080cb..42b184c29e 100644\n--- a/drivers/net/sfc/meson.build\n+++ b/drivers/net/sfc/meson.build\n@@ -47,6 +47,7 @@ sources = files(\n \t'sfc_tx.c',\n \t'sfc_tso.c',\n \t'sfc_filter.c',\n+\t'sfc_switch.c',\n \t'sfc_mae.c',\n \t'sfc_flow.c',\n \t'sfc_dp.c',\ndiff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c\nindex c0672083ec..107dd0f470 100644\n--- a/drivers/net/sfc/sfc_ethdev.c\n+++ b/drivers/net/sfc/sfc_ethdev.c\n@@ -93,6 +93,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \tstruct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev);\n \tstruct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev);\n \tstruct sfc_rss *rss = &sas->rss;\n+\tstruct sfc_mae *mae = &sa->mae;\n \tuint64_t txq_offloads_def = 0;\n \n \tsfc_log_init(sa, \"entry\");\n@@ -187,6 +188,12 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \tdev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\n \n+\tif (mae->status == SFC_MAE_STATUS_SUPPORTED) {\n+\t\tdev_info->switch_info.name = dev->device->driver->name;\n+\t\tdev_info->switch_info.domain_id = mae->switch_domain_id;\n+\t\tdev_info->switch_info.port_id = mae->switch_port_id;\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/sfc/sfc_mae.c b/drivers/net/sfc/sfc_mae.c\nindex a5800ae722..64cd6b0e9b 100644\n--- a/drivers/net/sfc/sfc_mae.c\n+++ b/drivers/net/sfc/sfc_mae.c\n@@ -15,11 +15,24 @@\n \n #include \"sfc.h\"\n #include \"sfc_log.h\"\n+#include \"sfc_switch.h\"\n+\n+static int\n+sfc_mae_assign_entity_mport(struct sfc_adapter *sa,\n+\t\t\t efx_mport_sel_t *mportp)\n+{\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);\n+\n+\treturn efx_mae_mport_by_pcie_function(encp->enc_pf, encp->enc_vf,\n+\t\t\t\t\t mportp);\n+}\n \n int\n sfc_mae_attach(struct sfc_adapter *sa)\n {\n+\tstruct sfc_mae_switch_port_request switch_port_request = {0};\n \tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);\n+\tefx_mport_sel_t entity_mport;\n \tstruct sfc_mae *mae = &sa->mae;\n \tefx_mae_limits_t limits;\n \tint rc;\n@@ -41,6 +54,25 @@ sfc_mae_attach(struct sfc_adapter *sa)\n \tif (rc != 0)\n \t\tgoto fail_mae_get_limits;\n \n+\tsfc_log_init(sa, \"assign entity MPORT\");\n+\trc = sfc_mae_assign_entity_mport(sa, &entity_mport);\n+\tif (rc != 0)\n+\t\tgoto fail_mae_assign_entity_mport;\n+\n+\tsfc_log_init(sa, \"assign RTE switch domain\");\n+\trc = sfc_mae_assign_switch_domain(sa, &mae->switch_domain_id);\n+\tif (rc != 0)\n+\t\tgoto fail_mae_assign_switch_domain;\n+\n+\tsfc_log_init(sa, \"assign RTE switch port\");\n+\tswitch_port_request.type = SFC_MAE_SWITCH_PORT_INDEPENDENT;\n+\tswitch_port_request.entity_mportp = &entity_mport;\n+\trc = sfc_mae_assign_switch_port(mae->switch_domain_id,\n+\t\t\t\t\t&switch_port_request,\n+\t\t\t\t\t&mae->switch_port_id);\n+\tif (rc != 0)\n+\t\tgoto fail_mae_assign_switch_port;\n+\n \tmae->status = SFC_MAE_STATUS_SUPPORTED;\n \tmae->nb_action_rule_prios_max = limits.eml_max_n_action_prios;\n \tTAILQ_INIT(&mae->action_sets);\n@@ -49,6 +81,9 @@ sfc_mae_attach(struct sfc_adapter *sa)\n \n \treturn 0;\n \n+fail_mae_assign_switch_port:\n+fail_mae_assign_switch_domain:\n+fail_mae_assign_entity_mport:\n fail_mae_get_limits:\n \tefx_mae_fini(sa->nic);\n \ndiff --git a/drivers/net/sfc/sfc_mae.h b/drivers/net/sfc/sfc_mae.h\nindex 3c34d08f88..f92e62dcbe 100644\n--- a/drivers/net/sfc/sfc_mae.h\n+++ b/drivers/net/sfc/sfc_mae.h\n@@ -12,6 +12,8 @@\n \n #include <stdbool.h>\n \n+#include <rte_spinlock.h>\n+\n #include \"efx.h\"\n \n #ifdef __cplusplus\n@@ -45,6 +47,10 @@ enum sfc_mae_status {\n };\n \n struct sfc_mae {\n+\t/** Assigned switch domain identifier */\n+\tuint16_t\t\t\tswitch_domain_id;\n+\t/** Assigned switch port identifier */\n+\tuint16_t\t\t\tswitch_port_id;\n \t/** NIC support for MAE status */\n \tenum sfc_mae_status\t\tstatus;\n \t/** Priority level limit for MAE action rules */\ndiff --git a/drivers/net/sfc/sfc_switch.c b/drivers/net/sfc/sfc_switch.c\nnew file mode 100644\nindex 0000000000..395fc40263\n--- /dev/null\n+++ b/drivers/net/sfc/sfc_switch.c\n@@ -0,0 +1,276 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2019 Solarflare Communications Inc.\n+ *\n+ * This software was jointly developed between OKTET Labs (under contract\n+ * for Solarflare) and Solarflare Communications, Inc.\n+ */\n+\n+#include <stdbool.h>\n+\n+#include <rte_common.h>\n+#include <rte_spinlock.h>\n+\n+#include \"efx.h\"\n+\n+#include \"sfc.h\"\n+#include \"sfc_log.h\"\n+#include \"sfc_switch.h\"\n+\n+/**\n+ * Switch port registry entry.\n+ *\n+ * Drivers aware of RTE switch domains also have to maintain RTE switch\n+ * port IDs for RTE ethdev instances they operate. These IDs are supposed\n+ * to stand for physical interconnect entities, in example, PCIe functions.\n+ *\n+ * In terms of MAE, a physical interconnect entity can be referred to using\n+ * an MPORT selector, that is, a 32-bit value. RTE switch port IDs, in turn,\n+ * are 16-bit values, so indirect mapping has to be maintained:\n+ *\n+ * +--------------------+ +---------------------------------------+\n+ * | RTE switch port ID | ------ | MAE switch port entry |\n+ * +--------------------+ | --------------------- |\n+ * | |\n+ * | Entity (PCIe function) MPORT selector |\n+ * | + |\n+ * | Port type (independent/representor) |\n+ * +---------------------------------------+\n+ *\n+ * This mapping comprises a port type to ensure that RTE switch port ID\n+ * of a represented entity and that of its representor are different in\n+ * the case when the entity gets plugged into DPDK and not into a guest.\n+ */\n+struct sfc_mae_switch_port {\n+\tTAILQ_ENTRY(sfc_mae_switch_port)\tswitch_domain_ports;\n+\n+\t/** Entity (PCIe function) MPORT selector */\n+\tefx_mport_sel_t\t\t\t\tentity_mport;\n+\t/** Port type (independent/representor) */\n+\tenum sfc_mae_switch_port_type\t\ttype;\n+\t/** RTE switch port ID */\n+\tuint16_t\t\t\t\tid;\n+};\n+\n+TAILQ_HEAD(sfc_mae_switch_ports, sfc_mae_switch_port);\n+\n+/**\n+ * Switch domain registry entry.\n+ *\n+ * Even if an RTE ethdev instance gets unplugged, the corresponding\n+ * entry in the switch port registry will not be removed because the\n+ * entity (PCIe function) MPORT is static and cannot change. If this\n+ * RTE ethdev gets plugged back, the entry will be reused, and\n+ * RTE switch port ID will be the same.\n+ */\n+struct sfc_mae_switch_domain {\n+\tTAILQ_ENTRY(sfc_mae_switch_domain)\tentries;\n+\n+\t/** HW switch ID */\n+\tstruct sfc_hw_switch_id\t\t\t*hw_switch_id;\n+\t/** The number of ports in the switch port registry */\n+\tunsigned int\t\t\t\tnb_ports;\n+\t/** Switch port registry */\n+\tstruct sfc_mae_switch_ports\t\tports;\n+\t/** RTE switch domain ID allocated for a group of devices */\n+\tuint16_t\t\t\t\tid;\n+};\n+\n+TAILQ_HEAD(sfc_mae_switch_domains, sfc_mae_switch_domain);\n+\n+/**\n+ * MAE representation of RTE switch infrastructure.\n+ *\n+ * It is possible that an RTE flow API client tries to insert a rule\n+ * referencing an RTE ethdev deployed on top of a different physical\n+ * device (it may belong to the same vendor or not). This particular\n+ * driver/engine cannot support this and has to turn down such rules.\n+ *\n+ * Technically, it's HW switch identifier which, if queried for each\n+ * RTE ethdev instance, indicates relationship between the instances.\n+ * In the meantime, RTE flow API clients also need to somehow figure\n+ * out relationship between RTE ethdev instances in advance.\n+ *\n+ * The concept of RTE switch domains resolves this issue. The driver\n+ * maintains a static list of switch domains which is easy to browse,\n+ * and each RTE ethdev fills RTE switch parameters in device\n+ * information structure which is made available to clients.\n+ *\n+ * Even if all RTE ethdev instances belonging to a switch domain get\n+ * unplugged, the corresponding entry in the switch domain registry\n+ * will not be removed because the corresponding HW switch exists\n+ * regardless of its ports being plugged to DPDK or kept aside.\n+ * If a port gets plugged back to DPDK, the corresponding\n+ * RTE ethdev will indicate the same RTE switch domain ID.\n+ */\n+struct sfc_mae_switch {\n+\t/** A lock to protect the whole structure */\n+\trte_spinlock_t\t\t\tlock;\n+\t/** Switch domain registry */\n+\tstruct sfc_mae_switch_domains\tdomains;\n+};\n+\n+static struct sfc_mae_switch sfc_mae_switch = {\n+\t.lock = RTE_SPINLOCK_INITIALIZER,\n+\t.domains = TAILQ_HEAD_INITIALIZER(sfc_mae_switch.domains),\n+};\n+\n+\n+/* This function expects to be called only when the lock is held */\n+static struct sfc_mae_switch_domain *\n+sfc_mae_find_switch_domain_by_id(uint16_t switch_domain_id)\n+{\n+\tstruct sfc_mae_switch_domain *domain;\n+\n+\tSFC_ASSERT(rte_spinlock_is_locked(&sfc_mae_switch.lock));\n+\n+\tTAILQ_FOREACH(domain, &sfc_mae_switch.domains, entries) {\n+\t\tif (domain->id == switch_domain_id)\n+\t\t\treturn domain;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/* This function expects to be called only when the lock is held */\n+static struct sfc_mae_switch_domain *\n+sfc_mae_find_switch_domain_by_hw_switch_id(const struct sfc_hw_switch_id *id)\n+{\n+\tstruct sfc_mae_switch_domain *domain;\n+\n+\tSFC_ASSERT(rte_spinlock_is_locked(&sfc_mae_switch.lock));\n+\n+\tTAILQ_FOREACH(domain, &sfc_mae_switch.domains, entries) {\n+\t\tif (sfc_hw_switch_ids_equal(domain->hw_switch_id, id))\n+\t\t\treturn domain;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+int\n+sfc_mae_assign_switch_domain(struct sfc_adapter *sa,\n+\t\t\t uint16_t *switch_domain_id)\n+{\n+\tstruct sfc_hw_switch_id *hw_switch_id;\n+\tstruct sfc_mae_switch_domain *domain;\n+\tint rc;\n+\n+\trte_spinlock_lock(&sfc_mae_switch.lock);\n+\n+\trc = sfc_hw_switch_id_init(sa, &hw_switch_id);\n+\tif (rc != 0)\n+\t\tgoto fail_hw_switch_id_init;\n+\n+\tdomain = sfc_mae_find_switch_domain_by_hw_switch_id(hw_switch_id);\n+\tif (domain != NULL) {\n+\t\tsfc_hw_switch_id_fini(sa, hw_switch_id);\n+\t\tgoto done;\n+\t}\n+\n+\tdomain = rte_zmalloc(\"sfc_mae_switch_domain\", sizeof(*domain), 0);\n+\tif (domain == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail_mem_alloc;\n+\t}\n+\n+\t/*\n+\t * This code belongs to driver init path, that is, negation is\n+\t * done at the end of the path by sfc_eth_dev_init(). RTE APIs\n+\t * negate error codes, so drop negation here.\n+\t */\n+\trc = -rte_eth_switch_domain_alloc(&domain->id);\n+\tif (rc != 0)\n+\t\tgoto fail_domain_alloc;\n+\n+\tdomain->hw_switch_id = hw_switch_id;\n+\n+\tTAILQ_INIT(&domain->ports);\n+\n+\tTAILQ_INSERT_TAIL(&sfc_mae_switch.domains, domain, entries);\n+\n+done:\n+\t*switch_domain_id = domain->id;\n+\n+\trte_spinlock_unlock(&sfc_mae_switch.lock);\n+\n+\treturn 0;\n+\n+fail_domain_alloc:\n+\trte_free(domain);\n+\n+fail_mem_alloc:\n+\tsfc_hw_switch_id_fini(sa, hw_switch_id);\n+\trte_spinlock_unlock(&sfc_mae_switch.lock);\n+\n+fail_hw_switch_id_init:\n+\treturn rc;\n+}\n+\n+/* This function expects to be called only when the lock is held */\n+static struct sfc_mae_switch_port *\n+sfc_mae_find_switch_port_by_entity(const struct sfc_mae_switch_domain *domain,\n+\t\t\t\t const efx_mport_sel_t *entity_mportp,\n+\t\t\t\t enum sfc_mae_switch_port_type type)\n+{\n+\tstruct sfc_mae_switch_port *port;\n+\n+\tSFC_ASSERT(rte_spinlock_is_locked(&sfc_mae_switch.lock));\n+\n+\tTAILQ_FOREACH(port, &domain->ports, switch_domain_ports) {\n+\t\tif (port->entity_mport.sel == entity_mportp->sel &&\n+\t\t port->type == type)\n+\t\t\treturn port;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+int\n+sfc_mae_assign_switch_port(uint16_t switch_domain_id,\n+\t\t\t const struct sfc_mae_switch_port_request *req,\n+\t\t\t uint16_t *switch_port_id)\n+{\n+\tstruct sfc_mae_switch_domain *domain;\n+\tstruct sfc_mae_switch_port *port;\n+\tint rc;\n+\n+\trte_spinlock_lock(&sfc_mae_switch.lock);\n+\n+\tdomain = sfc_mae_find_switch_domain_by_id(switch_domain_id);\n+\tif (domain == NULL) {\n+\t\trc = EINVAL;\n+\t\tgoto fail_find_switch_domain_by_id;\n+\t}\n+\n+\tport = sfc_mae_find_switch_port_by_entity(domain, req->entity_mportp,\n+\t\t\t\t\t\t req->type);\n+\tif (port != NULL)\n+\t\tgoto done;\n+\n+\tport = rte_zmalloc(\"sfc_mae_switch_port\", sizeof(*port), 0);\n+\tif (port == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail_mem_alloc;\n+\t}\n+\n+\tport->entity_mport.sel = req->entity_mportp->sel;\n+\tport->type = req->type;\n+\n+\tport->id = (domain->nb_ports++);\n+\n+\tTAILQ_INSERT_TAIL(&domain->ports, port, switch_domain_ports);\n+\n+done:\n+\t*switch_port_id = port->id;\n+\n+\trte_spinlock_unlock(&sfc_mae_switch.lock);\n+\n+\treturn 0;\n+\n+fail_mem_alloc:\n+fail_find_switch_domain_by_id:\n+\trte_spinlock_unlock(&sfc_mae_switch.lock);\n+\treturn rc;\n+}\ndiff --git a/drivers/net/sfc/sfc_switch.h b/drivers/net/sfc/sfc_switch.h\nnew file mode 100644\nindex 0000000000..9845ac8801\n--- /dev/null\n+++ b/drivers/net/sfc/sfc_switch.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2019 Solarflare Communications Inc.\n+ *\n+ * This software was jointly developed between OKTET Labs (under contract\n+ * for Solarflare) and Solarflare Communications, Inc.\n+ */\n+\n+#ifndef _SFC_SWITCH_H\n+#define _SFC_SWITCH_H\n+\n+#include <stdint.h>\n+\n+#include \"efx.h\"\n+\n+#include \"sfc.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** Options for MAE switch port type */\n+enum sfc_mae_switch_port_type {\n+\t/**\n+\t * The switch port is operated by a self-sufficient RTE ethdev\n+\t * and thus refers to its underlying PCIe function\n+\t */\n+\tSFC_MAE_SWITCH_PORT_INDEPENDENT = 0,\n+};\n+\n+struct sfc_mae_switch_port_request {\n+\tenum sfc_mae_switch_port_type\t\ttype;\n+\tconst efx_mport_sel_t\t\t\t*entity_mportp;\n+};\n+\n+int sfc_mae_assign_switch_domain(struct sfc_adapter *sa,\n+\t\t\t\t uint16_t *switch_domain_id);\n+\n+int sfc_mae_assign_switch_port(uint16_t switch_domain_id,\n+\t\t\t const struct sfc_mae_switch_port_request *req,\n+\t\t\t uint16_t *switch_port_id);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+#endif /* _SFC_SWITCH_H */\n", "prefixes": [ "v2", "43/62" ] }