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GET /api/patches/81496/?format=api
{ "id": 81496, "url": "http://patches.dpdk.org/api/patches/81496/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603183709-23420-61-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603183709-23420-61-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603183709-23420-61-git-send-email-arybchenko@solarflare.com", "date": "2020-10-20T08:48:27", "name": "[60/62] common/sfc_efx/base: support outer rule provisioning", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cb71e77960afd05827dd2a04d0056413b54c46ea", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603183709-23420-61-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 13132, "url": "http://patches.dpdk.org/api/series/13132/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13132", "date": "2020-10-20T08:47:30", "name": "net/sfc: support flow API transfer rules", "version": 1, "mbox": "http://patches.dpdk.org/series/13132/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81496/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/81496/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6FF5FA04DD;\n\tTue, 20 Oct 2020 11:08:47 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 665F0CA36;\n\tTue, 20 Oct 2020 10:50:25 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id E166BBBB4\n for <dev@dpdk.org>; Tue, 20 Oct 2020 10:49:08 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.60])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n B1F8C6006D for <dev@dpdk.org>; Tue, 20 Oct 2020 08:49:08 +0000 (UTC)", "from us4-mdac16-27.ut7.mdlocal (unknown [10.7.66.59])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id B154A2009A\n for <dev@dpdk.org>; Tue, 20 Oct 2020 08:49:08 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.66.41])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 055391C0051\n for <dev@dpdk.org>; Tue, 20 Oct 2020 08:49:08 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n AD1294C005C\n for <dev@dpdk.org>; Tue, 20 Oct 2020 08:49:07 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 20 Oct 2020 09:48:51 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 09:48:51 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09K8mp0x030933;\n Tue, 20 Oct 2020 09:48:51 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id ED27D1613AB;\n Tue, 20 Oct 2020 09:48:50 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<y@solarflare.com>", "CC": "<dev@dpdk.org>, Ivan Malov <ivan.malov@oktetlabs.ru>", "Date": "Tue, 20 Oct 2020 09:48:27 +0100", "Message-ID": "<1603183709-23420-61-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>", "References": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-TM-AS-Result": "No-1.389900-8.000000-10", "X-TMASE-MatchedRID": "IaQsIsqmO9Q/REwOA9OGtQ9rVnOZ7Na2aeMaKzvXUpljLp8Cm8vwF12O\n RX0B8+qTT1fsjZmF+qzm9S/0eIQUb+ox2xGkyLxhPwKTD1v8YV4yieckNRsVx8LR/1CaEfqJR+X\n 4fj4ypMn/aNNKUC1FYcwhBUgPv4Ps/uudbUpvyZHJ1E/nrJFED3vEgoSBmr8BkY8eITaSJPibfn\n TDz+a2OX2dcFgFzv71EtRm78gcrDHtzSKzUmDUV8ewkPVzkoGNqb3/o5s+OcO1E+HbdRuHYHd7b\n ci/LVuNdR9IuTvvB94PtqKIlA3hYsKfN8lhf0yu7+azOEjVWOOiIpNv3rjMdeD3XFrJfgvzIX4K\n 6awSpd7i8zVgXoAltsIJ+4gwXrEtWBd6ltyXuvs2k0Gbj8GCy2/SjwtHaDeMFV/rwU4HCDgI0eU\n FZmDyOnKgTZRqNH0y6gumGf9mHG+4RKcahf4Y41IMFAxTLLN5ViQAkXSslhW9Tbikt9AWZ0CBSG\n S7bIBtA1B/p1SzcogrKiD/U8b7SaNbPJBuvLaLftwZ3X11IV0=", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10-1.389900-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-MDID": "1603183748-Ppl1c9n4fEPE", "X-PPE-DISP": "1603183748;Ppl1c9n4fEPE", "Subject": "[dpdk-dev] [PATCH 60/62] common/sfc_efx/base: support outer rule\n\tprovisioning", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ivan Malov <ivan.malov@oktetlabs.ru>\n\nLet the client insert / remove outer rules.\nLet the client refer to an inserted outer rule in a match\nspecification of type ACTION.\n\nSigned-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx.h | 21 ++\n drivers/common/sfc_efx/base/efx_mae.c | 197 ++++++++++++++++++\n .../sfc_efx/rte_common_sfc_efx_version.map | 3 +\n 3 files changed, 221 insertions(+)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h\nindex c6472eaf76..3b40e28b4e 100644\n--- a/drivers/common/sfc_efx/base/efx.h\n+++ b/drivers/common/sfc_efx/base/efx.h\n@@ -4137,6 +4137,7 @@ typedef enum efx_mae_field_id_e {\n \tEFX_MAE_FIELD_ENC_L4_SPORT_BE,\n \tEFX_MAE_FIELD_ENC_L4_DPORT_BE,\n \tEFX_MAE_FIELD_ENC_VNET_ID_BE,\n+\tEFX_MAE_FIELD_OUTER_RULE_ID,\n \n \tEFX_MAE_FIELD_NIDS\n } efx_mae_field_id_t;\n@@ -4298,6 +4299,26 @@ typedef struct efx_mae_rule_id_s {\n \tuint32_t id;\n } efx_mae_rule_id_t;\n \n+LIBEFX_API\n+extern\t__checkReturn\t\tefx_rc_t\n+efx_mae_outer_rule_insert(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tconst efx_mae_match_spec_t *spec,\n+\t__in\t\t\tefx_tunnel_protocol_t encap_type,\n+\t__out\t\t\tefx_mae_rule_id_t *or_idp);\n+\n+LIBEFX_API\n+extern\t__checkReturn\t\tefx_rc_t\n+efx_mae_outer_rule_remove(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tconst efx_mae_rule_id_t *or_idp);\n+\n+LIBEFX_API\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_outer_rule_id_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tconst efx_mae_rule_id_t *or_idp);\n+\n /* Action set ID */\n typedef struct efx_mae_aset_id_s {\n \tuint32_t id;\ndiff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c\nindex 45a796fdad..fbf56b14ce 100644\n--- a/drivers/common/sfc_efx/base/efx_mae.c\n+++ b/drivers/common/sfc_efx/base/efx_mae.c\n@@ -446,6 +446,7 @@ typedef enum efx_mae_field_cap_id_e {\n \tEFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,\n \tEFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,\n \tEFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,\n+\tEFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,\n \n \tEFX_MAE_FIELD_CAP_NIDS\n } efx_mae_field_cap_id_t;\n@@ -506,6 +507,7 @@ static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {\n \tEFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),\n \tEFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),\n \tEFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),\n+\tEFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),\n \n #undef EFX_MAE_MV_DESC\n };\n@@ -1380,6 +1382,201 @@ efx_mae_match_specs_class_cmp(\n \n \treturn (0);\n \n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\tefx_rc_t\n+efx_mae_outer_rule_insert(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tconst efx_mae_match_spec_t *spec,\n+\t__in\t\t\tefx_tunnel_protocol_t encap_type,\n+\t__out\t\t\tefx_mae_rule_id_t *or_idp)\n+{\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n+\tefx_mcdi_req_t req;\n+\tEFX_MCDI_DECLARE_BUF(payload,\n+\t MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,\n+\t MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);\n+\tuint32_t encap_type_mcdi;\n+\tefx_mae_rule_id_t or_id;\n+\tsize_t offset;\n+\tefx_rc_t rc;\n+\n+\tEFX_STATIC_ASSERT(sizeof (or_idp->id) ==\n+\t MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);\n+\n+\tEFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==\n+\t MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);\n+\n+\tif (encp->enc_mae_supported == B_FALSE) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (spec->emms_type != EFX_MAE_RULE_OUTER) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\tswitch (encap_type) {\n+\tcase EFX_TUNNEL_PROTOCOL_NONE:\n+\t\tencap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;\n+\t\tbreak;\n+\tcase EFX_TUNNEL_PROTOCOL_VXLAN:\n+\t\tencap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;\n+\t\tbreak;\n+\tcase EFX_TUNNEL_PROTOCOL_GENEVE:\n+\t\tencap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;\n+\t\tbreak;\n+\tcase EFX_TUNNEL_PROTOCOL_NVGRE:\n+\t\tencap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;\n+\t\tbreak;\n+\tdefault:\n+\t\trc = ENOTSUP;\n+\t\tgoto fail3;\n+\t}\n+\n+\treq.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;\n+\n+\tMCDI_IN_SET_DWORD(req,\n+\t MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);\n+\n+\tMCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);\n+\n+\t/*\n+\t * Mask-value pairs have been stored in the byte order needed for the\n+\t * MCDI request and are thus safe to be copied directly to the buffer.\n+\t * The library cares about byte order in efx_mae_match_spec_field_set().\n+\t */\n+\tEFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=\n+\t MAE_ENC_FIELD_PAIRS_LEN);\n+\toffset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;\n+\tmemcpy(payload + offset, spec->emms_mask_value_pairs.outer,\n+\t MAE_ENC_FIELD_PAIRS_LEN);\n+\n+\tefx_mcdi_execute(enp, &req);\n+\n+\tif (req.emr_rc != 0) {\n+\t\trc = req.emr_rc;\n+\t\tgoto fail4;\n+\t}\n+\n+\tif (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {\n+\t\trc = EMSGSIZE;\n+\t\tgoto fail5;\n+\t}\n+\n+\tor_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);\n+\tif (or_id.id == EFX_MAE_RSRC_ID_INVALID) {\n+\t\trc = ENOENT;\n+\t\tgoto fail6;\n+\t}\n+\n+\tor_idp->id = or_id.id;\n+\n+\treturn (0);\n+\n+fail6:\n+\tEFSYS_PROBE(fail6);\n+fail5:\n+\tEFSYS_PROBE(fail5);\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\tefx_rc_t\n+efx_mae_outer_rule_remove(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tconst efx_mae_rule_id_t *or_idp)\n+{\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n+\tefx_mcdi_req_t req;\n+\tEFX_MCDI_DECLARE_BUF(payload,\n+\t MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),\n+\t MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));\n+\tefx_rc_t rc;\n+\n+\tif (encp->enc_mae_supported == B_FALSE) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\treq.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);\n+\n+\tMCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);\n+\n+\tefx_mcdi_execute(enp, &req);\n+\n+\tif (req.emr_rc != 0) {\n+\t\trc = req.emr_rc;\n+\t\tgoto fail2;\n+\t}\n+\n+\tif (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=\n+\t or_idp->id) {\n+\t\t/* Firmware failed to remove the outer rule. */\n+\t\trc = EAGAIN;\n+\t\tgoto fail3;\n+\t}\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_outer_rule_id_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tconst efx_mae_rule_id_t *or_idp)\n+{\n+\tuint32_t full_mask = UINT32_MAX;\n+\tefx_rc_t rc;\n+\n+\tif (spec->emms_type != EFX_MAE_RULE_ACTION) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (or_idp == NULL) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\trc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,\n+\t sizeof (or_idp->id), (const uint8_t *)&or_idp->id,\n+\t sizeof (full_mask), (const uint8_t *)&full_mask);\n+\tif (rc != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n fail2:\n \tEFSYS_PROBE(fail2);\n fail1:\ndiff --git a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\nindex 07b3b6371b..403feeaf11 100644\n--- a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n+++ b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n@@ -106,10 +106,13 @@ INTERNAL {\n \tefx_mae_match_spec_init;\n \tefx_mae_match_spec_is_valid;\n \tefx_mae_match_spec_mport_set;\n+\tefx_mae_match_spec_outer_rule_id_set;\n \tefx_mae_match_specs_class_cmp;\n \tefx_mae_match_specs_equal;\n \tefx_mae_mport_by_pcie_function;\n \tefx_mae_mport_by_phy_port;\n+\tefx_mae_outer_rule_insert;\n+\tefx_mae_outer_rule_remove;\n \n \tefx_mcdi_fini;\n \tefx_mcdi_get_proxy_handle;\n", "prefixes": [ "60/62" ] }