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{
    "id": 81466,
    "url": "http://patches.dpdk.org/api/patches/81466/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603183709-23420-2-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1603183709-23420-2-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1603183709-23420-2-git-send-email-arybchenko@solarflare.com",
    "date": "2020-10-20T08:47:28",
    "name": "[01/62] common/sfc_efx/base: add MAE definitions to MCDI",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a6d8892957fb49f8c58424d1653d203b3d66451f",
    "submitter": {
        "id": 607,
        "url": "http://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603183709-23420-2-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [
        {
            "id": 13132,
            "url": "http://patches.dpdk.org/api/series/13132/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13132",
            "date": "2020-10-20T08:47:30",
            "name": "net/sfc: support flow API transfer rules",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/13132/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/81466/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/81466/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        ],
        "X-Virus-Scanned": "Proofpoint Essentials engine",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<y@solarflare.com>",
        "CC": "<dev@dpdk.org>",
        "Date": "Tue, 20 Oct 2020 09:47:28 +0100",
        "Message-ID": "<1603183709-23420-2-git-send-email-arybchenko@solarflare.com>",
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        "References": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>",
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        "X-PPE-DISP": "1603183742;o4LB8wiln2E6",
        "Subject": "[dpdk-dev] [PATCH 01/62] common/sfc_efx/base: add MAE definitions\n\tto MCDI",
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    "content": "MAE stands for Match-Action-Engine and will be used to\nsupport rte_flow API transfer rules.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/common/sfc_efx/base/efx_regs_mcdi.h | 2232 +++++++++++++++++++\n 1 file changed, 2232 insertions(+)",
    "diff": "diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\nindex f31a25e4ff..7125d053e8 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n@@ -410,6 +410,151 @@\n #define\tMC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff\n #define\tMC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */\n \n+/* MAE_FIELD_SUPPORT_STATUS enum */\n+/* enum: The NIC does not support this field. The driver must ensure that any\n+ * mask associated with this field in a match rule is zeroed. The NIC may\n+ * either reject requests with an invalid mask for such a field, or may assume\n+ * that the mask is zero. (This category only exists to describe behaviour for\n+ * fields that a newer driver might know about but that older firmware does\n+ * not. It is recommended that firmware report MAE_FIELD_FIELD_MATCH_NEVER for\n+ * all match fields defined at the time of its compilation. If a driver see a\n+ * field support status value that it does not recognise, it must treat that\n+ * field as thought the field was reported as MAE_FIELD_SUPPORTED_MATCH_NEVER,\n+ * and must never set a non-zero mask value for this field.\n+ */\n+#define\tMAE_FIELD_UNSUPPORTED 0x0\n+/* enum: The NIC supports this field, but cannot use it in a match rule. The\n+ * driver must ensure that any mask for such a field in a match rule is zeroed.\n+ * The NIC will reject requests with an invalid mask for such a field.\n+ */\n+#define\tMAE_FIELD_SUPPORTED_MATCH_NEVER 0x1\n+/* enum: The NIC supports this field, and must use it in all match rules. The\n+ * driver must ensure that any mask for such a field is all ones. The NIC will\n+ * reject requests with an invalid mask for such a field.\n+ */\n+#define\tMAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2\n+/* enum: The NIC supports this field, and may optionally use it in match rules.\n+ * The driver must ensure that any mask for such a field is either all zeroes\n+ * or all ones. The NIC will reject requests with an invalid mask for such a\n+ * field.\n+ */\n+#define\tMAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3\n+/* enum: The NIC supports this field, and may optionally use it in match rules.\n+ * The driver must ensure that any mask for such a field is either all zeroes\n+ * or a consecutive set of ones following by all zeroes (starting from MSB).\n+ * The NIC will reject requests with an invalid mask for such a field.\n+ */\n+#define\tMAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4\n+/* enum: The NIC supports this field, and may optionally use it in match rules.\n+ * The driver may provide an arbitrary mask for such a field.\n+ */\n+#define\tMAE_FIELD_SUPPORTED_MATCH_MASK 0x5\n+\n+/* MAE_FIELD enum: NB: this enum shares namespace with the support status enum.\n+ */\n+/* enum: Source mport upon entering the MAE. */\n+#define\tMAE_FIELD_INGRESS_PORT 0x0\n+#define\tMAE_FIELD_MARK 0x1 /* enum */\n+/* enum: Table ID used in action rule. Initially zero, can be changed in action\n+ * rule response.\n+ */\n+#define\tMAE_FIELD_RECIRC_ID 0x2\n+#define\tMAE_FIELD_IS_IP_FRAG 0x3 /* enum */\n+#define\tMAE_FIELD_DO_CT 0x4 /* enum */\n+#define\tMAE_FIELD_CT_HIT 0x5 /* enum */\n+/* enum: Undefined unless CT_HIT=1. */\n+#define\tMAE_FIELD_CT_MARK 0x6\n+/* enum: Undefined unless DO_CT=1. */\n+#define\tMAE_FIELD_CT_DOMAIN 0x7\n+/* enum: Undefined unless CT_HIT=1. */\n+#define\tMAE_FIELD_CT_PRIVATE_FLAGS 0x8\n+/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */\n+#define\tMAE_FIELD_IS_FROM_NETWORK 0x9\n+#define\tMAE_FIELD_ETHER_TYPE 0x21 /* enum */\n+#define\tMAE_FIELD_VLAN0_TCI 0x22 /* enum */\n+#define\tMAE_FIELD_VLAN0_PROTO 0x23 /* enum */\n+#define\tMAE_FIELD_VLAN1_TCI 0x24 /* enum */\n+#define\tMAE_FIELD_VLAN1_PROTO 0x25 /* enum */\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_ETH_SADDR 0x28\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_ETH_DADDR 0x29\n+/* enum: Inner when encap. NB: IPv4 and IPv6 fields are mutually exclusive. */\n+#define\tMAE_FIELD_SRC_IP4 0x2a\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_SRC_IP6 0x2b\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_DST_IP4 0x2c\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_DST_IP6 0x2d\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_IP_PROTO 0x2e\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_IP_TOS 0x2f\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_IP_TTL 0x30\n+/* enum: Inner when encap TODO: how this is defined? The raw flags +\n+ * frag_offset from the packet, or some derived value more amenable to ternary\n+ * matching? TODO: there was a proposal for driver-allocation fields. The\n+ * driver would provide some instruction for how to extract given field values,\n+ * and would be given a field id in return. It could then use that field id in\n+ * its matches. This feels like it would be extremely hard to implement in\n+ * hardware, but I mention it for completeness.\n+ */\n+#define\tMAE_FIELD_IP_FLAGS 0x31\n+/* enum: Ports (UDP, TCP) Inner when encap */\n+#define\tMAE_FIELD_L4_SPORT 0x32\n+/* enum: Ports (UDP, TCP) Inner when encap */\n+#define\tMAE_FIELD_L4_DPORT 0x33\n+/* enum: Inner when encap */\n+#define\tMAE_FIELD_TCP_FLAGS 0x34\n+/* enum: The type of encapsulated used for this packet. Value as per\n+ * ENCAP_TYPE_*.\n+ */\n+#define\tMAE_FIELD_ENCAP_TYPE 0x3f\n+/* enum: The ID of the outer rule that marked this packet as encapsulated.\n+ * Useful for implicitly matching on outer fields.\n+ */\n+#define\tMAE_FIELD_OUTER_RULE_ID 0x40\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_ETHER_TYPE 0x41\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_VLAN0_TCI 0x42\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_VLAN0_PROTO 0x43\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_VLAN1_TCI 0x44\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_VLAN1_PROTO 0x45\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_ETH_SADDR 0x48\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_ETH_DADDR 0x49\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_SRC_IP4 0x4a\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_SRC_IP6 0x4b\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_DST_IP4 0x4c\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_DST_IP6 0x4d\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_IP_PROTO 0x4e\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_IP_TOS 0x4f\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_IP_TTL 0x50\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_IP_FLAGS 0x51\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_L4_SPORT 0x52\n+/* enum: Outer; only present when encap */\n+#define\tMAE_FIELD_ENC_L4_DPORT 0x53\n+/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Outer; only present when\n+ * encap\n+ */\n+#define\tMAE_FIELD_ENC_VNET_ID 0x54\n+\n /* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will\n  * be parsed to an inner frame. Other values are reserved. Unknown values\n  * should be treated same as NONE.\n@@ -25644,6 +25789,900 @@\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0\n #define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4\n \n+/* MAE_FIELD_FLAGS structuredef */\n+#define\tMAE_FIELD_FLAGS_LEN 4\n+#define\tMAE_FIELD_FLAGS_FLAT_OFST 0\n+#define\tMAE_FIELD_FLAGS_FLAT_LEN 4\n+#define\tMAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0\n+#define\tMAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0\n+#define\tMAE_FIELD_FLAGS_SUPPORT_STATUS_WIDTH 6\n+#define\tMAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0\n+#define\tMAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_LBN 6\n+#define\tMAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_WIDTH 1\n+#define\tMAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0\n+#define\tMAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_LBN 7\n+#define\tMAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_WIDTH 1\n+#define\tMAE_FIELD_FLAGS_FLAT_LBN 0\n+#define\tMAE_FIELD_FLAGS_FLAT_WIDTH 32\n+\n+/* MAE_ENC_FIELD_PAIRS structuredef: Mask and value pairs for all fields that\n+ * it makes sense to use to determine the encapsulation type of a packet. Its\n+ * intended use is to keep a common packing of fields across multiple MCDI\n+ * commands, keeping things inherently sychronised and allowing code shared. To\n+ * use in an MCDI command, the command should end with a variable length byte\n+ * array populated with this structure. Do not extend this structure. Instead,\n+ * create _Vx versions with the necessary fields appended. That way, the\n+ * existing semantics for extending MCDI commands are preserved.\n+ */\n+#define\tMAE_ENC_FIELD_PAIRS_LEN 156\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32\n+#define\tMAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_OFST 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LBN 64\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 10\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 80\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_OFST 12\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LBN 96\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 14\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 112\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_OFST 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LBN 128\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 18\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 144\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_OFST 20\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LBN 160\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 22\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 176\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_OFST 24\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LBN 192\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 26\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 208\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_OFST 28\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LEN 6\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LBN 224\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 34\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 272\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_OFST 40\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LEN 6\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LBN 320\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 46\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 368\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_OFST 52\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LBN 416\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 56\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 448\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_OFST 60\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LEN 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LBN 480\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_WIDTH 128\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 76\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 608\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_OFST 92\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LBN 736\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_OFST 96\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LBN 768\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_OFST 100\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LEN 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LBN 800\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_WIDTH 128\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_OFST 116\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LBN 928\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_OFST 132\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LBN 1056\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_OFST 133\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LBN 1064\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_OFST 134\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LBN 1072\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_OFST 135\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LBN 1080\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_OFST 136\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LBN 1088\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_OFST 137\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 144\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 1152\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_OFST 148\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LBN 1184\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 150\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 1200\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_OFST 152\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LBN 1216\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_WIDTH 16\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 154\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 1232\n+#define\tMAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16\n+\n+/* MAE_FIELD_MASK_VALUE_PAIRS structuredef: Mask and value pairs for all fields\n+ * currently defined. Same semantics as MAE_ENC_FIELD_PAIRS.\n+ */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_LEN 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_OFST 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_LBN 64\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_OFST 12\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LBN 96\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_OFST 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LBN 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_OFST 18\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LBN 144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_OFST 20\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LBN 160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_OFST 22\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LBN 176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_OFST 24\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LBN 192\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_OFST 26\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LBN 208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_OFST 28\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LBN 224\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_OFST 30\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LBN 240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_OFST 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LBN 256\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_OFST 34\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LBN 272\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_OFST 36\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LBN 288\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_OFST 42\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LBN 336\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_OFST 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LBN 384\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_OFST 54\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LBN 432\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_OFST 60\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LBN 480\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_OFST 64\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LBN 512\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_OFST 68\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LBN 544\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_OFST 84\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LBN 672\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_OFST 100\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LBN 800\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_OFST 104\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LBN 832\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_OFST 108\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LBN 864\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_OFST 124\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LBN 992\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_OFST 140\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LBN 1120\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_OFST 141\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LBN 1128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_OFST 142\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LBN 1136\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_OFST 143\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LBN 1144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_OFST 144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LBN 1152\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_OFST 145\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LBN 1160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_OFST 148\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LBN 1184\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_OFST 152\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LBN 1216\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_OFST 156\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LBN 1248\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_OFST 158\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LBN 1264\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_OFST 160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LBN 1280\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_OFST 162\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LBN 1296\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_OFST 164\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LBN 1312\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_OFST 166\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LBN 1328\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_OFST 168\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LBN 1344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_OFST 172\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LBN 1376\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_OFST 176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LBN 1408\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_OFST 180\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LBN 1440\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_OFST 184\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LBN 1472\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 188\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 1504\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_OFST 192\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LBN 1536\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 194\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 1552\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_OFST 196\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LBN 1568\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 198\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 1584\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_OFST 200\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LBN 1600\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 202\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 1616\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_OFST 204\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LBN 1632\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 206\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 1648\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_OFST 208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LBN 1664\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 214\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 1712\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_OFST 220\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LBN 1760\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 226\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 1808\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_OFST 232\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LBN 1856\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 236\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 1888\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_OFST 240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LBN 1920\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 256\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 2048\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_OFST 272\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LBN 2176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_OFST 276\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LBN 2208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_OFST 280\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LBN 2240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_OFST 296\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LBN 2368\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_OFST 312\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LBN 2496\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_OFST 313\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LBN 2504\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_OFST 314\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LBN 2512\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_OFST 315\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LBN 2520\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_OFST 316\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LBN 2528\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_OFST 317\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LBN 2536\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_OFST 320\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LBN 2560\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 324\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 2592\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_OFST 328\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LBN 2624\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 330\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 2640\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_OFST 332\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LBN 2656\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 334\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 2672\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_OFST 336\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LBN 2688\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_OFST 340\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LBN 2720\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_WIDTH 32\n+\n+/* MAE_FIELD_MASK_VALUE_PAIRS_V2 structuredef */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_LEN 372\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LBN 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_OFST 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LBN 64\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_OFST 12\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LBN 96\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_OFST 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LBN 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_OFST 18\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LBN 144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_OFST 20\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LBN 160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_OFST 22\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LBN 176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_OFST 24\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LBN 192\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_OFST 26\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LBN 208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_OFST 28\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LBN 224\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_OFST 30\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LBN 240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_OFST 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LBN 256\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_OFST 34\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LBN 272\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_OFST 36\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LBN 288\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_OFST 42\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LBN 336\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_OFST 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LBN 384\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_OFST 54\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LBN 432\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_OFST 60\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LBN 480\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_OFST 64\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LBN 512\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_OFST 68\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LBN 544\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_OFST 84\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LBN 672\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_OFST 100\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LBN 800\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_OFST 104\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LBN 832\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_OFST 108\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LBN 864\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_OFST 124\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LBN 992\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_OFST 140\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LBN 1120\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_OFST 141\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LBN 1128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_OFST 142\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LBN 1136\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_OFST 143\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LBN 1144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_OFST 144\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LBN 1152\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_OFST 145\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LBN 1160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_OFST 148\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LBN 1184\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_OFST 152\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LBN 1216\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_OFST 156\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LBN 1248\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_OFST 158\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LBN 1264\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_OFST 160\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LBN 1280\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_OFST 162\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LBN 1296\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_OFST 164\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LBN 1312\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_OFST 166\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LBN 1328\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_OFST 168\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LBN 1344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_OFST 172\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LBN 1376\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_OFST 176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LBN 1408\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_OFST 180\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LBN 1440\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_OFST 184\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LBN 1472\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_OFST 188\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LBN 1504\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_OFST 192\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LBN 1536\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_OFST 194\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LBN 1552\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_OFST 196\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LBN 1568\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_OFST 198\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LBN 1584\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_OFST 200\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LBN 1600\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_OFST 202\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LBN 1616\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_OFST 204\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LBN 1632\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_OFST 206\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LBN 1648\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_OFST 208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LBN 1664\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_OFST 214\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LBN 1712\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_OFST 220\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LBN 1760\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_OFST 226\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LEN 6\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LBN 1808\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_WIDTH 48\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_OFST 232\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LBN 1856\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_OFST 236\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LBN 1888\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_OFST 240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LBN 1920\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_OFST 256\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LBN 2048\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_OFST 272\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LBN 2176\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_OFST 276\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LBN 2208\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_OFST 280\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LBN 2240\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_OFST 296\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LEN 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LBN 2368\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_WIDTH 128\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_OFST 312\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LBN 2496\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_OFST 313\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LBN 2504\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_OFST 314\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LBN 2512\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_OFST 315\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LBN 2520\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_OFST 316\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LBN 2528\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_OFST 317\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LBN 2536\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_OFST 320\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LBN 2560\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_OFST 324\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LBN 2592\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_OFST 328\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LBN 2624\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_OFST 330\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LBN 2640\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_OFST 332\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LBN 2656\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_OFST 334\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LBN 2672\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_OFST 336\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LBN 2688\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_OFST 340\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LBN 2720\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_LBN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_LBN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_OFST 344\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_LBN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD_WIDTH 28\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LBN 2784\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_OFST 352\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LBN 2816\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_OFST 354\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LEN 2\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LBN 2832\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_WIDTH 16\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_OFST 356\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LBN 2848\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_OFST 360\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LBN 2880\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_WIDTH 32\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_OFST 364\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LBN 2912\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_WIDTH 8\n+/* Set to zero. */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_OFST 365\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LBN 2920\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_OFST 366\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LBN 2928\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_WIDTH 8\n+/* Set to zero. */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_OFST 367\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LBN 2936\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_OFST 368\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LBN 2944\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_WIDTH 8\n+/* Set to zero */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_OFST 369\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LBN 2952\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_WIDTH 8\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_OFST 370\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LBN 2960\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_WIDTH 8\n+/* Set to zero */\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_OFST 371\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LEN 1\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LBN 2968\n+#define\tMAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_WIDTH 8\n+\n /* MAE_MPORT_SELECTOR structuredef: MPORTS are identified by an opaque unsigned\n  * integer value (mport_id) that is guaranteed to be representable within\n  * 32-bits or within any NIC interface field that needs store the value\n@@ -25699,4 +26738,1197 @@\n #define\tMAE_MPORT_SELECTOR_FLAT_LBN 0\n #define\tMAE_MPORT_SELECTOR_FLAT_WIDTH 32\n \n+\n+/***********************************/\n+/* MC_CMD_MAE_GET_CAPS\n+ * Describes capabilities of the MAE (Match-Action Engine)\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS 0x140\n+#undef\tMC_CMD_0x140_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_GET_CAPS_IN msgrequest */\n+#define\tMC_CMD_MAE_GET_CAPS_IN_LEN 0\n+\n+/* MC_CMD_MAE_GET_CAPS_OUT msgresponse */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_LEN 52\n+/* The number of field IDs that the NIC supports. Any field with a ID greater\n+ * than or equal to the value returned in this field must be treated as having\n+ * a support level of MAE_FIELD_UNSUPPORTED in all requests.\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_WIDTH 1\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_LBN 1\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_WIDTH 1\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1\n+/* The total number of counters available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4\n+/* The total number of counters lists available to allocate. A value of zero\n+ * indicates that counter lists are not supported by the NIC. (But single\n+ * counters may still be.)\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_OFST 12\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4\n+/* The total number of encap header structures available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_OFST 16\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4\n+/* Reserved. Should be zero. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_RSVD_OFST 20\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4\n+/* The total number of action sets available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_OFST 24\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4\n+/* The total number of action set lists available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_OFST 28\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4\n+/* The total number of outer rules available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_OFST 32\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4\n+/* The total number of action rules available to allocate. */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_OFST 36\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4\n+/* The number of priorities available for ACTION_RULE filters. It is invalid to\n+ * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_OFST 40\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4\n+/* The number of priorities available for OUTER_RULE filters. It is invalid to\n+ * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_OFST 44\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4\n+/* MAE API major version. Currently 1. If this field is not present in the\n+ * response (i.e. response shorter than 384 bits), then its value is zero. If\n+ * the value does not match the client's expectations, the client should raise\n+ * a fatal error.\n+ */\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_API_VER_OFST 48\n+#define\tMC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_GET_AR_CAPS\n+ * Get a level of support for match fields when used in match-action rules\n+ */\n+#define\tMC_CMD_MAE_GET_AR_CAPS 0x141\n+#undef\tMC_CMD_0x141_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_GET_AR_CAPS_IN msgrequest */\n+#define\tMC_CMD_MAE_GET_AR_CAPS_IN_LEN 0\n+\n+/* MC_CMD_MAE_GET_AR_CAPS_OUT msgresponse */\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX 252\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)\n+/* Number of fields actually returned in FIELD_FLAGS. */\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4\n+/* Array of values indicating the NIC's support for a given field, indexed by\n+ * field id. The driver must ensure space for\n+ * MC_CMD_MAE_GET_CAPS.MATCH_FIELD_COUNT entries in the array..\n+ */\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62\n+#define\tMC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_GET_OR_CAPS\n+ * Get a level of support for fields used in outer rule keys.\n+ */\n+#define\tMC_CMD_MAE_GET_OR_CAPS 0x142\n+#undef\tMC_CMD_0x142_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_GET_OR_CAPS_IN msgrequest */\n+#define\tMC_CMD_MAE_GET_OR_CAPS_IN_LEN 0\n+\n+/* MC_CMD_MAE_GET_OR_CAPS_OUT msgresponse */\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX 252\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)\n+/* Number of fields actually returned in FIELD_FLAGS. */\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4\n+/* Same semantics as MC_CMD_MAE_GET_AR_CAPS.MAE_FIELD_FLAGS */\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62\n+#define\tMC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_COUNTER_ALLOC\n+ * Allocate match-action-engine counters, which can be referenced in Action\n+ * Rules.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC 0x143\n+#undef\tMC_CMD_0x143_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_COUNTER_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4\n+/* The number of counters that the driver would like allocated */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4\n+\n+/* MC_CMD_MAE_COUNTER_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_LENMIN 12\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX 252\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)\n+/* Generation count. Packets with generation count >= GENERATION_COUNT will\n+ * contain valid counter values for counter IDs allocated in this call, unless\n+ * the counter values are zero and zero squash is enabled.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4\n+/* The number of counter IDs that the NIC allocated. It is never less than 1;\n+ * failure to allocate a single counter will cause an error to be returned. It\n+ * is never greater than REQUESTED_COUNT, but may be less.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4\n+/* An array containing the IDs for the counters allocated. */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 8\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 1\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 61\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM_MCDI2 253\n+/* enum: A counter ID that is guaranteed never to represent a real counter */\n+#define\tMC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_COUNTER_FREE\n+ * Free match-action-engine counters\n+ */\n+#define\tMC_CMD_MAE_COUNTER_FREE 0x144\n+#undef\tMC_CMD_0x144_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_COUNTER_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_LENMIN 8\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_LENMAX 132\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_LENMAX_MCDI2 132\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)\n+/* The number of counter IDs to be freed. */\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4\n+/* An array containing the counter IDs to be freed. */\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MINNUM 1\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_COUNTER_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_LENMIN 12\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_LENMAX 136\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_LENMAX_MCDI2 136\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)\n+/* Generation count. A packet with generation count == GENERATION_COUNT will\n+ * contain the final values for these counter IDs, unless the counter values\n+ * are zero and zero squash is enabled. Receiving a packet with generation\n+ * count > GENERATION_COUNT guarantees that no more values will be written for\n+ * these counters. If values for these counter IDs are present, the counter ID\n+ * has been reallocated. A counter ID will not be reallocated within a single\n+ * read cycle as this would merge increments from the 'old' and 'new' counters.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4\n+/* The number of counter IDs actually freed. It is never less than 1; failure\n+ * to free a single counter will cause an error to be returned. It is never\n+ * greater than the number that were requested to be freed, but may be less if\n+ * counters could not be freed.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4\n+/* An array containing the IDs for the counters to that were freed. Note,\n+ * failure to free a counter can only occur on incorrect driver behaviour, so\n+ * asserting that the expected counters were freed is reasonable. When\n+ * debugging, attempting to free a single counter at a time will provide a\n+ * reason for the failure to free said counter.\n+ */\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_OFST 8\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MINNUM 1\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_COUNTERS_STREAM_START\n+ * Start streaming counter values, specifying an RxQ to deliver packets to.\n+ * Counters allocated to the calling function will be written in a round robin\n+ * at a fixed cycle rate, assuming sufficient credits are available. The driver\n+ * may cause the counter values to be written at a slower rate by constraining\n+ * the availability of credits. Note that if the driver wishes to deliver\n+ * packets to a different queue, it must call MAE_COUNTERS_STREAM_STOP to stop\n+ * delivering packets to the current queue first.\n+ */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START 0x151\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_START_IN msgrequest */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN 8\n+/* The RxQ to write packets to. */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_LEN 2\n+/* Maximum size in bytes of packets that may be written to the RxQ. */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_OFST 2\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_LEN 2\n+/* Optional flags. */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_WIDTH 1\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_LBN 1\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_WIDTH 1\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_START_OUT msgresponse */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_WIDTH 1\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_COUNTERS_STREAM_STOP\n+ * Stop streaming counter values to the specified RxQ.\n+ */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP 0x152\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_STOP_IN msgrequest */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN 2\n+/* The RxQ to stop writing packets to. */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_LEN 2\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT msgresponse */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4\n+/* Generation count. The final set of counter values will be written out in\n+ * packets with count == GENERATION_COUNT. An empty packet with count >\n+ * GENERATION_COUNT indicates that no more counter values will be written to\n+ * this stream.\n+ */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS\n+ * Give a number of credits to the packetiser. Each credit received allows the\n+ * MC to write one packet to the RxQ, therefore for each credit the driver must\n+ * have written sufficient descriptors for a packet of length\n+ * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.\n+ */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN msgrequest */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4\n+/* Number of credits to give to the packetiser. */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4\n+\n+/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT msgresponse */\n+#define\tMC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ENCAP_HEADER_ALLOC\n+ * Allocate encap action metadata\n+ */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148\n+#undef\tMC_CMD_0x148_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX 252\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_LEN 1\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM 248\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM_MCDI2 1016\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4\n+/* enum: An encap metadata ID that is guaranteed never to represent real encap\n+ * metadata\n+ */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ENCAP_HEADER_UPDATE\n+ * Update encap action metadata\n+ */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149\n+#undef\tMC_CMD_0x149_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN msgrequest */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMIN 8\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX 252\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LEN(num) (8+1*(num))\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_OFST 8\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_LEN 1\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM 244\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM_MCDI2 1012\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ENCAP_HEADER_FREE\n+ * Free encap action metadata\n+ */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE 0x14a\n+#undef\tMC_CMD_0x14a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_ENCAP_HEADER_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MAC_ADDR_ALLOC\n+ * Allocate MAC address. Hardware implementations have MAC addresses programmed\n+ * into an indirection table, and clients should take care not to allocate the\n+ * same MAC address twice (but instead reuse its ID).\n+ */\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC 0x15e\n+#undef\tMC_CMD_0x15e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_MAC_ADDR_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_IN_LEN 6\n+/* MAC address as bytes in network order. */\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_LEN 6\n+\n+/* MC_CMD_MAE_MAC_ADDR_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4\n+/* enum: An MAC address ID that is guaranteed never to represent a real MAC\n+ * address.\n+ */\n+#define\tMC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MAC_ADDR_FREE\n+ * Free MAC address.\n+ */\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE 0x15f\n+#undef\tMC_CMD_0x15f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_MAC_ADDR_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MINNUM 1\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_MAC_ADDR_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MINNUM 1\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_SET_ALLOC\n+ * Allocate an action set, which can be referenced either in response to an\n+ * Action Rule, or as part of an Action Set List.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC 0x14d\n+#undef\tMC_CMD_0x14d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_SET_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN 44\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_WIDTH 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_WIDTH 2\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_LBN 8\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_LBN 9\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_LBN 10\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_WIDTH 1\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1\n+/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2\n+/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_OFST 6\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_LEN 2\n+/* If VLAN_PUSH == 2, inner TCI value to be inserted. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_OFST 8\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_LEN 2\n+/* If VLAN_PUSH == 2, inner TPID value to be inserted. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_OFST 10\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_LEN 2\n+/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_OFST 12\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4\n+/* Set to ENCAP_HEADER_ID_NULL to request no encap action */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_OFST 16\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4\n+/* An m-port selector identifying the m-port that the modified packet should be\n+ * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the\n+ * packet.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_OFST 20\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4\n+/* Allows an action set to trigger several counter updates. Set to\n+ * COUNTER_LIST_ID_NULL to request no counter action.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_OFST 24\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4\n+/* If a driver only wished to update one counter within this action set, then\n+ * it can supply a COUNTER_ID instead of allocating a single-element counter\n+ * list. This field should be set to COUNTER_ID_NULL if this behaviour is not\n+ * required. It is not valid to supply a non-NULL value for both\n+ * COUNTER_LIST_ID and COUNTER_ID.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_OFST 28\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_OFST 32\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4\n+/* Set to MAC_ID_NULL to request no source MAC replacement. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_OFST 36\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4\n+/* Set to MAC_ID_NULL to request no destination MAC replacement. */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4\n+\n+/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4\n+/* enum: An action set ID that is guaranteed never to represent an action set\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_SET_FREE\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_FREE 0x14e\n+#undef\tMC_CMD_0x14e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_SET_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_ACTION_SET_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC\n+ * Allocate an action set list (ASL) that can be referenced by an ID. The ASL\n+ * ID can be used when inserting an action rule, so that for each packet\n+ * matching the rule every action set in the list is applied.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f\n+#undef\tMC_CMD_0x14f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMIN 8\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX 252\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)\n+/* Number of elements in the AS_IDS field. */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4\n+/* The IDs of the action sets in this list. The last element of this list may\n+ * be the ID of an already allocated ASL. In this case the action sets from the\n+ * already allocated ASL will be applied after the action sets supplied by this\n+ * request. This mechanism can be used to reduce resource usage in the case\n+ * where one ASL is a sublist of another ASL. The sublist should be allocated\n+ * first, then the superlist should be allocated by supplying all required\n+ * action set IDs that are not in the sublist followed by the ID of the\n+ * sublist. One sublist can be referenced by multiple superlists.\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM 62\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM_MCDI2 254\n+\n+/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4\n+/* enum: An action set list ID that is guaranteed never to represent an action\n+ * set list\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_SET_LIST_FREE\n+ * Free match-action-engine redirect_lists\n+ */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE 0x150\n+#undef\tMC_CMD_0x150_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_SET_LIST_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_OUTER_RULE_INSERT\n+ * Inserts an Outer Rule, which controls encapsulation parsing, and may\n+ * influence the Lookup Sequence.\n+ */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT 0x15a\n+#undef\tMC_CMD_0x15a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_MAE_OUTER_RULE_INSERT_IN msgrequest */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMIN 16\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX 252\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LEN(num) (16+1*(num))\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)\n+/* Packets matching the rule will be parsed with this encapsulation. */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MAE_MCDI_ENCAP_TYPE */\n+/* Match priority. Lower values have higher priority. Must be less than\n+ * MC_CMD_MAE_GET_CAPS_OUT.ENCAP_PRIOS If a packet matches two filters with\n+ * equal priority then it is unspecified which takes priority.\n+ */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_OFST 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_OFST 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_WIDTH 1\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_OFST 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_LBN 1\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_WIDTH 2\n+/*             Enum values, see field(s): */\n+/*                MAE_CT_VNI_MODE */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_OFST 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_LBN 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_WIDTH 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_OFST 8\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_LBN 16\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_WIDTH 16\n+/* Reserved for future use. Must be set to zero. */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_RSVD_OFST 12\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_RSVD_LEN 4\n+/* Structure of the format MAE_ENC_FIELD_PAIRS. */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST 16\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_LEN 1\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM 236\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM_MCDI2 1004\n+\n+/* MC_CMD_MAE_OUTER_RULE_INSERT_OUT msgresponse */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4\n+/* enum: An outer match ID that is guaranteed never to represent an outer match\n+ */\n+#define\tMC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_OUTER_RULE_REMOVE\n+ */\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE 0x15b\n+#undef\tMC_CMD_0x15b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_MAE_OUTER_RULE_REMOVE_IN msgrequest */\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MINNUM 1\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_OUTER_RULE_REMOVE_OUT msgresponse */\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MINNUM 1\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM_MCDI2 32\n+\n+/* MAE_ACTION_RULE_RESPONSE structuredef */\n+#define\tMAE_ACTION_RULE_RESPONSE_LEN 16\n+#define\tMAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0\n+#define\tMAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4\n+#define\tMAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0\n+#define\tMAE_ACTION_RULE_RESPONSE_ASL_ID_WIDTH 32\n+/* Only one of ASL_ID or AS_ID may have a non-NULL value. */\n+#define\tMAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4\n+#define\tMAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4\n+#define\tMAE_ACTION_RULE_RESPONSE_AS_ID_LBN 32\n+#define\tMAE_ACTION_RULE_RESPONSE_AS_ID_WIDTH 32\n+/* Controls lookup flow when this rule is hit. See sub-fields for details. More\n+ * info on the lookup sequence can be found in SF-122976-TC. It is an error to\n+ * set both DO_CT and DO_RECIRC.\n+ */\n+#define\tMAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_CT_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_CT_WIDTH 1\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_RECIRC_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_RECIRC_LBN 1\n+#define\tMAE_ACTION_RULE_RESPONSE_DO_RECIRC_WIDTH 1\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_LBN 2\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_WIDTH 2\n+/*             Enum values, see field(s): */\n+/*                MAE_CT_VNI_MODE */\n+#define\tMAE_ACTION_RULE_RESPONSE_RECIRC_ID_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_RECIRC_ID_LBN 8\n+#define\tMAE_ACTION_RULE_RESPONSE_RECIRC_ID_WIDTH 8\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_DOMAIN_OFST 8\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_DOMAIN_LBN 16\n+#define\tMAE_ACTION_RULE_RESPONSE_CT_DOMAIN_WIDTH 16\n+#define\tMAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LBN 64\n+#define\tMAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_WIDTH 32\n+/* Counter ID to increment if DO_CT or DO_RECIRC is set. Must be set to\n+ * COUNTER_ID_NULL otherwise.\n+ */\n+#define\tMAE_ACTION_RULE_RESPONSE_COUNTER_ID_OFST 12\n+#define\tMAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4\n+#define\tMAE_ACTION_RULE_RESPONSE_COUNTER_ID_LBN 96\n+#define\tMAE_ACTION_RULE_RESPONSE_COUNTER_ID_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_RULE_INSERT\n+ * Insert a rule specify that packets matching a filter be processed according\n+ * to a previous allocated action. Masks can be set as indicated by\n+ * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES.\n+ */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT 0x15c\n+#undef\tMC_CMD_0x15c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_RULE_INSERT_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMIN 28\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX 252\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_LEN(num) (28+1*(num))\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)\n+/* See MC_CMD_MAE_OUTER_RULE_REGISTER_IN/PRIO. */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4\n+/* Structure of the format MAE_ACTION_RULE_RESPONSE */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN 20\n+/* Reserved for future use. Must be set to zero. */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_OFST 24\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4\n+/* Structure of the format MAE_FIELD_MASK_VALUE_PAIRS */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST 28\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_LEN 1\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM 224\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM_MCDI2 992\n+\n+/* MC_CMD_MAE_ACTION_RULE_INSERT_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4\n+/* enum: An action rule ID that is guaranteed never to represent an action rule\n+ */\n+#define\tMC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_RULE_UPDATE\n+ * Atomically change the response of an action rule. Firmware may return\n+ * ENOTSUP, in which case the driver should DELETE/INSERT.\n+ */\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE 0x15d\n+#undef\tMC_CMD_0x15d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_RULE_UPDATE_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_IN_LEN 24\n+/* ID of action rule to update */\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4\n+/* Structure of the format MAE_ACTION_RULE_RESPONSE */\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_LEN 20\n+\n+/* MC_CMD_MAE_ACTION_RULE_UPDATE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_ACTION_RULE_DELETE\n+ */\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE 0x155\n+#undef\tMC_CMD_0x155_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_ACTION_RULE_DELETE_IN msgrequest */\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM_MCDI2 32\n+\n+/* MC_CMD_MAE_ACTION_RULE_DELETE_OUT msgresponse */\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX 128\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX_MCDI2 128\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)\n+/* Same semantics as MC_CMD_MAE_COUNTER_FREE */\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MINNUM 1\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM 32\n+#define\tMC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM_MCDI2 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MPORT_LOOKUP\n+ * Return the m-port corresponding to a selector.\n+ */\n+#define\tMC_CMD_MAE_MPORT_LOOKUP 0x160\n+#undef\tMC_CMD_0x160_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_MPORT_LOOKUP_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_LOOKUP_OUT msgresponse */\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0\n+#define\tMC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MPORT_ALLOC\n+ * Allocates a m-port, which can subsequently be used in action rules as a\n+ * match or delivery argument.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC 0x163\n+#undef\tMC_CMD_0x163_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_LEN 20\n+/* The type of m-port to allocate. Firmware may return ENOTSUP for certain\n+ * types.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4\n+/* enum: Traffic can be sent to this type of m-port using an override\n+ * descriptor. Traffic received on this type of m-port will go to the VNIC on a\n+ * nominated m-port, and will be delivered with metadata identifying the alias\n+ * m-port.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1\n+/* enum: This type of m-port has a VNIC attached. Queues can be created on this\n+ * VNIC by specifying the created m-port as an m-port selector at queue\n+ * creation time.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2\n+/* 128-bit value for use by the driver. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4\n+#define\tMC_CMD_MAE_MPORT_ALLOC_IN_UUID_LEN 16\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_LEN 24\n+/* The type of m-port to allocate. Firmware may return ENOTSUP for certain\n+ * types.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4\n+/* enum: Traffic can be sent to this type of m-port using an override\n+ * descriptor. Traffic received on this type of m-port will go to the VNIC on a\n+ * nominated m-port, and will be delivered with metadata identifying the alias\n+ * m-port.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1\n+/* enum: This type of m-port has a VNIC attached. Queues can be created on this\n+ * VNIC by specifying the created m-port as an m-port selector at queue\n+ * creation time.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2\n+/* 128-bit value for use by the driver. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_LEN 16\n+/* An m-port selector identifying the VNIC to which traffic should be\n+ * delivered. This must currently be set to MAE_MPORT_SELECTOR_ASSIGNED (i.e.\n+ * the m-port assigned to the calling client).\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_OFST 20\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_VNIC_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_LEN 20\n+/* The type of m-port to allocate. Firmware may return ENOTSUP for certain\n+ * types.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4\n+/* enum: Traffic can be sent to this type of m-port using an override\n+ * descriptor. Traffic received on this type of m-port will go to the VNIC on a\n+ * nominated m-port, and will be delivered with metadata identifying the alias\n+ * m-port.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1\n+/* enum: This type of m-port has a VNIC attached. Queues can be created on this\n+ * VNIC by specifying the created m-port as an m-port selector at queue\n+ * creation time.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2\n+/* 128-bit value for use by the driver. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_LEN 16\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4\n+/* ID of newly-allocated m-port. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LEN 24\n+/* ID of newly-allocated m-port. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4\n+/* A value that will appear in the packet metadata for any packets delivered\n+ * using an alias type m-port. This value is guaranteed unique on the VNIC\n+ * being delivered to, and is guaranteed not to exceed the range of values\n+ * representable in the relevant metadata field.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_OFST 20\n+#define\tMC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4\n+/* ID of newly-allocated m-port. */\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MPORT_FREE\n+ * Free a m-port which was previously allocated by the driver.\n+ */\n+#define\tMC_CMD_MAE_MPORT_FREE 0x164\n+#undef\tMC_CMD_0x164_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_MAE_MPORT_FREE_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_FREE_IN_LEN 4\n+/* MPORT_ID as returned by MC_CMD_MAE_MPORT_ALLOC. */\n+#define\tMC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0\n+#define\tMC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4\n+\n+/* MC_CMD_MAE_MPORT_FREE_OUT msgresponse */\n+#define\tMC_CMD_MAE_MPORT_FREE_OUT_LEN 0\n+\n+/* MAE_MPORT_DESC structuredef */\n+#define\tMAE_MPORT_DESC_LEN 52\n+#define\tMAE_MPORT_DESC_MPORT_ID_OFST 0\n+#define\tMAE_MPORT_DESC_MPORT_ID_LEN 4\n+#define\tMAE_MPORT_DESC_MPORT_ID_LBN 0\n+#define\tMAE_MPORT_DESC_MPORT_ID_WIDTH 32\n+/* Reserved for future purposes, contains information independent of caller */\n+#define\tMAE_MPORT_DESC_FLAGS_OFST 4\n+#define\tMAE_MPORT_DESC_FLAGS_LEN 4\n+#define\tMAE_MPORT_DESC_FLAGS_LBN 32\n+#define\tMAE_MPORT_DESC_FLAGS_WIDTH 32\n+#define\tMAE_MPORT_DESC_CALLER_FLAGS_OFST 8\n+#define\tMAE_MPORT_DESC_CALLER_FLAGS_LEN 4\n+#define\tMAE_MPORT_DESC_CAN_RECEIVE_ON_OFST 8\n+#define\tMAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0\n+#define\tMAE_MPORT_DESC_CAN_RECEIVE_ON_WIDTH 1\n+#define\tMAE_MPORT_DESC_CAN_DELIVER_TO_OFST 8\n+#define\tMAE_MPORT_DESC_CAN_DELIVER_TO_LBN 1\n+#define\tMAE_MPORT_DESC_CAN_DELIVER_TO_WIDTH 1\n+#define\tMAE_MPORT_DESC_CAN_DELETE_OFST 8\n+#define\tMAE_MPORT_DESC_CAN_DELETE_LBN 2\n+#define\tMAE_MPORT_DESC_CAN_DELETE_WIDTH 1\n+#define\tMAE_MPORT_DESC_CALLER_FLAGS_LBN 64\n+#define\tMAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32\n+/* Not the ideal name; it's really the type of thing connected to the m-port */\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_OFST 12\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_LEN 4\n+/* enum: Connected to a MAC... */\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0\n+/* enum: Adds metadata and delivers to another m-port */\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1\n+/* enum: Connected to a VNIC. */\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_LBN 96\n+#define\tMAE_MPORT_DESC_MPORT_TYPE_WIDTH 32\n+/* 128-bit value available to drivers for m-port identification. */\n+#define\tMAE_MPORT_DESC_UUID_OFST 16\n+#define\tMAE_MPORT_DESC_UUID_LEN 16\n+#define\tMAE_MPORT_DESC_UUID_LBN 128\n+#define\tMAE_MPORT_DESC_UUID_WIDTH 128\n+/* Big wadge of space reserved for other common properties */\n+#define\tMAE_MPORT_DESC_RESERVED_OFST 32\n+#define\tMAE_MPORT_DESC_RESERVED_LEN 8\n+#define\tMAE_MPORT_DESC_RESERVED_LO_OFST 32\n+#define\tMAE_MPORT_DESC_RESERVED_HI_OFST 36\n+#define\tMAE_MPORT_DESC_RESERVED_LBN 256\n+#define\tMAE_MPORT_DESC_RESERVED_WIDTH 64\n+/* Logical port index. Only valid when type NET Port. */\n+#define\tMAE_MPORT_DESC_NET_PORT_IDX_OFST 40\n+#define\tMAE_MPORT_DESC_NET_PORT_IDX_LEN 4\n+#define\tMAE_MPORT_DESC_NET_PORT_IDX_LBN 320\n+#define\tMAE_MPORT_DESC_NET_PORT_IDX_WIDTH 32\n+/* The m-port delivered to */\n+#define\tMAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_OFST 40\n+#define\tMAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4\n+#define\tMAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LBN 320\n+#define\tMAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_WIDTH 32\n+/* The type of thing that owns the VNIC */\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_OFST 40\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_LBN 320\n+#define\tMAE_MPORT_DESC_VNIC_CLIENT_TYPE_WIDTH 32\n+/* The PCIe interface on which the funcion lives. CJK: We need an enumeration\n+ * of interfaces that we extend as new interface (types) appear. This belongs\n+ * elsewhere and should be referenced from here\n+ */\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_OFST 44\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LBN 352\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_WIDTH 32\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_OFST 48\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LEN 2\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LBN 384\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_WIDTH 16\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_OFST 50\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LEN 2\n+/* enum: Indicates that the function is a PF */\n+#define\tMAE_MPORT_DESC_VF_IDX_NULL 0xffff\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LBN 400\n+#define\tMAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_WIDTH 16\n+/* Reserved. Should be ignored for now. */\n+#define\tMAE_MPORT_DESC_VNIC_PLUGIN_TBD_OFST 44\n+#define\tMAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4\n+#define\tMAE_MPORT_DESC_VNIC_PLUGIN_TBD_LBN 352\n+#define\tMAE_MPORT_DESC_VNIC_PLUGIN_TBD_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_MAE_MPORT_ENUMERATE\n+ */\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE 0x17c\n+\n+/* MC_CMD_MAE_MPORT_ENUMERATE_IN msgrequest */\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0\n+\n+/* MC_CMD_MAE_MPORT_ENUMERATE_OUT msgresponse */\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMIN 8\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX 252\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_LEN(num) (8+1*(num))\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_NUM(len) (((len)-8)/1)\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_OFST 0\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_LEN 4\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_OFST 4\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_LEN 4\n+/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may\n+ * grow in future version of this command. Drivers should use a stride of\n+ * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.\n+ */\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_OFST 8\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_LEN 1\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MINNUM 0\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM 244\n+#define\tMC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1012\n+\n #endif /* _SIENA_MC_DRIVER_PCOL_H */\n",
    "prefixes": [
        "01/62"
    ]
}