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GET /api/patches/81388/?format=api
{ "id": 81388, "url": "http://patches.dpdk.org/api/patches/81388/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/2ad5a5ef741e681e7699f4e04858ce1723166c27.1603119829.git.vladimir.medvedkin@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<2ad5a5ef741e681e7699f4e04858ce1723166c27.1603119829.git.vladimir.medvedkin@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/2ad5a5ef741e681e7699f4e04858ce1723166c27.1603119829.git.vladimir.medvedkin@intel.com", "date": "2020-10-19T15:05:24", "name": "[v13,6/7] fib6: introduce AVX512 lookup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "27abaecdbf917cd89c6fa59d69b5626085774232", "submitter": { "id": 1216, "url": "http://patches.dpdk.org/api/people/1216/?format=api", "name": "Vladimir Medvedkin", "email": "vladimir.medvedkin@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/2ad5a5ef741e681e7699f4e04858ce1723166c27.1603119829.git.vladimir.medvedkin@intel.com/mbox/", "series": [ { "id": 13107, "url": "http://patches.dpdk.org/api/series/13107/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13107", "date": "2020-10-19T15:05:19", "name": "fib: implement AVX512 vector lookup", "version": 13, "mbox": "http://patches.dpdk.org/series/13107/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81388/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81388/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F71FA04DC;\n\tMon, 19 Oct 2020 17:07:43 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 17FEBFC51;\n\tMon, 19 Oct 2020 17:05:46 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 8ACF2FC41\n for <dev@dpdk.org>; Mon, 19 Oct 2020 17:05:42 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Oct 2020 08:05:42 -0700", "from silpixa00400072.ir.intel.com ([10.237.222.213])\n by fmsmga004.fm.intel.com with ESMTP; 19 Oct 2020 08:05:40 -0700" ], "IronPort-SDR": [ "\n 4soURkDzHdcWcXNPBU8I46JGYiNVkKAhwpBnjywqhU3gYU7CG786f0AUxWJ6JWkqsOc6Q9M6uK\n cCq3LWsBLSHw==", "\n jWtOx4TwVkKUPrGC0tIriO/81NIxESL1Hg0NpOPFnMtPEktg4qBUBjP4T4dEDbypsg2e2MigfW\n 2aSY94ftvFpQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9778\"; a=\"251739553\"", "E=Sophos;i=\"5.77,394,1596524400\"; d=\"scan'208\";a=\"251739553\"", "E=Sophos;i=\"5.77,394,1596524400\"; d=\"scan'208\";a=\"347460059\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Vladimir Medvedkin <vladimir.medvedkin@intel.com>", "To": "dev@dpdk.org", "Cc": "david.marchand@redhat.com, jerinj@marvell.com, mdr@ashroe.eu,\n thomas@monjalon.net, konstantin.ananyev@intel.com,\n bruce.richardson@intel.com, ciara.power@intel.com", "Date": "Mon, 19 Oct 2020 16:05:24 +0100", "Message-Id": "\n <2ad5a5ef741e681e7699f4e04858ce1723166c27.1603119829.git.vladimir.medvedkin@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<cover.1603119828.git.vladimir.medvedkin@intel.com>", "<cover.1603119828.git.vladimir.medvedkin@intel.com>" ], "References": [ "<cover.1603119828.git.vladimir.medvedkin@intel.com>", "<cover.1603102577.git.vladimir.medvedkin@intel.com>\n <cover.1603119828.git.vladimir.medvedkin@intel.com>" ], "Subject": "[dpdk-dev] [PATCH v13 6/7] fib6: introduce AVX512 lookup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add new lookup implementation for FIB6 trie algorithm using\nAVX512 instruction set\n\nSigned-off-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n doc/guides/rel_notes/release_20_11.rst | 2 +-\n lib/librte_fib/meson.build | 17 +++\n lib/librte_fib/rte_fib6.c | 2 +-\n lib/librte_fib/rte_fib6.h | 5 +-\n lib/librte_fib/trie.c | 36 +++++\n lib/librte_fib/trie_avx512.c | 269 +++++++++++++++++++++++++++++++++\n lib/librte_fib/trie_avx512.h | 20 +++\n 7 files changed, 348 insertions(+), 3 deletions(-)\n create mode 100644 lib/librte_fib/trie_avx512.c\n create mode 100644 lib/librte_fib/trie_avx512.h", "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 7eacab5..fa50e81 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -346,7 +346,7 @@ New Features\n \n * **Added AVX512 lookup implementation for FIB.**\n \n- Added a AVX512 lookup functions implementation into FIB library.\n+ Added a AVX512 lookup functions implementation into FIB and FIB6 libraries.\n \n Removed Items\n -------------\ndiff --git a/lib/librte_fib/meson.build b/lib/librte_fib/meson.build\nindex 0a8adef..5d93de9 100644\n--- a/lib/librte_fib/meson.build\n+++ b/lib/librte_fib/meson.build\n@@ -30,6 +30,12 @@ if dpdk_conf.has('RTE_ARCH_X86_64') and binutils_ok.returncode() == 0\n \tif acl_avx512_on == true\n \t\tcflags += ['-DCC_DIR24_8_AVX512_SUPPORT']\n \t\tsources += files('dir24_8_avx512.c')\n+\t\t# TRIE AVX512 implementation uses avx512bw intrinsics along with\n+\t\t# avx512f and avx512dq\n+\t\tif cc.get_define('__AVX512BW__', args: machine_args) != ''\n+\t\t\tcflags += ['-DCC_TRIE_AVX512_SUPPORT']\n+\t\t\tsources += files('trie_avx512.c')\n+\t\tendif\n \telif cc.has_multi_arguments('-mavx512f', '-mavx512dq')\n \t\tdir24_8_avx512_tmp = static_library('dir24_8_avx512_tmp',\n \t\t\t\t'dir24_8_avx512.c',\n@@ -37,5 +43,16 @@ if dpdk_conf.has('RTE_ARCH_X86_64') and binutils_ok.returncode() == 0\n \t\t\t\tc_args: cflags + ['-mavx512f', '-mavx512dq'])\n \t\tobjs += dir24_8_avx512_tmp.extract_objects('dir24_8_avx512.c')\n \t\tcflags += '-DCC_DIR24_8_AVX512_SUPPORT'\n+\t\t# TRIE AVX512 implementation uses avx512bw intrinsics along with\n+\t\t# avx512f and avx512dq\n+\t\tif cc.has_argument('-mavx512bw')\n+\t\t\ttrie_avx512_tmp = static_library('trie_avx512_tmp',\n+\t\t\t\t'trie_avx512.c',\n+\t\t\t\tdependencies: static_rte_eal,\n+\t\t\t\tc_args: cflags + ['-mavx512f', \\\n+\t\t\t\t\t'-mavx512dq', '-mavx512bw'])\n+\t\t\tobjs += trie_avx512_tmp.extract_objects('trie_avx512.c')\n+\t\t\tcflags += '-DCC_TRIE_AVX512_SUPPORT'\n+\t\tendif\n \tendif\n endif\ndiff --git a/lib/librte_fib/rte_fib6.c b/lib/librte_fib/rte_fib6.c\nindex 566cd5f..8512584 100644\n--- a/lib/librte_fib/rte_fib6.c\n+++ b/lib/librte_fib/rte_fib6.c\n@@ -107,7 +107,7 @@ init_dataplane(struct rte_fib6 *fib, __rte_unused int socket_id,\n \t\tfib->dp = trie_create(dp_name, socket_id, conf);\n \t\tif (fib->dp == NULL)\n \t\t\treturn -rte_errno;\n-\t\tfib->lookup = trie_get_lookup_fn(fib->dp, RTE_FIB6_TRIE_SCALAR);\n+\t\tfib->lookup = trie_get_lookup_fn(fib->dp, RTE_FIB6_TRIE_ANY);\n \t\tfib->modify = trie_modify;\n \t\treturn 0;\n \tdefault:\ndiff --git a/lib/librte_fib/rte_fib6.h b/lib/librte_fib/rte_fib6.h\nindex cd0c75e..2b2a1c8 100644\n--- a/lib/librte_fib/rte_fib6.h\n+++ b/lib/librte_fib/rte_fib6.h\n@@ -62,7 +62,10 @@ enum rte_fib_trie_nh_sz {\n \n /** Type of lookup function implementation */\n enum rte_fib_trie_lookup_type {\n-\tRTE_FIB6_TRIE_SCALAR /**< Scalar lookup function implementation*/\n+\tRTE_FIB6_TRIE_SCALAR, /**< Scalar lookup function implementation*/\n+\tRTE_FIB6_TRIE_VECTOR_AVX512, /**< Vector implementation using AVX512 */\n+\tRTE_FIB6_TRIE_ANY = UINT32_MAX\n+\t/**< Selects the best implementation based on the max simd bitwidth */\n };\n \n /** FIB configuration structure */\ndiff --git a/lib/librte_fib/trie.c b/lib/librte_fib/trie.c\nindex 82ba13d..d1b7672 100644\n--- a/lib/librte_fib/trie.c\n+++ b/lib/librte_fib/trie.c\n@@ -13,11 +13,18 @@\n #include <rte_malloc.h>\n #include <rte_errno.h>\n #include <rte_memory.h>\n+#include <rte_vect.h>\n \n #include <rte_rib6.h>\n #include <rte_fib6.h>\n #include \"trie.h\"\n \n+#ifdef CC_TRIE_AVX512_SUPPORT\n+\n+#include \"trie_avx512.h\"\n+\n+#endif /* CC_TRIE_AVX512_SUPPORT */\n+\n #define TRIE_NAMESIZE\t\t64\n \n enum edge {\n@@ -40,11 +47,35 @@ get_scalar_fn(enum rte_fib_trie_nh_sz nh_sz)\n \t}\n }\n \n+static inline rte_fib6_lookup_fn_t\n+get_vector_fn(enum rte_fib_trie_nh_sz nh_sz)\n+{\n+#ifdef CC_TRIE_AVX512_SUPPORT\n+\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) <= 0) ||\n+\t\t\t(rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_512))\n+\t\treturn NULL;\n+\tswitch (nh_sz) {\n+\tcase RTE_FIB6_TRIE_2B:\n+\t\treturn rte_trie_vec_lookup_bulk_2b;\n+\tcase RTE_FIB6_TRIE_4B:\n+\t\treturn rte_trie_vec_lookup_bulk_4b;\n+\tcase RTE_FIB6_TRIE_8B:\n+\t\treturn rte_trie_vec_lookup_bulk_8b;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+#else\n+\tRTE_SET_USED(nh_sz);\n+#endif\n+\treturn NULL;\n+}\n+\n rte_fib6_lookup_fn_t\n trie_get_lookup_fn(void *p, enum rte_fib_trie_lookup_type type)\n {\n \tenum rte_fib_trie_nh_sz nh_sz;\n \tstruct rte_trie_tbl *dp = p;\n+\trte_fib6_lookup_fn_t ret_fn = NULL;\n \n \tif (dp == NULL)\n \t\treturn NULL;\n@@ -54,6 +85,11 @@ trie_get_lookup_fn(void *p, enum rte_fib_trie_lookup_type type)\n \tswitch (type) {\n \tcase RTE_FIB6_TRIE_SCALAR:\n \t\treturn get_scalar_fn(nh_sz);\n+\tcase RTE_FIB6_TRIE_VECTOR_AVX512:\n+\t\treturn get_vector_fn(nh_sz);\n+\tcase RTE_FIB6_TRIE_ANY:\n+\t\tret_fn = get_vector_fn(nh_sz);\n+\t\treturn (ret_fn) ? ret_fn : get_scalar_fn(nh_sz);\n \tdefault:\n \t\treturn NULL;\n \t}\ndiff --git a/lib/librte_fib/trie_avx512.c b/lib/librte_fib/trie_avx512.c\nnew file mode 100644\nindex 0000000..b1c9e4e\n--- /dev/null\n+++ b/lib/librte_fib/trie_avx512.c\n@@ -0,0 +1,269 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include <rte_vect.h>\n+#include <rte_fib6.h>\n+\n+#include \"trie.h\"\n+#include \"trie_avx512.h\"\n+\n+static __rte_always_inline void\n+transpose_x16(uint8_t ips[16][RTE_FIB6_IPV6_ADDR_SIZE],\n+\t__m512i *first, __m512i *second, __m512i *third, __m512i *fourth)\n+{\n+\t__m512i tmp1, tmp2, tmp3, tmp4;\n+\t__m512i tmp5, tmp6, tmp7, tmp8;\n+\tconst __rte_x86_zmm_t perm_idxes = {\n+\t\t.u32 = { 0, 4, 8, 12, 2, 6, 10, 14,\n+\t\t\t1, 5, 9, 13, 3, 7, 11, 15\n+\t\t},\n+\t};\n+\n+\t/* load all ip addresses */\n+\ttmp1 = _mm512_loadu_si512(&ips[0][0]);\n+\ttmp2 = _mm512_loadu_si512(&ips[4][0]);\n+\ttmp3 = _mm512_loadu_si512(&ips[8][0]);\n+\ttmp4 = _mm512_loadu_si512(&ips[12][0]);\n+\n+\t/* transpose 4 byte chunks of 16 ips */\n+\ttmp5 = _mm512_unpacklo_epi32(tmp1, tmp2);\n+\ttmp7 = _mm512_unpackhi_epi32(tmp1, tmp2);\n+\ttmp6 = _mm512_unpacklo_epi32(tmp3, tmp4);\n+\ttmp8 = _mm512_unpackhi_epi32(tmp3, tmp4);\n+\n+\ttmp1 = _mm512_unpacklo_epi32(tmp5, tmp6);\n+\ttmp3 = _mm512_unpackhi_epi32(tmp5, tmp6);\n+\ttmp2 = _mm512_unpacklo_epi32(tmp7, tmp8);\n+\ttmp4 = _mm512_unpackhi_epi32(tmp7, tmp8);\n+\n+\t/* first 4-byte chunks of ips[] */\n+\t*first = _mm512_permutexvar_epi32(perm_idxes.z, tmp1);\n+\t/* second 4-byte chunks of ips[] */\n+\t*second = _mm512_permutexvar_epi32(perm_idxes.z, tmp3);\n+\t/* third 4-byte chunks of ips[] */\n+\t*third = _mm512_permutexvar_epi32(perm_idxes.z, tmp2);\n+\t/* fourth 4-byte chunks of ips[] */\n+\t*fourth = _mm512_permutexvar_epi32(perm_idxes.z, tmp4);\n+}\n+\n+static __rte_always_inline void\n+transpose_x8(uint8_t ips[8][RTE_FIB6_IPV6_ADDR_SIZE],\n+\t__m512i *first, __m512i *second)\n+{\n+\t__m512i tmp1, tmp2, tmp3, tmp4;\n+\tconst __rte_x86_zmm_t perm_idxes = {\n+\t\t.u64 = { 0, 2, 4, 6, 1, 3, 5, 7\n+\t\t},\n+\t};\n+\n+\ttmp1 = _mm512_loadu_si512(&ips[0][0]);\n+\ttmp2 = _mm512_loadu_si512(&ips[4][0]);\n+\n+\ttmp3 = _mm512_unpacklo_epi64(tmp1, tmp2);\n+\t*first = _mm512_permutexvar_epi64(perm_idxes.z, tmp3);\n+\ttmp4 = _mm512_unpackhi_epi64(tmp1, tmp2);\n+\t*second = _mm512_permutexvar_epi64(perm_idxes.z, tmp4);\n+}\n+\n+static __rte_always_inline void\n+trie_vec_lookup_x16(void *p, uint8_t ips[16][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, int size)\n+{\n+\tstruct rte_trie_tbl *dp = (struct rte_trie_tbl *)p;\n+\tconst __m512i zero = _mm512_set1_epi32(0);\n+\tconst __m512i lsb = _mm512_set1_epi32(1);\n+\tconst __m512i two_lsb = _mm512_set1_epi32(3);\n+\t__m512i first, second, third, fourth; /*< IPv6 four byte chunks */\n+\t__m512i idxes, res, shuf_idxes;\n+\t__m512i tmp, tmp2, bytes, byte_chunk, base_idxes;\n+\t/* used to mask gather values if size is 2 (16 bit next hops) */\n+\tconst __m512i res_msk = _mm512_set1_epi32(UINT16_MAX);\n+\tconst __rte_x86_zmm_t bswap = {\n+\t\t.u8 = { 2, 1, 0, 255, 6, 5, 4, 255,\n+\t\t\t10, 9, 8, 255, 14, 13, 12, 255,\n+\t\t\t2, 1, 0, 255, 6, 5, 4, 255,\n+\t\t\t10, 9, 8, 255, 14, 13, 12, 255,\n+\t\t\t2, 1, 0, 255, 6, 5, 4, 255,\n+\t\t\t10, 9, 8, 255, 14, 13, 12, 255,\n+\t\t\t2, 1, 0, 255, 6, 5, 4, 255,\n+\t\t\t10, 9, 8, 255, 14, 13, 12, 255\n+\t\t\t},\n+\t};\n+\tconst __mmask64 k = 0x1111111111111111;\n+\tint i = 3;\n+\t__mmask16 msk_ext, new_msk;\n+\t__mmask16 exp_msk = 0x5555;\n+\n+\ttranspose_x16(ips, &first, &second, &third, &fourth);\n+\n+\t/* get_tbl24_idx() for every 4 byte chunk */\n+\tidxes = _mm512_shuffle_epi8(first, bswap.z);\n+\n+\t/**\n+\t * lookup in tbl24\n+\t * Put it inside branch to make compiller happy with -O0\n+\t */\n+\tif (size == sizeof(uint16_t)) {\n+\t\tres = _mm512_i32gather_epi32(idxes, (const int *)dp->tbl24, 2);\n+\t\tres = _mm512_and_epi32(res, res_msk);\n+\t} else\n+\t\tres = _mm512_i32gather_epi32(idxes, (const int *)dp->tbl24, 4);\n+\n+\n+\t/* get extended entries indexes */\n+\tmsk_ext = _mm512_test_epi32_mask(res, lsb);\n+\n+\ttmp = _mm512_srli_epi32(res, 1);\n+\n+\t/* idxes to retrieve bytes */\n+\tshuf_idxes = _mm512_setr_epi32(3, 7, 11, 15,\n+\t\t\t\t19, 23, 27, 31,\n+\t\t\t\t35, 39, 43, 47,\n+\t\t\t\t51, 55, 59, 63);\n+\n+\tbase_idxes = _mm512_setr_epi32(0, 4, 8, 12,\n+\t\t\t\t16, 20, 24, 28,\n+\t\t\t\t32, 36, 40, 44,\n+\t\t\t\t48, 52, 56, 60);\n+\n+\t/* traverse down the trie */\n+\twhile (msk_ext) {\n+\t\tidxes = _mm512_maskz_slli_epi32(msk_ext, tmp, 8);\n+\t\tbyte_chunk = (i < 8) ?\n+\t\t\t((i >= 4) ? second : first) :\n+\t\t\t((i >= 12) ? fourth : third);\n+\t\tbytes = _mm512_maskz_shuffle_epi8(k, byte_chunk, shuf_idxes);\n+\t\tidxes = _mm512_maskz_add_epi32(msk_ext, idxes, bytes);\n+\t\tif (size == sizeof(uint16_t)) {\n+\t\t\ttmp = _mm512_mask_i32gather_epi32(zero, msk_ext,\n+\t\t\t\tidxes, (const int *)dp->tbl8, 2);\n+\t\t\ttmp = _mm512_and_epi32(tmp, res_msk);\n+\t\t} else\n+\t\t\ttmp = _mm512_mask_i32gather_epi32(zero, msk_ext,\n+\t\t\t\tidxes, (const int *)dp->tbl8, 4);\n+\t\tnew_msk = _mm512_test_epi32_mask(tmp, lsb);\n+\t\tres = _mm512_mask_blend_epi32(msk_ext ^ new_msk, res, tmp);\n+\t\ttmp = _mm512_srli_epi32(tmp, 1);\n+\t\tmsk_ext = new_msk;\n+\n+\t\tshuf_idxes = _mm512_maskz_add_epi8(k, shuf_idxes, lsb);\n+\t\tshuf_idxes = _mm512_and_epi32(shuf_idxes, two_lsb);\n+\t\tshuf_idxes = _mm512_maskz_add_epi8(k, shuf_idxes, base_idxes);\n+\t\ti++;\n+\t}\n+\n+\tres = _mm512_srli_epi32(res, 1);\n+\ttmp = _mm512_maskz_expand_epi32(exp_msk, res);\n+\t__m256i tmp256;\n+\ttmp256 = _mm512_extracti32x8_epi32(res, 1);\n+\ttmp2 = _mm512_maskz_expand_epi32(exp_msk,\n+\t\t_mm512_castsi256_si512(tmp256));\n+\t_mm512_storeu_si512(next_hops, tmp);\n+\t_mm512_storeu_si512(next_hops + 8, tmp2);\n+}\n+\n+static void\n+trie_vec_lookup_x8_8b(void *p, uint8_t ips[8][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops)\n+{\n+\tstruct rte_trie_tbl *dp = (struct rte_trie_tbl *)p;\n+\tconst __m512i zero = _mm512_set1_epi32(0);\n+\tconst __m512i lsb = _mm512_set1_epi32(1);\n+\tconst __m512i three_lsb = _mm512_set1_epi32(7);\n+\t__m512i first, second; /*< IPv6 eight byte chunks */\n+\t__m512i idxes, res, shuf_idxes;\n+\t__m512i tmp, bytes, byte_chunk, base_idxes;\n+\tconst __rte_x86_zmm_t bswap = {\n+\t\t.u8 = { 2, 1, 0, 255, 255, 255, 255, 255,\n+\t\t\t10, 9, 8, 255, 255, 255, 255, 255,\n+\t\t\t2, 1, 0, 255, 255, 255, 255, 255,\n+\t\t\t10, 9, 8, 255, 255, 255, 255, 255,\n+\t\t\t2, 1, 0, 255, 255, 255, 255, 255,\n+\t\t\t10, 9, 8, 255, 255, 255, 255, 255,\n+\t\t\t2, 1, 0, 255, 255, 255, 255, 255,\n+\t\t\t10, 9, 8, 255, 255, 255, 255, 255\n+\t\t\t},\n+\t};\n+\tconst __mmask64 k = 0x101010101010101;\n+\tint i = 3;\n+\t__mmask8 msk_ext, new_msk;\n+\n+\ttranspose_x8(ips, &first, &second);\n+\n+\t/* get_tbl24_idx() for every 4 byte chunk */\n+\tidxes = _mm512_shuffle_epi8(first, bswap.z);\n+\n+\t/* lookup in tbl24 */\n+\tres = _mm512_i64gather_epi64(idxes, (const void *)dp->tbl24, 8);\n+\t/* get extended entries indexes */\n+\tmsk_ext = _mm512_test_epi64_mask(res, lsb);\n+\n+\ttmp = _mm512_srli_epi64(res, 1);\n+\n+\t/* idxes to retrieve bytes */\n+\tshuf_idxes = _mm512_setr_epi64(3, 11, 19, 27, 35, 43, 51, 59);\n+\n+\tbase_idxes = _mm512_setr_epi64(0, 8, 16, 24, 32, 40, 48, 56);\n+\n+\t/* traverse down the trie */\n+\twhile (msk_ext) {\n+\t\tidxes = _mm512_maskz_slli_epi64(msk_ext, tmp, 8);\n+\t\tbyte_chunk = (i < 8) ? first : second;\n+\t\tbytes = _mm512_maskz_shuffle_epi8(k, byte_chunk, shuf_idxes);\n+\t\tidxes = _mm512_maskz_add_epi64(msk_ext, idxes, bytes);\n+\t\ttmp = _mm512_mask_i64gather_epi64(zero, msk_ext,\n+\t\t\t\tidxes, (const void *)dp->tbl8, 8);\n+\t\tnew_msk = _mm512_test_epi64_mask(tmp, lsb);\n+\t\tres = _mm512_mask_blend_epi64(msk_ext ^ new_msk, res, tmp);\n+\t\ttmp = _mm512_srli_epi64(tmp, 1);\n+\t\tmsk_ext = new_msk;\n+\n+\t\tshuf_idxes = _mm512_maskz_add_epi8(k, shuf_idxes, lsb);\n+\t\tshuf_idxes = _mm512_and_epi64(shuf_idxes, three_lsb);\n+\t\tshuf_idxes = _mm512_maskz_add_epi8(k, shuf_idxes, base_idxes);\n+\t\ti++;\n+\t}\n+\n+\tres = _mm512_srli_epi64(res, 1);\n+\t_mm512_storeu_si512(next_hops, res);\n+}\n+\n+void\n+rte_trie_vec_lookup_bulk_2b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 16); i++) {\n+\t\ttrie_vec_lookup_x16(p, (uint8_t (*)[16])&ips[i * 16][0],\n+\t\t\t\tnext_hops + i * 16, sizeof(uint16_t));\n+\t}\n+\trte_trie_lookup_bulk_2b(p, (uint8_t (*)[16])&ips[i * 16][0],\n+\t\t\tnext_hops + i * 16, n - i * 16);\n+}\n+\n+void\n+rte_trie_vec_lookup_bulk_4b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 16); i++) {\n+\t\ttrie_vec_lookup_x16(p, (uint8_t (*)[16])&ips[i * 16][0],\n+\t\t\t\tnext_hops + i * 16, sizeof(uint32_t));\n+\t}\n+\trte_trie_lookup_bulk_4b(p, (uint8_t (*)[16])&ips[i * 16][0],\n+\t\t\tnext_hops + i * 16, n - i * 16);\n+}\n+\n+void\n+rte_trie_vec_lookup_bulk_8b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 8); i++) {\n+\t\ttrie_vec_lookup_x8_8b(p, (uint8_t (*)[16])&ips[i * 8][0],\n+\t\t\t\tnext_hops + i * 8);\n+\t}\n+\trte_trie_lookup_bulk_8b(p, (uint8_t (*)[16])&ips[i * 8][0],\n+\t\t\tnext_hops + i * 8, n - i * 8);\n+}\ndiff --git a/lib/librte_fib/trie_avx512.h b/lib/librte_fib/trie_avx512.h\nnew file mode 100644\nindex 0000000..ef8c7f0\n--- /dev/null\n+++ b/lib/librte_fib/trie_avx512.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _TRIE_AVX512_H_\n+#define _TRIE_AVX512_H_\n+\n+void\n+rte_trie_vec_lookup_bulk_2b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+void\n+rte_trie_vec_lookup_bulk_4b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+void\n+rte_trie_vec_lookup_bulk_8b(void *p, uint8_t ips[][RTE_FIB6_IPV6_ADDR_SIZE],\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+#endif /* _TRIE_AVX512_H_ */\n", "prefixes": [ "v13", "6/7" ] }