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GET /api/patches/81324/?format=api
{ "id": 81324, "url": "http://patches.dpdk.org/api/patches/81324/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-42-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-42-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-42-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:58", "name": "[v4,41/58] net/txgbe: add VMDq configure", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "759d8e6e75f99d97c18f17ff8bdae89bbb72b4fb", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-42-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81324/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81324/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1EFACA04DC;\n\tMon, 19 Oct 2020 11:09:13 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BAF0CE22F;\n\tMon, 19 Oct 2020 10:53:55 +0200 (CEST)", "from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33])\n by dpdk.org (Postfix) with ESMTP id 5896EC9B6\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:53:25 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:53:20 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097600tm4u65gho", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "l6IKqkG+NbljIggJHbIPvL6Cl0GInHVJn/vrdby3e8lPgqFrjDD3277kaghBr\n ie/CQl7l2RW1dId9XHzDZIK5GyrsfPf9z/JXaRt3JP+/SpzzC2y9IYzjEMT0IbD4er7turs\n 6iDSODWWBjo9P2+97Il7CtWQuxbpdOWKbPF0pPLqwW6A4HamIMf0/tH/LcBWqL0RjtehUwn\n TfevH5jMjysRQ1d1EQrsIglTpSoznPpMiwRqitBBXvEWxdOJ/C1ozJt5XCzHIp1u0Rjfirf\n Opf/g9IL7BKuOmqjcCTFOhAhIqErVQ8y+S5pf+AeX3W0qftzZyuTC/06ezPznrjVGNlZP2B\n 6/ANbTp3/d049vQIPwir0kyMB3M8Q==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:58 +0800", "Message-Id": "<20201019085415.82207-42-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 41/58] net/txgbe: add VMDq configure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add multiple queue setting with VMDq.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 35 ++++\n drivers/net/txgbe/txgbe_ethdev.h | 2 +\n drivers/net/txgbe/txgbe_rxtx.c | 260 +++++++++++++++++++++++++++++\n 4 files changed, 298 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 022e56d45..578ec05b0 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -15,6 +15,7 @@ LRO = Y\n TSO = Y\n Unicast MAC filter = Y\n Multicast MAC filter = Y\n+VMDq = Y\n SR-IOV = Y\n VLAN filter = Y\n Rate limitation = Y\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex c60df26c8..e14980a2e 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -943,6 +943,17 @@ txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n \treturn 0;\n }\n \n+static void\n+txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\t/* VLNCTL: enable vlan filtering and allow all vlan tags through */\n+\tuint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);\n+\n+\tvlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */\n+\twr32(hw, TXGBE_VLANCTL, vlanctrl);\n+}\n+\n static int\n txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)\n {\n@@ -1330,6 +1341,11 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \t\tgoto error;\n \t}\n \n+\tif (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {\n+\t\t/* Enable vlan filtering for VMDq */\n+\t\ttxgbe_vmdq_vlan_hw_filter_enable(dev);\n+\t}\n+\n \t/* Restore vf rate limit */\n \tif (vfinfo != NULL) {\n \t\tfor (vf = 0; vf < pci_dev->max_vfs; vf++)\n@@ -2765,6 +2781,25 @@ txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)\n \treturn 0;\n }\n \n+uint32_t\n+txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)\n+{\n+\tuint32_t new_val = orig_val;\n+\n+\tif (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)\n+\t\tnew_val |= TXGBE_POOLETHCTL_UTA;\n+\tif (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)\n+\t\tnew_val |= TXGBE_POOLETHCTL_MCHA;\n+\tif (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)\n+\t\tnew_val |= TXGBE_POOLETHCTL_UCHA;\n+\tif (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)\n+\t\tnew_val |= TXGBE_POOLETHCTL_BCA;\n+\tif (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)\n+\t\tnew_val |= TXGBE_POOLETHCTL_MCP;\n+\n+\treturn new_val;\n+}\n+\n static int\n txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n {\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex ba9cab718..bf13e0378 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -256,6 +256,8 @@ void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);\n \n int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);\n \n+uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);\n+\n int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n \t\t\t uint16_t tx_rate, uint64_t q_msk);\n int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,\ndiff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c\nindex fd6a3f436..c8ca9e2d0 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.c\n+++ b/drivers/net/txgbe/txgbe_rxtx.c\n@@ -2555,6 +2555,145 @@ txgbe_dev_free_queues(struct rte_eth_dev *dev)\n \tdev->data->nb_tx_queues = 0;\n }\n \n+static void\n+txgbe_rss_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw;\n+\n+\thw = TXGBE_DEV_HW(dev);\n+\n+\twr32m(hw, TXGBE_RACTL, TXGBE_RACTL_RSSENA, 0);\n+}\n+\n+#define NUM_VFTA_REGISTERS 128\n+\n+/*\n+ * VMDq only support for 10 GbE NIC.\n+ */\n+static void\n+txgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_vmdq_rx_conf *cfg;\n+\tstruct txgbe_hw *hw;\n+\tenum rte_eth_nb_pools num_pools;\n+\tuint32_t mrqc, vt_ctl, vlanctrl;\n+\tuint32_t vmolr = 0;\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = TXGBE_DEV_HW(dev);\n+\tcfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;\n+\tnum_pools = cfg->nb_queue_pools;\n+\n+\ttxgbe_rss_disable(dev);\n+\n+\t/* enable vmdq */\n+\tmrqc = TXGBE_PORTCTL_NUMVT_64;\n+\twr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK, mrqc);\n+\n+\t/* turn on virtualisation and set the default pool */\n+\tvt_ctl = TXGBE_POOLCTL_RPLEN;\n+\tif (cfg->enable_default_pool)\n+\t\tvt_ctl |= TXGBE_POOLCTL_DEFPL(cfg->default_pool);\n+\telse\n+\t\tvt_ctl |= TXGBE_POOLCTL_DEFDSA;\n+\n+\twr32(hw, TXGBE_POOLCTL, vt_ctl);\n+\n+\tfor (i = 0; i < (int)num_pools; i++) {\n+\t\tvmolr = txgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);\n+\t\twr32(hw, TXGBE_POOLETHCTL(i), vmolr);\n+\t}\n+\n+\t/* enable vlan filtering and allow all vlan tags through */\n+\tvlanctrl = rd32(hw, TXGBE_VLANCTL);\n+\tvlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */\n+\twr32(hw, TXGBE_VLANCTL, vlanctrl);\n+\n+\t/* enable all vlan filters */\n+\tfor (i = 0; i < NUM_VFTA_REGISTERS; i++)\n+\t\twr32(hw, TXGBE_VLANTBL(i), UINT32_MAX);\n+\n+\t/* pool enabling for receive - 64 */\n+\twr32(hw, TXGBE_POOLRXENA(0), UINT32_MAX);\n+\tif (num_pools == ETH_64_POOLS)\n+\t\twr32(hw, TXGBE_POOLRXENA(1), UINT32_MAX);\n+\n+\t/*\n+\t * allow pools to read specific mac addresses\n+\t * In this case, all pools should be able to read from mac addr 0\n+\t */\n+\twr32(hw, TXGBE_ETHADDRIDX, 0);\n+\twr32(hw, TXGBE_ETHADDRASSL, 0xFFFFFFFF);\n+\twr32(hw, TXGBE_ETHADDRASSH, 0xFFFFFFFF);\n+\n+\t/* set up filters for vlan tags as configured */\n+\tfor (i = 0; i < cfg->nb_pool_maps; i++) {\n+\t\t/* set vlan id in VF register and set the valid bit */\n+\t\twr32(hw, TXGBE_PSRVLANIDX, i);\n+\t\twr32(hw, TXGBE_PSRVLAN, (TXGBE_PSRVLAN_EA |\n+\t\t\t\tTXGBE_PSRVLAN_VID(cfg->pool_map[i].vlan_id)));\n+\t\t/*\n+\t\t * Put the allowed pools in VFB reg. As we only have 16 or 64\n+\t\t * pools, we only need to use the first half of the register\n+\t\t * i.e. bits 0-31\n+\t\t */\n+\t\tif (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)\n+\t\t\twr32(hw, TXGBE_PSRVLANPLM(0),\n+\t\t\t\t(cfg->pool_map[i].pools & UINT32_MAX));\n+\t\telse\n+\t\t\twr32(hw, TXGBE_PSRVLANPLM(1),\n+\t\t\t\t((cfg->pool_map[i].pools >> 32) & UINT32_MAX));\n+\t}\n+\n+\t/* Tx General Switch Control Enables VMDQ loopback */\n+\tif (cfg->enable_loop_back) {\n+\t\twr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA);\n+\t\tfor (i = 0; i < 64; i++)\n+\t\t\twr32m(hw, TXGBE_POOLETHCTL(i),\n+\t\t\t\tTXGBE_POOLETHCTL_LLB, TXGBE_POOLETHCTL_LLB);\n+\t}\n+\n+\ttxgbe_flush(hw);\n+}\n+\n+/*\n+ * txgbe_vmdq_tx_hw_configure - Configure general VMDq TX parameters\n+ * @hw: pointer to hardware structure\n+ */\n+static void\n+txgbe_vmdq_tx_hw_configure(struct txgbe_hw *hw)\n+{\n+\tuint32_t reg;\n+\tuint32_t q;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\t/*PF VF Transmit Enable*/\n+\twr32(hw, TXGBE_POOLTXENA(0), UINT32_MAX);\n+\twr32(hw, TXGBE_POOLTXENA(1), UINT32_MAX);\n+\n+\t/* Disable the Tx desc arbiter */\n+\treg = rd32(hw, TXGBE_ARBTXCTL);\n+\treg |= TXGBE_ARBTXCTL_DIA;\n+\twr32(hw, TXGBE_ARBTXCTL, reg);\n+\n+\twr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK,\n+\t\tTXGBE_PORTCTL_NUMVT_64);\n+\n+\t/* Disable drop for all queues */\n+\tfor (q = 0; q < 128; q++) {\n+\t\tu32 val = 1 << (q % 32);\n+\t\twr32m(hw, TXGBE_QPRXDROP(q / 32), val, val);\n+\t}\n+\n+\t/* Enable the Tx desc arbiter */\n+\treg = rd32(hw, TXGBE_ARBTXCTL);\n+\treg &= ~TXGBE_ARBTXCTL_DIA;\n+\twr32(hw, TXGBE_ARBTXCTL, reg);\n+\n+\ttxgbe_flush(hw);\n+}\n+\n static int __rte_cold\n txgbe_alloc_rx_queue_mbufs(struct txgbe_rx_queue *rxq)\n {\n@@ -2587,6 +2726,119 @@ txgbe_alloc_rx_queue_mbufs(struct txgbe_rx_queue *rxq)\n \treturn 0;\n }\n \n+static int\n+txgbe_config_vf_default(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t mrqc;\n+\n+\tmrqc = rd32(hw, TXGBE_PORTCTL);\n+\tmrqc &= ~(TXGBE_PORTCTL_NUMTC_MASK | TXGBE_PORTCTL_NUMVT_MASK);\n+\tswitch (RTE_ETH_DEV_SRIOV(dev).active) {\n+\tcase ETH_64_POOLS:\n+\t\tmrqc |= TXGBE_PORTCTL_NUMVT_64;\n+\t\tbreak;\n+\n+\tcase ETH_32_POOLS:\n+\t\tmrqc |= TXGBE_PORTCTL_NUMVT_32;\n+\t\tbreak;\n+\n+\tcase ETH_16_POOLS:\n+\t\tmrqc |= TXGBE_PORTCTL_NUMVT_16;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"invalid pool number in IOV mode\");\n+\t\treturn 0;\n+\t}\n+\n+\twr32(hw, TXGBE_PORTCTL, mrqc);\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)\n+{\n+\tif (RTE_ETH_DEV_SRIOV(dev).active == 0) {\n+\t\t/*\n+\t\t * SRIOV inactive scheme\n+\t\t * VMDq multi-queue setting\n+\t\t */\n+\t\tswitch (dev->data->dev_conf.rxmode.mq_mode) {\n+\t\tcase ETH_MQ_RX_VMDQ_ONLY:\n+\t\t\ttxgbe_vmdq_rx_hw_configure(dev);\n+\t\t\tbreak;\n+\n+\t\tcase ETH_MQ_RX_NONE:\n+\t\tdefault:\n+\t\t\t/* if mq_mode is none, disable rss mode.*/\n+\t\t\ttxgbe_rss_disable(dev);\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\t/* SRIOV active scheme\n+\t\t */\n+\t\tswitch (dev->data->dev_conf.rxmode.mq_mode) {\n+\t\tdefault:\n+\t\t\ttxgbe_config_vf_default(dev);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t mtqc;\n+\tuint32_t rttdcs;\n+\n+\t/* disable arbiter */\n+\trttdcs = rd32(hw, TXGBE_ARBTXCTL);\n+\trttdcs |= TXGBE_ARBTXCTL_DIA;\n+\twr32(hw, TXGBE_ARBTXCTL, rttdcs);\n+\n+\tif (RTE_ETH_DEV_SRIOV(dev).active == 0) {\n+\t\t/*\n+\t\t * SRIOV inactive scheme\n+\t\t * any DCB w/o VMDq multi-queue setting\n+\t\t */\n+\t\tif (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)\n+\t\t\ttxgbe_vmdq_tx_hw_configure(hw);\n+\t\telse\n+\t\t\twr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK, 0);\n+\t} else {\n+\t\tswitch (RTE_ETH_DEV_SRIOV(dev).active) {\n+\t\t/*\n+\t\t * SRIOV active scheme\n+\t\t * FIXME if support DCB together with VMDq & SRIOV\n+\t\t */\n+\t\tcase ETH_64_POOLS:\n+\t\t\tmtqc = TXGBE_PORTCTL_NUMVT_64;\n+\t\t\tbreak;\n+\t\tcase ETH_32_POOLS:\n+\t\t\tmtqc = TXGBE_PORTCTL_NUMVT_32;\n+\t\t\tbreak;\n+\t\tcase ETH_16_POOLS:\n+\t\t\tmtqc = TXGBE_PORTCTL_NUMVT_16;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tmtqc = 0;\n+\t\t\tPMD_INIT_LOG(ERR, \"invalid pool number in IOV mode\");\n+\t\t}\n+\t\twr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK, mtqc);\n+\t}\n+\n+\t/* re-enable arbiter */\n+\trttdcs &= ~TXGBE_ARBTXCTL_DIA;\n+\twr32(hw, TXGBE_ARBTXCTL, rttdcs);\n+\n+\treturn 0;\n+}\n+\n /**\n * txgbe_get_rscctl_maxdesc\n *\n@@ -2919,6 +3171,11 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev)\n \tif (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\tdev->data->scattered_rx = 1;\n \n+\t/*\n+\t * Device configured with multiple RX queues.\n+\t */\n+\ttxgbe_dev_mq_rx_configure(dev);\n+\n \t/*\n \t * Setup the Checksum Register.\n \t * Disable Full-Packet Checksum which is mutually exclusive with RSS.\n@@ -2980,6 +3237,9 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)\n \t\twr32(hw, TXGBE_TXRP(txq->reg_idx), 0);\n \t\twr32(hw, TXGBE_TXWP(txq->reg_idx), 0);\n \t}\n+\n+\t/* Device configured with multiple TX queues. */\n+\ttxgbe_dev_mq_tx_configure(dev);\n }\n \n /*\n", "prefixes": [ "v4", "41/58" ] }