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GET /api/patches/81323/?format=api
{ "id": 81323, "url": "http://patches.dpdk.org/api/patches/81323/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-36-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-36-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-36-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:52", "name": "[v4,35/58] net/txgbe: add queue stats mapping", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b30325db70fe24025e96729486a97b3786885103", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-36-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81323/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D6867A04DC;\n\tMon, 19 Oct 2020 11:08:50 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6019BE22E;\n\tMon, 19 Oct 2020 10:53:54 +0200 (CEST)", "from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52])\n by dpdk.org (Postfix) with ESMTP id AEA59C9B6\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:53:23 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:53:12 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097592tdovmaa0z", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "5p2KJntE3DHgHv0poy6y+YBVGYEnsyeqaLTbIU7LoJQ2jHiX6MBfywc1jqSrN\n 3ihKQbv/NBJgySRr6tNmTOloMXnFhGmD15tapB0zgL45dWrVxExJF6WpI1o12cke83BTcqZ\n r3ph/DDq4zijfM5nVAGBdQD6BPJfU9bRM9KcqTrR3wKZVussmi+mvHua4A5521j1BoG72Zj\n yVNeaUOPpacENVq0vuOLZ3RyjntLqxp9xvXOG3/OfDyOi+7A3Gynbsh8lELGCK5T8236REa\n EtWXlTjj4zV1uW4BOKuwZxtCKbJkBywWZvZduZEIbAfhERKyb7sSIPISKcmHsg6ErWdJ92T\n UYk3aLZ4nWkBB0EjeY6tj5NJoijbQ==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:52 +0800", "Message-Id": "<20201019085415.82207-36-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 35/58] net/txgbe: add queue stats mapping", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add queue stats mapping set, and clear hardware counters.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n drivers/net/txgbe/base/txgbe_hw.c | 118 +++++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_hw.h | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 55 ++++++++++++++\n 4 files changed, 175 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex e18632205..ad7513eca 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -25,6 +25,7 @@ Inner L4 checksum = P\n Packet type parsing = Y\n Basic stats = Y\n Extended stats = Y\n+Stats per queue = Y\n Multiprocess aware = Y\n Linux UIO = Y\n Linux VFIO = Y\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex afd7172a9..5e81464e9 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -115,6 +115,123 @@ s32 txgbe_init_hw(struct txgbe_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * txgbe_clear_hw_cntrs - Generic clear hardware counters\n+ * @hw: pointer to hardware structure\n+ *\n+ * Clears all hardware statistics counters by reading them from the hardware\n+ * Statistics counters are clear on read.\n+ **/\n+s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)\n+{\n+\tu16 i = 0;\n+\n+\tDEBUGFUNC(\"txgbe_clear_hw_cntrs\");\n+\n+\t/* QP Stats */\n+\t/* don't write clear queue stats */\n+\tfor (i = 0; i < TXGBE_MAX_QP; i++) {\n+\t\thw->qp_last[i].rx_qp_packets = 0;\n+\t\thw->qp_last[i].tx_qp_packets = 0;\n+\t\thw->qp_last[i].rx_qp_bytes = 0;\n+\t\thw->qp_last[i].tx_qp_bytes = 0;\n+\t\thw->qp_last[i].rx_qp_mc_packets = 0;\n+\t}\n+\n+\t/* PB Stats */\n+\tfor (i = 0; i < TXGBE_MAX_UP; i++) {\n+\t\trd32(hw, TXGBE_PBRXUPXON(i));\n+\t\trd32(hw, TXGBE_PBRXUPXOFF(i));\n+\t\trd32(hw, TXGBE_PBTXUPXON(i));\n+\t\trd32(hw, TXGBE_PBTXUPXOFF(i));\n+\t\trd32(hw, TXGBE_PBTXUPOFF(i));\n+\n+\t\trd32(hw, TXGBE_PBRXMISS(i));\n+\t}\n+\trd32(hw, TXGBE_PBRXLNKXON);\n+\trd32(hw, TXGBE_PBRXLNKXOFF);\n+\trd32(hw, TXGBE_PBTXLNKXON);\n+\trd32(hw, TXGBE_PBTXLNKXOFF);\n+\n+\t/* DMA Stats */\n+\trd32(hw, TXGBE_DMARXPKT);\n+\trd32(hw, TXGBE_DMATXPKT);\n+\n+\trd64(hw, TXGBE_DMARXOCTL);\n+\trd64(hw, TXGBE_DMATXOCTL);\n+\n+\t/* MAC Stats */\n+\trd64(hw, TXGBE_MACRXERRCRCL);\n+\trd64(hw, TXGBE_MACRXMPKTL);\n+\trd64(hw, TXGBE_MACTXMPKTL);\n+\n+\trd64(hw, TXGBE_MACRXPKTL);\n+\trd64(hw, TXGBE_MACTXPKTL);\n+\trd64(hw, TXGBE_MACRXGBOCTL);\n+\n+\trd64(hw, TXGBE_MACRXOCTL);\n+\trd32(hw, TXGBE_MACTXOCTL);\n+\n+\trd64(hw, TXGBE_MACRX1TO64L);\n+\trd64(hw, TXGBE_MACRX65TO127L);\n+\trd64(hw, TXGBE_MACRX128TO255L);\n+\trd64(hw, TXGBE_MACRX256TO511L);\n+\trd64(hw, TXGBE_MACRX512TO1023L);\n+\trd64(hw, TXGBE_MACRX1024TOMAXL);\n+\trd64(hw, TXGBE_MACTX1TO64L);\n+\trd64(hw, TXGBE_MACTX65TO127L);\n+\trd64(hw, TXGBE_MACTX128TO255L);\n+\trd64(hw, TXGBE_MACTX256TO511L);\n+\trd64(hw, TXGBE_MACTX512TO1023L);\n+\trd64(hw, TXGBE_MACTX1024TOMAXL);\n+\n+\trd64(hw, TXGBE_MACRXERRLENL);\n+\trd32(hw, TXGBE_MACRXOVERSIZE);\n+\trd32(hw, TXGBE_MACRXJABBER);\n+\n+\t/* FCoE Stats */\n+\trd32(hw, TXGBE_FCOECRC);\n+\trd32(hw, TXGBE_FCOELAST);\n+\trd32(hw, TXGBE_FCOERPDC);\n+\trd32(hw, TXGBE_FCOEPRC);\n+\trd32(hw, TXGBE_FCOEPTC);\n+\trd32(hw, TXGBE_FCOEDWRC);\n+\trd32(hw, TXGBE_FCOEDWTC);\n+\n+\t/* Flow Director Stats */\n+\trd32(hw, TXGBE_FDIRMATCH);\n+\trd32(hw, TXGBE_FDIRMISS);\n+\trd32(hw, TXGBE_FDIRUSED);\n+\trd32(hw, TXGBE_FDIRUSED);\n+\trd32(hw, TXGBE_FDIRFAIL);\n+\trd32(hw, TXGBE_FDIRFAIL);\n+\n+\t/* MACsec Stats */\n+\trd32(hw, TXGBE_LSECTX_UTPKT);\n+\trd32(hw, TXGBE_LSECTX_ENCPKT);\n+\trd32(hw, TXGBE_LSECTX_PROTPKT);\n+\trd32(hw, TXGBE_LSECTX_ENCOCT);\n+\trd32(hw, TXGBE_LSECTX_PROTOCT);\n+\trd32(hw, TXGBE_LSECRX_UTPKT);\n+\trd32(hw, TXGBE_LSECRX_BTPKT);\n+\trd32(hw, TXGBE_LSECRX_NOSCIPKT);\n+\trd32(hw, TXGBE_LSECRX_UNSCIPKT);\n+\trd32(hw, TXGBE_LSECRX_DECOCT);\n+\trd32(hw, TXGBE_LSECRX_VLDOCT);\n+\trd32(hw, TXGBE_LSECRX_UNCHKPKT);\n+\trd32(hw, TXGBE_LSECRX_DLYPKT);\n+\trd32(hw, TXGBE_LSECRX_LATEPKT);\n+\tfor (i = 0; i < 2; i++) {\n+\t\trd32(hw, TXGBE_LSECRX_OKPKT(i));\n+\t\trd32(hw, TXGBE_LSECRX_INVPKT(i));\n+\t\trd32(hw, TXGBE_LSECRX_BADPKT(i));\n+\t}\n+\trd32(hw, TXGBE_LSECRX_INVSAPKT);\n+\trd32(hw, TXGBE_LSECRX_BADSAPKT);\n+\n+\treturn 0;\n+}\n+\n /**\n * txgbe_get_mac_addr - Generic get MAC address\n * @hw: pointer to hardware structure\n@@ -1455,6 +1572,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)\n \t/* MAC */\n \tmac->init_hw = txgbe_init_hw;\n \tmac->start_hw = txgbe_start_hw_raptor;\n+\tmac->clear_hw_cntrs = txgbe_clear_hw_cntrs;\n \tmac->enable_rx_dma = txgbe_enable_rx_dma_raptor;\n \tmac->get_mac_addr = txgbe_get_mac_addr;\n \tmac->stop_hw = txgbe_stop_hw;\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h\nindex f0435976d..48543b951 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.h\n+++ b/drivers/net/txgbe/base/txgbe_hw.h\n@@ -11,6 +11,7 @@ s32 txgbe_init_hw(struct txgbe_hw *hw);\n s32 txgbe_start_hw(struct txgbe_hw *hw);\n s32 txgbe_stop_hw(struct txgbe_hw *hw);\n s32 txgbe_start_hw_gen2(struct txgbe_hw *hw);\n+s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw);\n s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr);\n \n void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw);\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 9ead046e1..e6b0489d7 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -261,6 +261,60 @@ txgbe_disable_intr(struct txgbe_hw *hw)\n \ttxgbe_flush(hw);\n }\n \n+static int\n+txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint16_t queue_id,\n+\t\t\t\t uint8_t stat_idx,\n+\t\t\t\t uint8_t is_rx)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);\n+\tstruct txgbe_stat_mappings *stat_mappings =\n+\t\tTXGBE_DEV_STAT_MAPPINGS(eth_dev);\n+\tuint32_t qsmr_mask = 0;\n+\tuint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;\n+\tuint32_t q_map;\n+\tuint8_t n, offset;\n+\n+\tif (hw->mac.type != txgbe_mac_raptor)\n+\t\treturn -ENOSYS;\n+\n+\tif (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)\n+\t\treturn -EIO;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Setting port %d, %s queue_id %d to stat index %d\",\n+\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n+\t\t queue_id, stat_idx);\n+\n+\tn = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);\n+\tif (n >= TXGBE_NB_STAT_MAPPING) {\n+\t\tPMD_INIT_LOG(ERR, \"Nb of stat mapping registers exceeded\");\n+\t\treturn -EIO;\n+\t}\n+\toffset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);\n+\n+\t/* Now clear any previous stat_idx set */\n+\tclearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n+\tif (!is_rx)\n+\t\tstat_mappings->tqsm[n] &= ~clearing_mask;\n+\telse\n+\t\tstat_mappings->rqsm[n] &= ~clearing_mask;\n+\n+\tq_map = (uint32_t)stat_idx;\n+\tq_map &= QMAP_FIELD_RESERVED_BITS_MASK;\n+\tqsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n+\tif (!is_rx)\n+\t\tstat_mappings->tqsm[n] |= qsmr_mask;\n+\telse\n+\t\tstat_mappings->rqsm[n] |= qsmr_mask;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Set port %d, %s queue_id %d to stat index %d\",\n+\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n+\t\t queue_id, stat_idx);\n+\tPMD_INIT_LOG(DEBUG, \"%s[%d] = 0x%08x\", is_rx ? \"RQSMR\" : \"TQSM\", n,\n+\t\t is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);\n+\treturn 0;\n+}\n+\n static int\n eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n {\n@@ -2375,6 +2429,7 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.xstats_reset = txgbe_dev_xstats_reset,\n \t.xstats_get_names = txgbe_dev_xstats_get_names,\n \t.xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,\n+\t.queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,\n \t.dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,\n \t.rx_queue_start\t = txgbe_dev_rx_queue_start,\n \t.rx_queue_stop = txgbe_dev_rx_queue_stop,\n", "prefixes": [ "v4", "35/58" ] }