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GET /api/patches/81318/?format=api
{ "id": 81318, "url": "http://patches.dpdk.org/api/patches/81318/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-34-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-34-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-34-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:50", "name": "[v4,33/58] net/txgbe: add device stats get", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d23cb0fd7dcf583009402244bdd1e5f940fe69d3", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-34-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81318/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/81318/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 97E3CA04DC;\n\tMon, 19 Oct 2020 11:06:57 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C71F8CFCF;\n\tMon, 19 Oct 2020 10:53:47 +0200 (CEST)", "from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142])\n by dpdk.org (Postfix) with ESMTP id 811FCC8C6\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:53:13 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:53:09 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097590toq5x867r", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "rhYPnIpFJeQJRDUjP7Uy/V6f+j5XBImoAgbNjkycvunwwTftmakv7q5jnTlAC\n 7ULqxzvMwgkEpjRXNW2kEoRVnul/9K+wCmhas2Bc9E272hzeQfXBpwZ0hO9NreUqg2/yrKf\n carcgkZTPCOHLXfbY/BAZ87slLoGxnHD8SxI4Rg0pm4k6Wjy2NJj3re3yGNx3ozVl6Z3pW0\n LX+qSYA+xf5HRZF79XtIPg5pw/eMOp67e+wgh6vep8u5CaDPDBGgZQvMG/eLiUNLIlXF9jG\n 58cG5PYGsiLhLPUjkddSNJwUd/p/z0+3rDGTEKVjbBPJ0XH/0doiQ9SN9T3IPzXmGVu01j+\n v+LYE5TvMiUbKBDEDw=", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:50 +0800", "Message-Id": "<20201019085415.82207-34-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign6", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 33/58] net/txgbe: add device stats get", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add device stats get from reading hardware registers.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n doc/guides/nics/txgbe.rst | 1 +\n drivers/net/txgbe/base/txgbe_regs.h | 48 ++---\n drivers/net/txgbe/base/txgbe_type.h | 155 ++++++++++++++++\n drivers/net/txgbe/txgbe_ethdev.c | 271 ++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_ethdev.h | 19 ++\n 6 files changed, 471 insertions(+), 24 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex b2f5f832c..32df33dfc 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -23,6 +23,7 @@ L4 checksum offload = P\n Inner L3 checksum = P\n Inner L4 checksum = P\n Packet type parsing = Y\n+Basic stats = Y\n Multiprocess aware = Y\n Linux UIO = Y\n Linux VFIO = Y\ndiff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst\nindex 1bf4b6b6f..b020aaf98 100644\n--- a/doc/guides/nics/txgbe.rst\n+++ b/doc/guides/nics/txgbe.rst\n@@ -15,6 +15,7 @@ Features\n - Packet type information\n - Checksum offload\n - TSO offload\n+- Port hardware statistics\n - Jumbo frames\n - Link state information\n - Interrupt mode for RX\ndiff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h\nindex 607e1df29..052609e3c 100644\n--- a/drivers/net/txgbe/base/txgbe_regs.h\n+++ b/drivers/net/txgbe/base/txgbe_regs.h\n@@ -1071,30 +1071,30 @@ enum txgbe_5tuple_protocol {\n #define TXGBE_MACRXERRCRCH 0x01192C\n #define TXGBE_MACRXERRLENL 0x011978\n #define TXGBE_MACRXERRLENH 0x01197C\n-#define TXGBE_MACRX1to64L 0x001940\n-#define TXGBE_MACRX1to64H 0x001944\n-#define TXGBE_MACRX65to127L 0x001948\n-#define TXGBE_MACRX65to127H 0x00194C\n-#define TXGBE_MACRX128to255L 0x001950\n-#define TXGBE_MACRX128to255H 0x001954\n-#define TXGBE_MACRX256to511L 0x001958\n-#define TXGBE_MACRX256to511H 0x00195C\n-#define TXGBE_MACRX512to1023L 0x001960\n-#define TXGBE_MACRX512to1023H 0x001964\n-#define TXGBE_MACRX1024toMAXL 0x001968\n-#define TXGBE_MACRX1024toMAXH 0x00196C\n-#define TXGBE_MACTX1to64L 0x001834\n-#define TXGBE_MACTX1to64H 0x001838\n-#define TXGBE_MACTX65to127L 0x00183C\n-#define TXGBE_MACTX65to127H 0x001840\n-#define TXGBE_MACTX128to255L 0x001844\n-#define TXGBE_MACTX128to255H 0x001848\n-#define TXGBE_MACTX256to511L 0x00184C\n-#define TXGBE_MACTX256to511H 0x001850\n-#define TXGBE_MACTX512to1023L 0x001854\n-#define TXGBE_MACTX512to1023H 0x001858\n-#define TXGBE_MACTX1024toMAXL 0x00185C\n-#define TXGBE_MACTX1024toMAXH 0x001860\n+#define TXGBE_MACRX1TO64L 0x001940\n+#define TXGBE_MACRX1TO64H 0x001944\n+#define TXGBE_MACRX65TO127L 0x001948\n+#define TXGBE_MACRX65TO127H 0x00194C\n+#define TXGBE_MACRX128TO255L 0x001950\n+#define TXGBE_MACRX128TO255H 0x001954\n+#define TXGBE_MACRX256TO511L 0x001958\n+#define TXGBE_MACRX256TO511H 0x00195C\n+#define TXGBE_MACRX512TO1023L 0x001960\n+#define TXGBE_MACRX512TO1023H 0x001964\n+#define TXGBE_MACRX1024TOMAXL 0x001968\n+#define TXGBE_MACRX1024TOMAXH 0x00196C\n+#define TXGBE_MACTX1TO64L 0x001834\n+#define TXGBE_MACTX1TO64H 0x001838\n+#define TXGBE_MACTX65TO127L 0x00183C\n+#define TXGBE_MACTX65TO127H 0x001840\n+#define TXGBE_MACTX128TO255L 0x001844\n+#define TXGBE_MACTX128TO255H 0x001848\n+#define TXGBE_MACTX256TO511L 0x00184C\n+#define TXGBE_MACTX256TO511H 0x001850\n+#define TXGBE_MACTX512TO1023L 0x001854\n+#define TXGBE_MACTX512TO1023H 0x001858\n+#define TXGBE_MACTX1024TOMAXL 0x00185C\n+#define TXGBE_MACTX1024TOMAXH 0x001860\n \n #define TXGBE_MACRXUNDERSIZE 0x011938\n #define TXGBE_MACRXOVERSIZE 0x01193C\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex d21e9475c..76f769008 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -10,6 +10,8 @@\n \n #define TXGBE_FRAME_SIZE_MAX\t(9728) /* Maximum frame size, +FCS */\n #define TXGBE_FRAME_SIZE_DFT\t(1518) /* Default frame size, +FCS */\n+#define TXGBE_MAX_UP\t\t8\n+#define TXGBE_MAX_QP\t\t(128)\n #define TXGBE_MAX_UTA\t\t128\n \n #define TXGBE_ALIGN\t\t128 /* as intel did */\n@@ -206,6 +208,151 @@ struct txgbe_bus_info {\n \tu16 instance_id;\n };\n \n+/* Statistics counters collected by the MAC */\n+/* PB[] RxTx */\n+struct txgbe_pb_stats {\n+\tu64 tx_pb_xon_packets;\n+\tu64 rx_pb_xon_packets;\n+\tu64 tx_pb_xoff_packets;\n+\tu64 rx_pb_xoff_packets;\n+\tu64 rx_pb_dropped;\n+\tu64 rx_pb_mbuf_alloc_errors;\n+\tu64 tx_pb_xon2off_packets;\n+};\n+\n+/* QP[] RxTx */\n+struct txgbe_qp_stats {\n+\tu64 rx_qp_packets;\n+\tu64 tx_qp_packets;\n+\tu64 rx_qp_bytes;\n+\tu64 tx_qp_bytes;\n+\tu64 rx_qp_mc_packets;\n+};\n+\n+struct txgbe_hw_stats {\n+\t/* MNG RxTx */\n+\tu64 mng_bmc2host_packets;\n+\tu64 mng_host2bmc_packets;\n+\t/* Basix RxTx */\n+\tu64 rx_packets;\n+\tu64 tx_packets;\n+\tu64 rx_bytes;\n+\tu64 tx_bytes;\n+\tu64 rx_total_bytes;\n+\tu64 rx_total_packets;\n+\tu64 tx_total_packets;\n+\tu64 rx_total_missed_packets;\n+\tu64 rx_broadcast_packets;\n+\tu64 tx_broadcast_packets;\n+\tu64 rx_multicast_packets;\n+\tu64 tx_multicast_packets;\n+\tu64 rx_management_packets;\n+\tu64 tx_management_packets;\n+\tu64 rx_management_dropped;\n+\tu64 rx_drop_packets;\n+\n+\t/* Basic Error */\n+\tu64 rx_crc_errors;\n+\tu64 rx_illegal_byte_errors;\n+\tu64 rx_error_bytes;\n+\tu64 rx_mac_short_packet_dropped;\n+\tu64 rx_length_errors;\n+\tu64 rx_undersize_errors;\n+\tu64 rx_fragment_errors;\n+\tu64 rx_oversize_errors;\n+\tu64 rx_jabber_errors;\n+\tu64 rx_l3_l4_xsum_error;\n+\tu64 mac_local_errors;\n+\tu64 mac_remote_errors;\n+\n+\t/* Flow Director */\n+\tu64 flow_director_added_filters;\n+\tu64 flow_director_removed_filters;\n+\tu64 flow_director_filter_add_errors;\n+\tu64 flow_director_filter_remove_errors;\n+\tu64 flow_director_matched_filters;\n+\tu64 flow_director_missed_filters;\n+\n+\t/* FCoE */\n+\tu64 rx_fcoe_crc_errors;\n+\tu64 rx_fcoe_mbuf_allocation_errors;\n+\tu64 rx_fcoe_dropped;\n+\tu64 rx_fcoe_packets;\n+\tu64 tx_fcoe_packets;\n+\tu64 rx_fcoe_bytes;\n+\tu64 tx_fcoe_bytes;\n+\tu64 rx_fcoe_no_ddp;\n+\tu64 rx_fcoe_no_ddp_ext_buff;\n+\n+\t/* MACSEC */\n+\tu64 tx_macsec_pkts_untagged;\n+\tu64 tx_macsec_pkts_encrypted;\n+\tu64 tx_macsec_pkts_protected;\n+\tu64 tx_macsec_octets_encrypted;\n+\tu64 tx_macsec_octets_protected;\n+\tu64 rx_macsec_pkts_untagged;\n+\tu64 rx_macsec_pkts_badtag;\n+\tu64 rx_macsec_pkts_nosci;\n+\tu64 rx_macsec_pkts_unknownsci;\n+\tu64 rx_macsec_octets_decrypted;\n+\tu64 rx_macsec_octets_validated;\n+\tu64 rx_macsec_sc_pkts_unchecked;\n+\tu64 rx_macsec_sc_pkts_delayed;\n+\tu64 rx_macsec_sc_pkts_late;\n+\tu64 rx_macsec_sa_pkts_ok;\n+\tu64 rx_macsec_sa_pkts_invalid;\n+\tu64 rx_macsec_sa_pkts_notvalid;\n+\tu64 rx_macsec_sa_pkts_unusedsa;\n+\tu64 rx_macsec_sa_pkts_notusingsa;\n+\n+\t/* MAC RxTx */\n+\tu64 rx_size_64_packets;\n+\tu64 rx_size_65_to_127_packets;\n+\tu64 rx_size_128_to_255_packets;\n+\tu64 rx_size_256_to_511_packets;\n+\tu64 rx_size_512_to_1023_packets;\n+\tu64 rx_size_1024_to_max_packets;\n+\tu64 tx_size_64_packets;\n+\tu64 tx_size_65_to_127_packets;\n+\tu64 tx_size_128_to_255_packets;\n+\tu64 tx_size_256_to_511_packets;\n+\tu64 tx_size_512_to_1023_packets;\n+\tu64 tx_size_1024_to_max_packets;\n+\n+\t/* Flow Control */\n+\tu64 tx_xon_packets;\n+\tu64 rx_xon_packets;\n+\tu64 tx_xoff_packets;\n+\tu64 rx_xoff_packets;\n+\n+\t/* PB[] RxTx */\n+\tstruct {\n+\t\tu64 rx_up_packets;\n+\t\tu64 tx_up_packets;\n+\t\tu64 rx_up_bytes;\n+\t\tu64 tx_up_bytes;\n+\t\tu64 rx_up_drop_packets;\n+\n+\t\tu64 tx_up_xon_packets;\n+\t\tu64 rx_up_xon_packets;\n+\t\tu64 tx_up_xoff_packets;\n+\t\tu64 rx_up_xoff_packets;\n+\t\tu64 rx_up_dropped;\n+\t\tu64 rx_up_mbuf_alloc_errors;\n+\t\tu64 tx_up_xon2off_packets;\n+\t} up[TXGBE_MAX_UP];\n+\n+\t/* QP[] RxTx */\n+\tstruct {\n+\t\tu64 rx_qp_packets;\n+\t\tu64 tx_qp_packets;\n+\t\tu64 rx_qp_bytes;\n+\t\tu64 tx_qp_bytes;\n+\t\tu64 rx_qp_mc_packets;\n+\t} qp[TXGBE_MAX_QP];\n+\n+};\n+\n /* iterator type for walking multicast address lists */\n typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,\n \t\t\t\t u32 *vmdq);\n@@ -488,6 +635,14 @@ struct txgbe_hw {\n \n \tu32 q_rx_regs[128 * 4];\n \tu32 q_tx_regs[128 * 4];\n+\tbool offset_loaded;\n+\tstruct {\n+\t\tu64 rx_qp_packets;\n+\t\tu64 tx_qp_packets;\n+\t\tu64 rx_qp_bytes;\n+\t\tu64 tx_qp_bytes;\n+\t\tu64 rx_qp_mc_packets;\n+\t} qp_last[TXGBE_MAX_QP];\n };\n \n #include \"txgbe_regs.h\"\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex d74d822ad..f299fae29 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -27,6 +27,7 @@ static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);\n static int txgbe_dev_close(struct rte_eth_dev *dev);\n static int txgbe_dev_link_update(struct rte_eth_dev *dev,\n \t\t\t\tint wait_to_complete);\n+static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);\n \n static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);\n static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);\n@@ -236,6 +237,9 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \t\treturn -EIO;\n \t}\n \n+\t/* Reset the hw statistics */\n+\ttxgbe_dev_stats_reset(eth_dev);\n+\n \t/* disable interrupt */\n \ttxgbe_disable_intr(hw);\n \n@@ -568,6 +572,7 @@ static int\n txgbe_dev_start(struct rte_eth_dev *dev)\n {\n \tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tuint32_t intr_vector = 0;\n@@ -749,6 +754,9 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \n \twr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);\n \n+\ttxgbe_read_stats_registers(hw, hw_stats);\n+\thw->offset_loaded = 1;\n+\n \treturn 0;\n \n error:\n@@ -942,6 +950,267 @@ txgbe_dev_reset(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+#define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \\\n+\t{ \\\n+\t\tuint32_t current_counter = rd32(hw, reg); \\\n+\t\tif (current_counter < last_counter) \\\n+\t\t\tcurrent_counter += 0x100000000LL; \\\n+\t\tif (!hw->offset_loaded) \\\n+\t\t\tlast_counter = current_counter; \\\n+\t\tcounter = current_counter - last_counter; \\\n+\t\tcounter &= 0xFFFFFFFFLL; \\\n+\t}\n+\n+#define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \\\n+\t{ \\\n+\t\tuint64_t current_counter_lsb = rd32(hw, reg_lsb); \\\n+\t\tuint64_t current_counter_msb = rd32(hw, reg_msb); \\\n+\t\tuint64_t current_counter = (current_counter_msb << 32) | \\\n+\t\t\tcurrent_counter_lsb; \\\n+\t\tif (current_counter < last_counter) \\\n+\t\t\tcurrent_counter += 0x1000000000LL; \\\n+\t\tif (!hw->offset_loaded) \\\n+\t\t\tlast_counter = current_counter; \\\n+\t\tcounter = current_counter - last_counter; \\\n+\t\tcounter &= 0xFFFFFFFFFLL; \\\n+\t}\n+\n+void\n+txgbe_read_stats_registers(struct txgbe_hw *hw,\n+\t\t\t struct txgbe_hw_stats *hw_stats)\n+{\n+\tunsigned int i;\n+\n+\t/* QP Stats */\n+\tfor (i = 0; i < hw->nb_rx_queues; i++) {\n+\t\tUPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),\n+\t\t\thw->qp_last[i].rx_qp_packets,\n+\t\t\thw_stats->qp[i].rx_qp_packets);\n+\t\tUPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),\n+\t\t\thw->qp_last[i].rx_qp_bytes,\n+\t\t\thw_stats->qp[i].rx_qp_bytes);\n+\t\tUPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),\n+\t\t\thw->qp_last[i].rx_qp_mc_packets,\n+\t\t\thw_stats->qp[i].rx_qp_mc_packets);\n+\t}\n+\n+\tfor (i = 0; i < hw->nb_tx_queues; i++) {\n+\t\tUPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),\n+\t\t\thw->qp_last[i].tx_qp_packets,\n+\t\t\thw_stats->qp[i].tx_qp_packets);\n+\t\tUPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),\n+\t\t\thw->qp_last[i].tx_qp_bytes,\n+\t\t\thw_stats->qp[i].tx_qp_bytes);\n+\t}\n+\t/* PB Stats */\n+\tfor (i = 0; i < TXGBE_MAX_UP; i++) {\n+\t\thw_stats->up[i].rx_up_xon_packets +=\n+\t\t\t\trd32(hw, TXGBE_PBRXUPXON(i));\n+\t\thw_stats->up[i].rx_up_xoff_packets +=\n+\t\t\t\trd32(hw, TXGBE_PBRXUPXOFF(i));\n+\t\thw_stats->up[i].tx_up_xon_packets +=\n+\t\t\t\trd32(hw, TXGBE_PBTXUPXON(i));\n+\t\thw_stats->up[i].tx_up_xoff_packets +=\n+\t\t\t\trd32(hw, TXGBE_PBTXUPXOFF(i));\n+\t\thw_stats->up[i].tx_up_xon2off_packets +=\n+\t\t\t\trd32(hw, TXGBE_PBTXUPOFF(i));\n+\t\thw_stats->up[i].rx_up_dropped +=\n+\t\t\t\trd32(hw, TXGBE_PBRXMISS(i));\n+\t}\n+\thw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);\n+\thw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);\n+\thw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);\n+\thw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);\n+\n+\t/* DMA Stats */\n+\thw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);\n+\thw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);\n+\n+\thw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);\n+\thw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);\n+\thw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);\n+\n+\t/* MAC Stats */\n+\thw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);\n+\thw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);\n+\thw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);\n+\n+\thw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);\n+\thw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);\n+\thw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);\n+\n+\thw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);\n+\thw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);\n+\n+\thw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);\n+\thw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);\n+\thw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);\n+\thw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);\n+\thw_stats->rx_size_512_to_1023_packets +=\n+\t\t\trd64(hw, TXGBE_MACRX512TO1023L);\n+\thw_stats->rx_size_1024_to_max_packets +=\n+\t\t\trd64(hw, TXGBE_MACRX1024TOMAXL);\n+\thw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);\n+\thw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);\n+\thw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);\n+\thw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);\n+\thw_stats->tx_size_512_to_1023_packets +=\n+\t\t\trd64(hw, TXGBE_MACTX512TO1023L);\n+\thw_stats->tx_size_1024_to_max_packets +=\n+\t\t\trd64(hw, TXGBE_MACTX1024TOMAXL);\n+\n+\thw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);\n+\thw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);\n+\thw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);\n+\n+\t/* MNG Stats */\n+\thw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);\n+\thw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);\n+\thw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);\n+\thw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);\n+\n+\t/* FCoE Stats */\n+\thw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);\n+\thw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);\n+\thw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);\n+\thw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);\n+\thw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);\n+\thw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);\n+\thw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);\n+\n+\t/* Flow Director Stats */\n+\thw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);\n+\thw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);\n+\thw_stats->flow_director_added_filters +=\n+\t\tTXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));\n+\thw_stats->flow_director_removed_filters +=\n+\t\tTXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));\n+\thw_stats->flow_director_filter_add_errors +=\n+\t\tTXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));\n+\thw_stats->flow_director_filter_remove_errors +=\n+\t\tTXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));\n+\n+\t/* MACsec Stats */\n+\thw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);\n+\thw_stats->tx_macsec_pkts_encrypted +=\n+\t\t\trd32(hw, TXGBE_LSECTX_ENCPKT);\n+\thw_stats->tx_macsec_pkts_protected +=\n+\t\t\trd32(hw, TXGBE_LSECTX_PROTPKT);\n+\thw_stats->tx_macsec_octets_encrypted +=\n+\t\t\trd32(hw, TXGBE_LSECTX_ENCOCT);\n+\thw_stats->tx_macsec_octets_protected +=\n+\t\t\trd32(hw, TXGBE_LSECTX_PROTOCT);\n+\thw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);\n+\thw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);\n+\thw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);\n+\thw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);\n+\thw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);\n+\thw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);\n+\thw_stats->rx_macsec_sc_pkts_unchecked +=\n+\t\t\trd32(hw, TXGBE_LSECRX_UNCHKPKT);\n+\thw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);\n+\thw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);\n+\tfor (i = 0; i < 2; i++) {\n+\t\thw_stats->rx_macsec_sa_pkts_ok +=\n+\t\t\trd32(hw, TXGBE_LSECRX_OKPKT(i));\n+\t\thw_stats->rx_macsec_sa_pkts_invalid +=\n+\t\t\trd32(hw, TXGBE_LSECRX_INVPKT(i));\n+\t\thw_stats->rx_macsec_sa_pkts_notvalid +=\n+\t\t\trd32(hw, TXGBE_LSECRX_BADPKT(i));\n+\t}\n+\thw_stats->rx_macsec_sa_pkts_unusedsa +=\n+\t\t\trd32(hw, TXGBE_LSECRX_INVSAPKT);\n+\thw_stats->rx_macsec_sa_pkts_notusingsa +=\n+\t\t\trd32(hw, TXGBE_LSECRX_BADSAPKT);\n+\n+\thw_stats->rx_total_missed_packets = 0;\n+\tfor (i = 0; i < TXGBE_MAX_UP; i++) {\n+\t\thw_stats->rx_total_missed_packets +=\n+\t\t\thw_stats->up[i].rx_up_dropped;\n+\t}\n+}\n+\n+static int\n+txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);\n+\tstruct txgbe_stat_mappings *stat_mappings =\n+\t\t\tTXGBE_DEV_STAT_MAPPINGS(dev);\n+\tuint32_t i, j;\n+\n+\ttxgbe_read_stats_registers(hw, hw_stats);\n+\n+\tif (stats == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Fill out the rte_eth_stats statistics structure */\n+\tstats->ipackets = hw_stats->rx_packets;\n+\tstats->ibytes = hw_stats->rx_bytes;\n+\tstats->opackets = hw_stats->tx_packets;\n+\tstats->obytes = hw_stats->tx_bytes;\n+\n+\tmemset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));\n+\tmemset(&stats->q_opackets, 0, sizeof(stats->q_opackets));\n+\tmemset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));\n+\tmemset(&stats->q_obytes, 0, sizeof(stats->q_obytes));\n+\tmemset(&stats->q_errors, 0, sizeof(stats->q_errors));\n+\tfor (i = 0; i < TXGBE_MAX_QP; i++) {\n+\t\tuint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;\n+\t\tuint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;\n+\t\tuint32_t q_map;\n+\n+\t\tq_map = (stat_mappings->rqsm[n] >> offset)\n+\t\t\t\t& QMAP_FIELD_RESERVED_BITS_MASK;\n+\t\tj = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS\n+\t\t ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);\n+\t\tstats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;\n+\t\tstats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;\n+\n+\t\tq_map = (stat_mappings->tqsm[n] >> offset)\n+\t\t\t\t& QMAP_FIELD_RESERVED_BITS_MASK;\n+\t\tj = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS\n+\t\t ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);\n+\t\tstats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;\n+\t\tstats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;\n+\t}\n+\n+\t/* Rx Errors */\n+\tstats->imissed = hw_stats->rx_total_missed_packets;\n+\tstats->ierrors = hw_stats->rx_crc_errors +\n+\t\t\t hw_stats->rx_mac_short_packet_dropped +\n+\t\t\t hw_stats->rx_length_errors +\n+\t\t\t hw_stats->rx_undersize_errors +\n+\t\t\t hw_stats->rx_oversize_errors +\n+\t\t\t hw_stats->rx_drop_packets +\n+\t\t\t hw_stats->rx_illegal_byte_errors +\n+\t\t\t hw_stats->rx_error_bytes +\n+\t\t\t hw_stats->rx_fragment_errors +\n+\t\t\t hw_stats->rx_fcoe_crc_errors +\n+\t\t\t hw_stats->rx_fcoe_mbuf_allocation_errors;\n+\n+\t/* Tx Errors */\n+\tstats->oerrors = 0;\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_dev_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);\n+\n+\t/* HW registers are cleared on read */\n+\thw->offset_loaded = 0;\n+\ttxgbe_dev_stats_get(dev, NULL);\n+\thw->offset_loaded = 1;\n+\n+\t/* Reset software totals */\n+\tmemset(hw_stats, 0, sizeof(*hw_stats));\n+\n+\treturn 0;\n+}\n+\n static int\n txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n {\n@@ -1726,6 +1995,8 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.dev_close = txgbe_dev_close,\n \t.dev_reset = txgbe_dev_reset,\n \t.link_update = txgbe_dev_link_update,\n+\t.stats_get = txgbe_dev_stats_get,\n+\t.stats_reset = txgbe_dev_stats_reset,\n \t.dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,\n \t.rx_queue_start\t = txgbe_dev_rx_queue_start,\n \t.rx_queue_stop = txgbe_dev_rx_queue_stop,\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex ab1ffe9fc..f82b400f6 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -50,6 +50,15 @@ struct txgbe_interrupt {\n \tuint32_t mask[2];\n };\n \n+#define TXGBE_NB_STAT_MAPPING 32\n+#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8\n+#define NB_QMAP_FIELDS_PER_QSM_REG 4\n+#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f\n+struct txgbe_stat_mappings {\n+\tuint32_t tqsm[TXGBE_NB_STAT_MAPPING];\n+\tuint32_t rqsm[TXGBE_NB_STAT_MAPPING];\n+};\n+\n struct txgbe_uta_info {\n \tuint8_t uc_filter_type;\n \tuint16_t uta_in_use;\n@@ -61,7 +70,9 @@ struct txgbe_uta_info {\n */\n struct txgbe_adapter {\n \tstruct txgbe_hw hw;\n+\tstruct txgbe_hw_stats stats;\n \tstruct txgbe_interrupt intr;\n+\tstruct txgbe_stat_mappings stat_mappings;\n \tstruct txgbe_uta_info uta_info;\n \tbool rx_bulk_alloc_allowed;\n };\n@@ -72,9 +83,15 @@ struct txgbe_adapter {\n #define TXGBE_DEV_HW(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)\n \n+#define TXGBE_DEV_STATS(dev) \\\n+\t(&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)\n+\n #define TXGBE_DEV_INTR(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)\n \n+#define TXGBE_DEV_STAT_MAPPINGS(dev) \\\n+\t(&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)\n+\n #define TXGBE_DEV_UTA_INFO(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)\n \n@@ -172,5 +189,7 @@ int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_ether_addr *mc_addr_set,\n \t\t\t\t uint32_t nb_mc_addr);\n void txgbe_dev_setup_link_alarm_handler(void *param);\n+void txgbe_read_stats_registers(struct txgbe_hw *hw,\n+\t\t\t struct txgbe_hw_stats *hw_stats);\n \n #endif /* _TXGBE_ETHDEV_H_ */\n", "prefixes": [ "v4", "33/58" ] }