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GET /api/patches/81311/?format=api
{ "id": 81311, "url": "http://patches.dpdk.org/api/patches/81311/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-21-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-21-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-21-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:37", "name": "[v4,20/58] net/txgbe: add Rx and Tx init", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0dfa3a2de045aaf008e9ddb504207ed5b2334f58", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-21-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81311/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81311/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A67EEA04DC;\n\tMon, 19 Oct 2020 11:04:02 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D9481CAE2;\n\tMon, 19 Oct 2020 10:53:36 +0200 (CEST)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by dpdk.org (Postfix) with ESMTP id AC4F8C8C8\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:53:05 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:52:52 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097573t515pb9pd", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "5p2KJntE3DGJ94mMgNwc4XuphQcTFnQCS1E3MNjnWE1pIr9DVmPziMhmMkHap\n PtK+rVtDheflUrYvIQmFnoSS64M0rt03U82ZpQnAqyjxkO5C2VKx1N5UAM33wYXlejgygWP\n Zlk8NKHOcZkfeNw2mMhNy7ytjUmQiEmR/GCap7tx7iHLJ3uDEHKQGBsxypmciLkwXmjOB1Y\n muHfqC2whFwUuZc0Are64ZENnHIOCDVAKSKW5uf32tNA4prBBm9qlhnEUeKY2sLhGkSXiyb\n MNGn2jgA0LBU+3LxGdzJ4YriXSkRfLdkj6SWXSaTM4qvGKDfIFt7HyMOpPsnSMb+1EY1RWs\n nzsUZudWHINN0JJFjpIbmaTZ4TEmw==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:37 +0800", "Message-Id": "<20201019085415.82207-21-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 20/58] net/txgbe: add Rx and Tx init", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add receive and transmit initialize unit.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 4 +\n doc/guides/nics/txgbe.rst | 1 +\n drivers/net/txgbe/base/txgbe_type.h | 2 +\n drivers/net/txgbe/txgbe_ethdev.h | 8 +\n drivers/net/txgbe/txgbe_rxtx.c | 338 ++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_rxtx.h | 32 +++\n 6 files changed, 385 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 115a8699b..707f64131 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -7,8 +7,12 @@\n Speed capabilities = Y\n Link status = Y\n Link status event = Y\n+Jumbo frame = Y\n+Scattered Rx = Y\n Unicast MAC filter = Y\n Multicast MAC filter = Y\n+CRC offload = P\n+VLAN offload = P\n Linux UIO = Y\n Linux VFIO = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst\nindex 0ec4148e2..9ae359c9b 100644\n--- a/doc/guides/nics/txgbe.rst\n+++ b/doc/guides/nics/txgbe.rst\n@@ -12,6 +12,7 @@ Features\n \n - Multiple queues for TX and RX\n - MAC filtering\n+- Jumbo frames\n - Link state information\n \n Prerequisites\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 8a8ca963f..747ada0f9 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -8,6 +8,8 @@\n #define TXGBE_LINK_UP_TIME\t90 /* 9.0 Seconds */\n #define TXGBE_AUTO_NEG_TIME\t45 /* 4.5 Seconds */\n \n+#define TXGBE_FRAME_SIZE_MAX\t(9728) /* Maximum frame size, +FCS */\n+#define TXGBE_FRAME_SIZE_DFT\t(1518) /* Default frame size, +FCS */\n #define TXGBE_MAX_UTA\t\t128\n \n #define TXGBE_ALIGN\t\t128 /* as intel did */\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex 8fd7a068e..096b17673 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -18,6 +18,7 @@\n * Defines that were not part of txgbe_type.h as they are not used by the\n * FreeBSD driver.\n */\n+#define TXGBE_VLAN_TAG_SIZE 4\n #define TXGBE_HKEY_MAX_INDEX 10\n /*Default value of Max Rx Queue*/\n #define TXGBE_MAX_RX_QUEUE_NUM\t128\n@@ -76,6 +77,13 @@ struct txgbe_adapter {\n #define TXGBE_DEV_UTA_INFO(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)\n \n+/*\n+ * RX/TX function prototypes\n+ */\n+int txgbe_dev_rx_init(struct rte_eth_dev *dev);\n+\n+void txgbe_dev_tx_init(struct rte_eth_dev *dev);\n+\n void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,\n \t\t\t uint8_t queue, uint8_t msix_vector);\n \ndiff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c\nindex 8a7282328..eadc06bcf 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.c\n+++ b/drivers/net/txgbe/txgbe_rxtx.c\n@@ -10,6 +10,8 @@\n \n #include <rte_common.h>\n #include <rte_ethdev.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_mbuf.h>\n \n #include \"txgbe_logs.h\"\n #include \"base/txgbe.h\"\n@@ -110,3 +112,339 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev)\n \treturn tx_offload_capa;\n }\n \n+void __rte_cold\n+txgbe_set_rx_function(struct rte_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+/**\n+ * txgbe_get_rscctl_maxdesc\n+ *\n+ * @pool Memory pool of the Rx queue\n+ */\n+static inline uint32_t\n+txgbe_get_rscctl_maxdesc(struct rte_mempool *pool)\n+{\n+\tstruct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);\n+\n+\tuint16_t maxdesc =\n+\t\tRTE_IPV4_MAX_PKT_LEN /\n+\t\t\t(mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);\n+\n+\tif (maxdesc >= 16)\n+\t\treturn TXGBE_RXCFG_RSCMAX_16;\n+\telse if (maxdesc >= 8)\n+\t\treturn TXGBE_RXCFG_RSCMAX_8;\n+\telse if (maxdesc >= 4)\n+\t\treturn TXGBE_RXCFG_RSCMAX_4;\n+\telse\n+\t\treturn TXGBE_RXCFG_RSCMAX_1;\n+}\n+\n+/**\n+ * txgbe_set_rsc - configure RSC related port HW registers\n+ *\n+ * Configures the port's RSC related registers.\n+ *\n+ * @dev port handle\n+ *\n+ * Returns 0 in case of success or a non-zero error code\n+ */\n+static int\n+txgbe_set_rsc(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct rte_eth_dev_info dev_info = { 0 };\n+\tbool rsc_capable = false;\n+\tuint16_t i;\n+\tuint32_t rdrxctl;\n+\tuint32_t rfctl;\n+\n+\t/* Sanity check */\n+\tdev->dev_ops->dev_infos_get(dev, &dev_info);\n+\tif (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)\n+\t\trsc_capable = true;\n+\n+\tif (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {\n+\t\tPMD_INIT_LOG(CRIT, \"LRO is requested on HW that doesn't \"\n+\t\t\t\t \"support it\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* RSC global configuration */\n+\n+\tif ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&\n+\t (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {\n+\t\tPMD_INIT_LOG(CRIT, \"LRO can't be enabled when HW CRC \"\n+\t\t\t\t \"is disabled\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trfctl = rd32(hw, TXGBE_PSRCTL);\n+\tif (rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))\n+\t\trfctl &= ~TXGBE_PSRCTL_RSCDIA;\n+\telse\n+\t\trfctl |= TXGBE_PSRCTL_RSCDIA;\n+\twr32(hw, TXGBE_PSRCTL, rfctl);\n+\n+\t/* If LRO hasn't been requested - we are done here. */\n+\tif (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))\n+\t\treturn 0;\n+\n+\t/* Set PSRCTL.RSCACK bit */\n+\trdrxctl = rd32(hw, TXGBE_PSRCTL);\n+\trdrxctl |= TXGBE_PSRCTL_RSCACK;\n+\twr32(hw, TXGBE_PSRCTL, rdrxctl);\n+\n+\t/* Per-queue RSC configuration */\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tstruct txgbe_rx_queue *rxq = dev->data->rx_queues[i];\n+\t\tuint32_t srrctl =\n+\t\t\trd32(hw, TXGBE_RXCFG(rxq->reg_idx));\n+\t\tuint32_t psrtype =\n+\t\t\trd32(hw, TXGBE_POOLRSS(rxq->reg_idx));\n+\t\tuint32_t eitr =\n+\t\t\trd32(hw, TXGBE_ITR(rxq->reg_idx));\n+\n+\t\t/*\n+\t\t * txgbe PMD doesn't support header-split at the moment.\n+\t\t */\n+\t\tsrrctl &= ~TXGBE_RXCFG_HDRLEN_MASK;\n+\t\tsrrctl |= TXGBE_RXCFG_HDRLEN(128);\n+\n+\t\t/*\n+\t\t * TODO: Consider setting the Receive Descriptor Minimum\n+\t\t * Threshold Size for an RSC case. This is not an obviously\n+\t\t * beneficiary option but the one worth considering...\n+\t\t */\n+\n+\t\tsrrctl |= TXGBE_RXCFG_RSCENA;\n+\t\tsrrctl &= ~TXGBE_RXCFG_RSCMAX_MASK;\n+\t\tsrrctl |= txgbe_get_rscctl_maxdesc(rxq->mb_pool);\n+\t\tpsrtype |= TXGBE_POOLRSS_L4HDR;\n+\n+\t\t/*\n+\t\t * RSC: Set ITR interval corresponding to 2K ints/s.\n+\t\t *\n+\t\t * Full-sized RSC aggregations for a 10Gb/s link will\n+\t\t * arrive at about 20K aggregation/s rate.\n+\t\t *\n+\t\t * 2K inst/s rate will make only 10% of the\n+\t\t * aggregations to be closed due to the interrupt timer\n+\t\t * expiration for a streaming at wire-speed case.\n+\t\t *\n+\t\t * For a sparse streaming case this setting will yield\n+\t\t * at most 500us latency for a single RSC aggregation.\n+\t\t */\n+\t\teitr &= ~TXGBE_ITR_IVAL_MASK;\n+\t\teitr |= TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT);\n+\t\teitr |= TXGBE_ITR_WRDSA;\n+\n+\t\twr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl);\n+\t\twr32(hw, TXGBE_POOLRSS(rxq->reg_idx), psrtype);\n+\t\twr32(hw, TXGBE_ITR(rxq->reg_idx), eitr);\n+\n+\t\t/*\n+\t\t * RSC requires the mapping of the queue to the\n+\t\t * interrupt vector.\n+\t\t */\n+\t\ttxgbe_set_ivar_map(hw, 0, rxq->reg_idx, i);\n+\t}\n+\n+\tdev->data->lro = 1;\n+\n+\tPMD_INIT_LOG(DEBUG, \"enabling LRO mode\");\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Initializes Receive Unit.\n+ */\n+int __rte_cold\n+txgbe_dev_rx_init(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw;\n+\tstruct txgbe_rx_queue *rxq;\n+\tuint64_t bus_addr;\n+\tuint32_t fctrl;\n+\tuint32_t hlreg0;\n+\tuint32_t srrctl;\n+\tuint32_t rdrxctl;\n+\tuint32_t rxcsum;\n+\tuint16_t buf_size;\n+\tuint16_t i;\n+\tstruct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;\n+\tint rc;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = TXGBE_DEV_HW(dev);\n+\n+\t/*\n+\t * Make sure receives are disabled while setting\n+\t * up the RX context (registers, descriptor rings, etc.).\n+\t */\n+\twr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);\n+\twr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);\n+\n+\t/* Enable receipt of broadcasted frames */\n+\tfctrl = rd32(hw, TXGBE_PSRCTL);\n+\tfctrl |= TXGBE_PSRCTL_BCA;\n+\twr32(hw, TXGBE_PSRCTL, fctrl);\n+\n+\t/*\n+\t * Configure CRC stripping, if any.\n+\t */\n+\thlreg0 = rd32(hw, TXGBE_SECRXCTL);\n+\tif (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)\n+\t\thlreg0 &= ~TXGBE_SECRXCTL_CRCSTRIP;\n+\telse\n+\t\thlreg0 |= TXGBE_SECRXCTL_CRCSTRIP;\n+\twr32(hw, TXGBE_SECRXCTL, hlreg0);\n+\n+\t/*\n+\t * Configure jumbo frame support, if any.\n+\t */\n+\tif (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {\n+\t\twr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,\n+\t\t\tTXGBE_FRMSZ_MAX(rx_conf->max_rx_pkt_len));\n+\t} else {\n+\t\twr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,\n+\t\t\tTXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));\n+\t}\n+\n+\t/*\n+\t * If loopback mode is configured, set LPBK bit.\n+\t */\n+\thlreg0 = rd32(hw, TXGBE_PSRCTL);\n+\tif (hw->mac.type == txgbe_mac_raptor &&\n+\t dev->data->dev_conf.lpbk_mode)\n+\t\thlreg0 |= TXGBE_PSRCTL_LBENA;\n+\telse\n+\t\thlreg0 &= ~TXGBE_PSRCTL_LBENA;\n+\n+\twr32(hw, TXGBE_PSRCTL, hlreg0);\n+\n+\t/*\n+\t * Assume no header split and no VLAN strip support\n+\t * on any Rx queue first .\n+\t */\n+\trx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;\n+\n+\t/* Setup RX queues */\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\trxq = dev->data->rx_queues[i];\n+\n+\t\t/*\n+\t\t * Reset crc_len in case it was changed after queue setup by a\n+\t\t * call to configure.\n+\t\t */\n+\t\tif (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)\n+\t\t\trxq->crc_len = RTE_ETHER_CRC_LEN;\n+\t\telse\n+\t\t\trxq->crc_len = 0;\n+\n+\t\t/* Setup the Base and Length of the Rx Descriptor Rings */\n+\t\tbus_addr = rxq->rx_ring_phys_addr;\n+\t\twr32(hw, TXGBE_RXBAL(rxq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr & BIT_MASK32));\n+\t\twr32(hw, TXGBE_RXBAH(rxq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr >> 32));\n+\t\twr32(hw, TXGBE_RXRP(rxq->reg_idx), 0);\n+\t\twr32(hw, TXGBE_RXWP(rxq->reg_idx), 0);\n+\n+\t\tsrrctl = TXGBE_RXCFG_RNGLEN(rxq->nb_rx_desc);\n+\n+\t\t/* Set if packets are dropped when no descriptors available */\n+\t\tif (rxq->drop_en)\n+\t\t\tsrrctl |= TXGBE_RXCFG_DROP;\n+\n+\t\t/*\n+\t\t * Configure the RX buffer size in the PKTLEN field of\n+\t\t * the RXCFG register of the queue.\n+\t\t * The value is in 1 KB resolution. Valid values can be from\n+\t\t * 1 KB to 16 KB.\n+\t\t */\n+\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n+\t\t\tRTE_PKTMBUF_HEADROOM);\n+\t\tbuf_size = ROUND_UP(buf_size, 0x1 << 10);\n+\t\tsrrctl |= TXGBE_RXCFG_PKTLEN(buf_size);\n+\n+\t\twr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl);\n+\n+\t\t/* It adds dual VLAN length for supporting dual VLAN */\n+\t\tif (dev->data->dev_conf.rxmode.max_rx_pkt_len +\n+\t\t\t\t\t 2 * TXGBE_VLAN_TAG_SIZE > buf_size)\n+\t\t\tdev->data->scattered_rx = 1;\n+\t\tif (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)\n+\t\t\trx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;\n+\t}\n+\n+\tif (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)\n+\t\tdev->data->scattered_rx = 1;\n+\n+\t/*\n+\t * Setup the Checksum Register.\n+\t * Disable Full-Packet Checksum which is mutually exclusive with RSS.\n+\t * Enable IP/L4 checksum computation by hardware if requested to do so.\n+\t */\n+\trxcsum = rd32(hw, TXGBE_PSRCTL);\n+\trxcsum |= TXGBE_PSRCTL_PCSD;\n+\tif (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)\n+\t\trxcsum |= TXGBE_PSRCTL_L4CSUM;\n+\telse\n+\t\trxcsum &= ~TXGBE_PSRCTL_L4CSUM;\n+\n+\twr32(hw, TXGBE_PSRCTL, rxcsum);\n+\n+\tif (hw->mac.type == txgbe_mac_raptor) {\n+\t\trdrxctl = rd32(hw, TXGBE_SECRXCTL);\n+\t\tif (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)\n+\t\t\trdrxctl &= ~TXGBE_SECRXCTL_CRCSTRIP;\n+\t\telse\n+\t\t\trdrxctl |= TXGBE_SECRXCTL_CRCSTRIP;\n+\t\twr32(hw, TXGBE_SECRXCTL, rdrxctl);\n+\t}\n+\n+\trc = txgbe_set_rsc(dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\ttxgbe_set_rx_function(dev);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Initializes Transmit Unit.\n+ */\n+void __rte_cold\n+txgbe_dev_tx_init(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw;\n+\tstruct txgbe_tx_queue *txq;\n+\tuint64_t bus_addr;\n+\tuint16_t i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = TXGBE_DEV_HW(dev);\n+\n+\t/* Setup the Base and Length of the Tx Descriptor Rings */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\n+\t\tbus_addr = txq->tx_ring_phys_addr;\n+\t\twr32(hw, TXGBE_TXBAL(txq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr & BIT_MASK32));\n+\t\twr32(hw, TXGBE_TXBAH(txq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr >> 32));\n+\t\twr32m(hw, TXGBE_TXCFG(txq->reg_idx), TXGBE_TXCFG_BUFLEN_MASK,\n+\t\t\tTXGBE_TXCFG_BUFLEN(txq->nb_tx_desc));\n+\t\t/* Setup the HW Tx Head and TX Tail descriptor pointers */\n+\t\twr32(hw, TXGBE_TXRP(txq->reg_idx), 0);\n+\t\twr32(hw, TXGBE_TXWP(txq->reg_idx), 0);\n+\t}\n+}\n+\ndiff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h\nindex 9488c2b75..7d3d9c275 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.h\n+++ b/drivers/net/txgbe/txgbe_rxtx.h\n@@ -5,8 +5,40 @@\n #ifndef _TXGBE_RXTX_H_\n #define _TXGBE_RXTX_H_\n \n+#define RTE_PMD_TXGBE_TX_MAX_BURST 32\n+#define RTE_PMD_TXGBE_RX_MAX_BURST 32\n+\n #define TXGBE_TX_MAX_SEG 40\n \n+/**\n+ * Structure associated with each RX queue.\n+ */\n+struct txgbe_rx_queue {\n+\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n+\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n+\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n+\tuint16_t reg_idx; /**< RX queue register index. */\n+\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n+\tuint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */\n+\tuint64_t\t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */\n+};\n+\n+/**\n+ * Structure associated with each TX queue.\n+ */\n+struct txgbe_tx_queue {\n+\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n+\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n+\t/**< Start freeing TX buffers if there are less free descriptors than\n+\t * this value.\n+\t */\n+\tuint16_t tx_free_thresh;\n+\tuint16_t reg_idx; /**< TX queue register index. */\n+\tuint64_t offloads; /**< Tx offload flags of DEV_TX_OFFLOAD_* */\n+};\n+\n+void txgbe_set_rx_function(struct rte_eth_dev *dev);\n+\n uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev);\n uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);\n uint64_t txgbe_get_rx_port_offloads(struct rte_eth_dev *dev);\n", "prefixes": [ "v4", "20/58" ] }