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GET /api/patches/81297/?format=api
{ "id": 81297, "url": "http://patches.dpdk.org/api/patches/81297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-8-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-8-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-8-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:24", "name": "[v4,07/58] net/txgbe: add EEPROM functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8234c23faba37989d186f37b6e6422f65afea522", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-8-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81297/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4CC9CA04DC;\n\tMon, 19 Oct 2020 10:57:32 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 89DE5C8FA;\n\tMon, 19 Oct 2020 10:53:09 +0200 (CEST)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by dpdk.org (Postfix) with ESMTP id 7ACDEC832\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:52:49 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:52:36 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097556trfp25w4c", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "uPKj8ga2w7Fq62UIl+JfaZYsvdEFdUBY7OMS6jezyXaQ/uL33nTV6VcCLHiCG\n 9nCDcpkdbYT/ZUX+sfANGcG3V23heQDeulWc26kFyxu84sWHx3FwN+ZdbKYdg5Hk9JWDX35\n XaD9bLCsc4reV2JUCebhSUE+BsEOMIpSEtCPsJIzbeo7tK2KKOyQEphw1ApnDSy6Ek8gBNl\n t1iHkuv/fDgpXM+e6CemaY8aSu5QhYnBOOUnCtcb4cjbMwnyUo4EY2/KFEdVVpcfjTUpYRG\n N4Zeh66fueRWmGZm1mMJf4azBade+E0YnlRiETkGv5UAMjGKtFDAiNOy/5ZLtGZtPHRieQg\n kn/xJLJRm3aqnzbs0YLWX4L0njwzw==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:24 +0800", "Message-Id": "<20201019085415.82207-8-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 07/58] net/txgbe: add EEPROM functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add EEPROM functions.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/meson.build | 2 +\n drivers/net/txgbe/base/txgbe.h | 2 +\n drivers/net/txgbe/base/txgbe_eeprom.c | 581 ++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_eeprom.h | 49 +++\n drivers/net/txgbe/base/txgbe_hw.c | 17 +\n drivers/net/txgbe/base/txgbe_mng.c | 396 ++++++++++++++++++\n drivers/net/txgbe/base/txgbe_mng.h | 176 ++++++++\n drivers/net/txgbe/base/txgbe_type.h | 21 +\n drivers/net/txgbe/txgbe_ethdev.c | 14 +\n 9 files changed, 1258 insertions(+)\n create mode 100644 drivers/net/txgbe/base/txgbe_eeprom.c\n create mode 100644 drivers/net/txgbe/base/txgbe_eeprom.h\n create mode 100644 drivers/net/txgbe/base/txgbe_mng.c\n create mode 100644 drivers/net/txgbe/base/txgbe_mng.h", "diff": "diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build\nindex 54d6e399d..9755bbbb4 100644\n--- a/drivers/net/txgbe/base/meson.build\n+++ b/drivers/net/txgbe/base/meson.build\n@@ -2,7 +2,9 @@\n # Copyright(c) 2015-2020\n \n sources = [\n+\t'txgbe_eeprom.c',\n \t'txgbe_hw.c',\n+\t'txgbe_mng.c',\n ]\n \n error_cflags = []\ndiff --git a/drivers/net/txgbe/base/txgbe.h b/drivers/net/txgbe/base/txgbe.h\nindex 7783bd694..329764be0 100644\n--- a/drivers/net/txgbe/base/txgbe.h\n+++ b/drivers/net/txgbe/base/txgbe.h\n@@ -6,6 +6,8 @@\n #define _TXGBE_H_\n \n #include \"txgbe_type.h\"\n+#include \"txgbe_mng.h\"\n+#include \"txgbe_eeprom.h\"\n #include \"txgbe_hw.h\"\n \n #endif /* _TXGBE_H_ */\ndiff --git a/drivers/net/txgbe/base/txgbe_eeprom.c b/drivers/net/txgbe/base/txgbe_eeprom.c\nnew file mode 100644\nindex 000000000..72cd3ff30\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_eeprom.c\n@@ -0,0 +1,581 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#include \"txgbe_hw.h\"\n+#include \"txgbe_mng.h\"\n+#include \"txgbe_eeprom.h\"\n+\n+/**\n+ * txgbe_init_eeprom_params - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initializes the EEPROM parameters txgbe_rom_info within the\n+ * txgbe_hw struct in order to set up EEPROM access.\n+ **/\n+s32 txgbe_init_eeprom_params(struct txgbe_hw *hw)\n+{\n+\tstruct txgbe_rom_info *eeprom = &hw->rom;\n+\tu32 eec;\n+\tu16 eeprom_size;\n+\tint err = 0;\n+\n+\tDEBUGFUNC(\"txgbe_init_eeprom_params\");\n+\n+\tif (eeprom->type != txgbe_eeprom_unknown)\n+\t\treturn 0;\n+\n+\teeprom->type = txgbe_eeprom_none;\n+\t/* Set default semaphore delay to 10ms which is a well\n+\t * tested value\n+\t */\n+\teeprom->semaphore_delay = 10; /*ms*/\n+\t/* Clear EEPROM page size, it will be initialized as needed */\n+\teeprom->word_page_size = 0;\n+\n+\t/*\n+\t * Check for EEPROM present first.\n+\t * If not present leave as none\n+\t */\n+\teec = rd32(hw, TXGBE_SPISTAT);\n+\tif (!(eec & TXGBE_SPISTAT_BPFLASH)) {\n+\t\teeprom->type = txgbe_eeprom_flash;\n+\n+\t\t/*\n+\t\t * SPI EEPROM is assumed here. This code would need to\n+\t\t * change if a future EEPROM is not SPI.\n+\t\t */\n+\t\teeprom_size = 4096;\n+\t\teeprom->word_size = eeprom_size >> 1;\n+\t}\n+\n+\teeprom->address_bits = 16;\n+\n+\terr = eeprom->read32(hw, TXGBE_SW_REGION_PTR << 1, &eeprom->sw_addr);\n+\tif (err) {\n+\t\tDEBUGOUT(\"EEPROM read failed.\\n\");\n+\t\treturn err;\n+\t}\n+\n+\tDEBUGOUT(\"eeprom params: type = %d, size = %d, address bits: \"\n+\t\t \"%d %d\\n\", eeprom->type, eeprom->word_size,\n+\t\t eeprom->address_bits, eeprom->sw_addr);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_get_eeprom_semaphore - Get hardware semaphore\n+ * @hw: pointer to hardware structure\n+ *\n+ * Sets the hardware semaphores so EEPROM access can occur for bit-bang method\n+ **/\n+s32 txgbe_get_eeprom_semaphore(struct txgbe_hw *hw)\n+{\n+\ts32 status = TXGBE_ERR_EEPROM;\n+\tu32 timeout = 2000;\n+\tu32 i;\n+\tu32 swsm;\n+\n+\tDEBUGFUNC(\"txgbe_get_eeprom_semaphore\");\n+\n+\n+\t/* Get SMBI software semaphore between device drivers first */\n+\tfor (i = 0; i < timeout; i++) {\n+\t\t/*\n+\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n+\t\t * set and we have the semaphore\n+\t\t */\n+\t\tswsm = rd32(hw, TXGBE_SWSEM);\n+\t\tif (!(swsm & TXGBE_SWSEM_PF)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusec_delay(50);\n+\t}\n+\n+\tif (i == timeout) {\n+\t\tDEBUGOUT(\"Driver can't access the eeprom - SMBI Semaphore \"\n+\t\t\t \"not granted.\\n\");\n+\t\t/*\n+\t\t * this release is particularly important because our attempts\n+\t\t * above to get the semaphore may have succeeded, and if there\n+\t\t * was a timeout, we should unconditionally clear the semaphore\n+\t\t * bits to free the driver to make progress\n+\t\t */\n+\t\ttxgbe_release_eeprom_semaphore(hw);\n+\n+\t\tusec_delay(50);\n+\t\t/*\n+\t\t * one last try\n+\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n+\t\t * set and we have the semaphore\n+\t\t */\n+\t\tswsm = rd32(hw, TXGBE_SWSEM);\n+\t\tif (!(swsm & TXGBE_SWSEM_PF))\n+\t\t\tstatus = 0;\n+\t}\n+\n+\t/* Now get the semaphore between SW/FW through the SWESMBI bit */\n+\tif (status == 0) {\n+\t\tfor (i = 0; i < timeout; i++) {\n+\t\t\t/* Set the SW EEPROM semaphore bit to request access */\n+\t\t\twr32m(hw, TXGBE_MNGSWSYNC,\n+\t\t\t\tTXGBE_MNGSWSYNC_REQ, TXGBE_MNGSWSYNC_REQ);\n+\n+\t\t\t/*\n+\t\t\t * If we set the bit successfully then we got the\n+\t\t\t * semaphore.\n+\t\t\t */\n+\t\t\tswsm = rd32(hw, TXGBE_MNGSWSYNC);\n+\t\t\tif (swsm & TXGBE_MNGSWSYNC_REQ)\n+\t\t\t\tbreak;\n+\n+\t\t\tusec_delay(50);\n+\t\t}\n+\n+\t\t/*\n+\t\t * Release semaphores and return error if SW EEPROM semaphore\n+\t\t * was not granted because we don't have access to the EEPROM\n+\t\t */\n+\t\tif (i >= timeout) {\n+\t\t\tDEBUGOUT(\"SWESMBI Software EEPROM semaphore not granted.\\n\");\n+\t\t\ttxgbe_release_eeprom_semaphore(hw);\n+\t\t\tstatus = TXGBE_ERR_EEPROM;\n+\t\t}\n+\t} else {\n+\t\tDEBUGOUT(\"Software semaphore SMBI between device drivers \"\n+\t\t\t \"not granted.\\n\");\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * txgbe_release_eeprom_semaphore - Release hardware semaphore\n+ * @hw: pointer to hardware structure\n+ *\n+ * This function clears hardware semaphore bits.\n+ **/\n+void txgbe_release_eeprom_semaphore(struct txgbe_hw *hw)\n+{\n+\tDEBUGFUNC(\"txgbe_release_eeprom_semaphore\");\n+\n+\twr32m(hw, TXGBE_MNGSWSYNC, TXGBE_MNGSWSYNC_REQ, 0);\n+\twr32m(hw, TXGBE_SWSEM, TXGBE_SWSEM_PF, 0);\n+\ttxgbe_flush(hw);\n+}\n+\n+/**\n+ * txgbe_ee_read - Read EEPROM word using a host interface cmd\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 16 bit word from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_read16(struct txgbe_hw *hw, u32 offset,\n+\t\t\t u16 *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = (offset << 1);\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_read(hw, addr, (u8 *)data, 2);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_read_buffer- Read EEPROM word(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n+ *\n+ * Reads a 16 bit word(s) from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_readw_buffer(struct txgbe_hw *hw,\n+\t\t\t\t u32 offset, u32 words, void *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = (offset << 1);\n+\tu32 len = (words << 1);\n+\tu8 *buf = (u8 *)data;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (len) {\n+\t\tu32 seg = (len <= TXGBE_PMMBX_DATA_SIZE\n+\t\t\t\t? len : TXGBE_PMMBX_DATA_SIZE);\n+\n+\t\terr = txgbe_hic_sr_read(hw, addr, buf, seg);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tlen -= seg;\n+\t\taddr += seg;\n+\t\tbuf += seg;\n+\t}\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\treturn err;\n+}\n+\n+\n+s32 txgbe_ee_readw_sw(struct txgbe_hw *hw, u32 offset,\n+\t\t\t u16 *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = hw->rom.sw_addr + (offset << 1);\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_read(hw, addr, (u8 *)data, 2);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_read32 - Read EEPROM word using a host interface cmd\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 32 bit word from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_read32(struct txgbe_hw *hw, u32 addr, u32 *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_read(hw, addr, (u8 *)data, 4);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_read_buffer - Read EEPROM byte(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @addr: offset of bytes in the EEPROM to read\n+ * @len: number of bytes\n+ * @data: byte(s) read from the EEPROM\n+ *\n+ * Reads a 8 bit byte(s) from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_read_buffer(struct txgbe_hw *hw,\n+\t\t\t\t u32 addr, u32 len, void *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu8 *buf = (u8 *)data;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (len) {\n+\t\tu32 seg = (len <= TXGBE_PMMBX_DATA_SIZE\n+\t\t\t\t? len : TXGBE_PMMBX_DATA_SIZE);\n+\n+\t\terr = txgbe_hic_sr_read(hw, addr, buf, seg);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tlen -= seg;\n+\t\tbuf += seg;\n+\t}\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_write - Write EEPROM word using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n+ *\n+ * Write a 16 bit word to the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_write16(struct txgbe_hw *hw, u32 offset,\n+\t\t\t u16 data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = (offset << 1);\n+\tint err;\n+\n+\tDEBUGFUNC(\"\\n\");\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_write(hw, addr, (u8 *)&data, 2);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_write_buffer - Write EEPROM word(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @words: number of words\n+ * @data: word(s) write to the EEPROM\n+ *\n+ * Write a 16 bit word(s) to the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_writew_buffer(struct txgbe_hw *hw,\n+\t\t\t\t u32 offset, u32 words, void *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = (offset << 1);\n+\tu32 len = (words << 1);\n+\tu8 *buf = (u8 *)data;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (len) {\n+\t\tu32 seg = (len <= TXGBE_PMMBX_DATA_SIZE\n+\t\t\t\t? len : TXGBE_PMMBX_DATA_SIZE);\n+\n+\t\terr = txgbe_hic_sr_write(hw, addr, buf, seg);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tlen -= seg;\n+\t\tbuf += seg;\n+\t}\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\treturn err;\n+}\n+\n+s32 txgbe_ee_writew_sw(struct txgbe_hw *hw, u32 offset,\n+\t\t\t u16 data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu32 addr = hw->rom.sw_addr + (offset << 1);\n+\tint err;\n+\n+\tDEBUGFUNC(\"\\n\");\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_write(hw, addr, (u8 *)&data, 2);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_write32 - Read EEPROM word using a host interface cmd\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 32 bit word from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_write32(struct txgbe_hw *hw, u32 addr, u32 data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_sr_write(hw, addr, (u8 *)&data, 4);\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_ee_write_buffer - Write EEPROM byte(s) using hostif\n+ * @hw: pointer to hardware structure\n+ * @addr: offset of bytes in the EEPROM to write\n+ * @len: number of bytes\n+ * @data: word(s) write to the EEPROM\n+ *\n+ * Write a 8 bit byte(s) to the EEPROM using the hostif.\n+ **/\n+s32 txgbe_ee_write_buffer(struct txgbe_hw *hw,\n+\t\t\t\t u32 addr, u32 len, void *data)\n+{\n+\tconst u32 mask = TXGBE_MNGSEM_SWMBX | TXGBE_MNGSEM_SWFLASH;\n+\tu8 *buf = (u8 *)data;\n+\tint err;\n+\n+\terr = hw->mac.acquire_swfw_sync(hw, mask);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (len) {\n+\t\tu32 seg = (len <= TXGBE_PMMBX_DATA_SIZE\n+\t\t\t\t? len : TXGBE_PMMBX_DATA_SIZE);\n+\n+\t\terr = txgbe_hic_sr_write(hw, addr, buf, seg);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tlen -= seg;\n+\t\tbuf += seg;\n+\t}\n+\n+\thw->mac.release_swfw_sync(hw, mask);\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_calc_eeprom_checksum - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns a negative error code on error, or the 16-bit checksum\n+ **/\n+#define BUFF_SIZE 64\n+s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw)\n+{\n+\tu16 checksum = 0, read_checksum = 0;\n+\tint i, j, seg;\n+\tint err;\n+\tu16 buffer[BUFF_SIZE];\n+\n+\tDEBUGFUNC(\"txgbe_calc_eeprom_checksum\");\n+\n+\terr = hw->rom.readw_sw(hw, TXGBE_EEPROM_CHECKSUM, &read_checksum);\n+\tif (err) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn err;\n+\t}\n+\n+\tfor (i = 0; i < TXGBE_EE_CSUM_MAX; i += seg) {\n+\t\tseg = (i + BUFF_SIZE < TXGBE_EE_CSUM_MAX\n+\t\t ? BUFF_SIZE : TXGBE_EE_CSUM_MAX - i);\n+\t\terr = hw->rom.readw_buffer(hw, i, seg, buffer);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t\tfor (j = 0; j < seg; j++)\n+\t\t\tchecksum += buffer[j];\n+\t}\n+\n+\tchecksum = (u16)TXGBE_EEPROM_SUM - checksum + read_checksum;\n+\n+\treturn (s32)checksum;\n+}\n+\n+/**\n+ * txgbe_validate_eeprom_checksum - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n+ *\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n+ **/\n+s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw,\n+\t\t\t\t\t u16 *checksum_val)\n+{\n+\tu16 checksum;\n+\tu16 read_checksum = 0;\n+\tint err;\n+\n+\tDEBUGFUNC(\"txgbe_validate_eeprom_checksum\");\n+\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n+\t * not continue or we could be in for a very long wait while every\n+\t * EEPROM read fails\n+\t */\n+\terr = hw->rom.read16(hw, 0, &checksum);\n+\tif (err) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn err;\n+\t}\n+\n+\terr = hw->rom.calc_checksum(hw);\n+\tif (err < 0)\n+\t\treturn err;\n+\n+\tchecksum = (u16)(err & 0xffff);\n+\n+\terr = hw->rom.readw_sw(hw, TXGBE_EEPROM_CHECKSUM, &read_checksum);\n+\tif (err) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn err;\n+\t}\n+\n+\t/* Verify read checksum from EEPROM is the same as\n+\t * calculated checksum\n+\t */\n+\tif (read_checksum != checksum) {\n+\t\terr = TXGBE_ERR_EEPROM_CHECKSUM;\n+\t\tDEBUGOUT(\"EEPROM checksum error\\n\");\n+\t}\n+\n+\t/* If the user cares, return the calculated checksum */\n+\tif (checksum_val)\n+\t\t*checksum_val = checksum;\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_update_eeprom_checksum - Updates the EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ **/\n+s32 txgbe_update_eeprom_checksum(struct txgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu16 checksum;\n+\n+\tDEBUGFUNC(\"txgbe_update_eeprom_checksum\");\n+\n+\t/* Read the first word from the EEPROM. If this times out or fails, do\n+\t * not continue or we could be in for a very long wait while every\n+\t * EEPROM read fails\n+\t */\n+\tstatus = hw->rom.read16(hw, 0, &checksum);\n+\tif (status) {\n+\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = hw->rom.calc_checksum(hw);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\tchecksum = (u16)(status & 0xffff);\n+\n+\tstatus = hw->rom.writew_sw(hw, TXGBE_EEPROM_CHECKSUM, checksum);\n+\n+\treturn status;\n+}\n+\ndiff --git a/drivers/net/txgbe/base/txgbe_eeprom.h b/drivers/net/txgbe/base/txgbe_eeprom.h\nnew file mode 100644\nindex 000000000..137fb1c30\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_eeprom.h\n@@ -0,0 +1,49 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#ifndef _TXGBE_EEPROM_H_\n+#define _TXGBE_EEPROM_H_\n+\n+/* Checksum and EEPROM pointers */\n+#define TXGBE_PBANUM_PTR_GUARD\t\t0xFAFA\n+#define TXGBE_EEPROM_SUM\t\t0xBABA\n+\n+#define TXGBE_FW_PTR\t\t\t0x0F\n+#define TXGBE_PBANUM0_PTR\t\t0x05\n+#define TXGBE_PBANUM1_PTR\t\t0x06\n+#define TXGBE_SW_REGION_PTR 0x1C\n+\n+#define TXGBE_EE_CSUM_MAX\t\t0x800\n+#define TXGBE_EEPROM_CHECKSUM\t\t0x2F\n+\n+#define TXGBE_SAN_MAC_ADDR_PTR\t\t0x18\n+#define TXGBE_DEVICE_CAPS\t\t0x1C\n+#define TXGBE_EEPROM_VERSION_L 0x1D\n+#define TXGBE_EEPROM_VERSION_H 0x1E\n+#define TXGBE_ISCSI_BOOT_CONFIG 0x07\n+\n+\n+s32 txgbe_init_eeprom_params(struct txgbe_hw *hw);\n+s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);\n+s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw, u16 *checksum_val);\n+s32 txgbe_update_eeprom_checksum(struct txgbe_hw *hw);\n+s32 txgbe_get_eeprom_semaphore(struct txgbe_hw *hw);\n+void txgbe_release_eeprom_semaphore(struct txgbe_hw *hw);\n+\n+s32 txgbe_ee_read16(struct txgbe_hw *hw, u32 offset, u16 *data);\n+s32 txgbe_ee_readw_sw(struct txgbe_hw *hw, u32 offset, u16 *data);\n+s32 txgbe_ee_readw_buffer(struct txgbe_hw *hw, u32 offset, u32 words,\n+\t\t\t\tvoid *data);\n+s32 txgbe_ee_read32(struct txgbe_hw *hw, u32 addr, u32 *data);\n+s32 txgbe_ee_read_buffer(struct txgbe_hw *hw, u32 addr, u32 len, void *data);\n+\n+s32 txgbe_ee_write16(struct txgbe_hw *hw, u32 offset, u16 data);\n+s32 txgbe_ee_writew_sw(struct txgbe_hw *hw, u32 offset, u16 data);\n+s32 txgbe_ee_writew_buffer(struct txgbe_hw *hw, u32 offset, u32 words,\n+\t\t\t\tvoid *data);\n+s32 txgbe_ee_write32(struct txgbe_hw *hw, u32 addr, u32 data);\n+s32 txgbe_ee_write_buffer(struct txgbe_hw *hw, u32 addr, u32 len, void *data);\n+\n+\n+#endif /* _TXGBE_EEPROM_H_ */\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex 6478b6fbf..e942c5631 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -3,6 +3,7 @@\n */\n \n #include \"txgbe_type.h\"\n+#include \"txgbe_eeprom.h\"\n #include \"txgbe_hw.h\"\n \n #define TXGBE_RAPTOR_RAR_ENTRIES 128\n@@ -135,13 +136,29 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)\n {\n \tstruct txgbe_bus_info *bus = &hw->bus;\n \tstruct txgbe_mac_info *mac = &hw->mac;\n+\tstruct txgbe_rom_info *rom = &hw->rom;\n \n \tDEBUGFUNC(\"txgbe_init_ops_pf\");\n \n \t/* BUS */\n \tbus->set_lan_id = txgbe_set_lan_id_multi_port;\n \n+\t/* MAC */\n \tmac->num_rar_entries\t= TXGBE_RAPTOR_RAR_ENTRIES;\n \n+\t/* EEPROM */\n+\trom->init_params = txgbe_init_eeprom_params;\n+\trom->read16 = txgbe_ee_read16;\n+\trom->readw_buffer = txgbe_ee_readw_buffer;\n+\trom->readw_sw = txgbe_ee_readw_sw;\n+\trom->read32 = txgbe_ee_read32;\n+\trom->write16 = txgbe_ee_write16;\n+\trom->writew_buffer = txgbe_ee_writew_buffer;\n+\trom->writew_sw = txgbe_ee_writew_sw;\n+\trom->write32 = txgbe_ee_write32;\n+\trom->validate_checksum = txgbe_validate_eeprom_checksum;\n+\trom->update_checksum = txgbe_update_eeprom_checksum;\n+\trom->calc_checksum = txgbe_calc_eeprom_checksum;\n+\n \treturn 0;\n }\ndiff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c\nnew file mode 100644\nindex 000000000..224e48f5e\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_mng.c\n@@ -0,0 +1,396 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#include \"txgbe_type.h\"\n+#include \"txgbe_mng.h\"\n+\n+/**\n+ * txgbe_calculate_checksum - Calculate checksum for buffer\n+ * @buffer: pointer to EEPROM\n+ * @length: size of EEPROM to calculate a checksum for\n+ * Calculates the checksum for some buffer on a specified length. The\n+ * checksum calculated is returned.\n+ **/\n+static u8\n+txgbe_calculate_checksum(u8 *buffer, u32 length)\n+{\n+\tu32 i;\n+\tu8 sum = 0;\n+\n+\tfor (i = 0; i < length; i++)\n+\t\tsum += buffer[i];\n+\n+\treturn (u8)(0 - sum);\n+}\n+\n+/**\n+ * txgbe_hic_unlocked - Issue command to manageability block unlocked\n+ * @hw: pointer to the HW structure\n+ * @buffer: command to write and where the return status will be placed\n+ * @length: length of buffer, must be multiple of 4 bytes\n+ * @timeout: time in ms to wait for command completion\n+ *\n+ * Communicates with the manageability block. On success return 0\n+ * else returns semaphore error when encountering an error acquiring\n+ * semaphore or TXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ *\n+ * This function assumes that the TXGBE_MNGSEM_SWMBX semaphore is held\n+ * by the caller.\n+ **/\n+static s32\n+txgbe_hic_unlocked(struct txgbe_hw *hw, u32 *buffer, u32 length, u32 timeout)\n+{\n+\tu32 value, loop;\n+\tu16 i, dword_len;\n+\n+\tDEBUGFUNC(\"txgbe_hic_unlocked\");\n+\n+\tif (!length || length > TXGBE_PMMBX_BSIZE) {\n+\t\tDEBUGOUT(\"Buffer length failure buffersize=%d.\\n\", length);\n+\t\treturn TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Calculate length in DWORDs. We must be DWORD aligned */\n+\tif (length % sizeof(u32)) {\n+\t\tDEBUGOUT(\"Buffer length failure, not aligned to dword\");\n+\t\treturn TXGBE_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\tdword_len = length >> 2;\n+\n+\t/* The device driver writes the relevant command block\n+\t * into the ram area.\n+\t */\n+\tfor (i = 0; i < dword_len; i++) {\n+\t\twr32a(hw, TXGBE_MNGMBX, i, cpu_to_le32(buffer[i]));\n+\t\tbuffer[i] = rd32a(hw, TXGBE_MNGMBX, i);\n+\t}\n+\ttxgbe_flush(hw);\n+\n+\t/* Setting this bit tells the ARC that a new command is pending. */\n+\twr32m(hw, TXGBE_MNGMBXCTL,\n+\t TXGBE_MNGMBXCTL_SWRDY, TXGBE_MNGMBXCTL_SWRDY);\n+\n+\t/* Check command completion */\n+\tloop = po32m(hw, TXGBE_MNGMBXCTL,\n+\t\tTXGBE_MNGMBXCTL_FWRDY, TXGBE_MNGMBXCTL_FWRDY,\n+\t\t&value, timeout, 1000);\n+\tif (!loop || !(value & TXGBE_MNGMBXCTL_FWACK)) {\n+\t\tDEBUGOUT(\"Command has failed with no status valid.\\n\");\n+\t\treturn TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_host_interface_command - Issue command to manageability block\n+ * @hw: pointer to the HW structure\n+ * @buffer: contains the command to write and where the return status will\n+ * be placed\n+ * @length: length of buffer, must be multiple of 4 bytes\n+ * @timeout: time in ms to wait for command completion\n+ * @return_data: read and return data from the buffer (true) or not (false)\n+ * Needed because FW structures are big endian and decoding of\n+ * these fields can be 8 bit or 16 bit based on command. Decoding\n+ * is not easily understood without making a table of commands.\n+ * So we will leave this up to the caller to read back the data\n+ * in these cases.\n+ *\n+ * Communicates with the manageability block. On success return 0\n+ * else returns semaphore error when encountering an error acquiring\n+ * semaphore or TXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ **/\n+static s32\n+txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer,\n+\t\t\t\t u32 length, u32 timeout, bool return_data)\n+{\n+\tu32 hdr_size = sizeof(struct txgbe_hic_hdr);\n+\tstruct txgbe_hic_hdr *resp = (struct txgbe_hic_hdr *)buffer;\n+\tu16 buf_len;\n+\ts32 err;\n+\tu32 bi;\n+\tu32 dword_len;\n+\n+\tDEBUGFUNC(\"txgbe_host_interface_command\");\n+\n+\tif (length == 0 || length > TXGBE_PMMBX_BSIZE) {\n+\t\tDEBUGOUT(\"Buffer length failure buffersize=%d.\\n\", length);\n+\t\treturn TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\t}\n+\n+\t/* Take management host interface semaphore */\n+\terr = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = txgbe_hic_unlocked(hw, buffer, length, timeout);\n+\tif (err)\n+\t\tgoto rel_out;\n+\n+\tif (!return_data)\n+\t\tgoto rel_out;\n+\n+\t/* Calculate length in DWORDs */\n+\tdword_len = hdr_size >> 2;\n+\n+\t/* first pull in the header so we know the buffer length */\n+\tfor (bi = 0; bi < dword_len; bi++)\n+\t\tbuffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);\n+\n+\t/*\n+\t * If there is any thing in data position pull it in\n+\t * Read Flash command requires reading buffer length from\n+\t * two byes instead of one byte\n+\t */\n+\tif (resp->cmd == 0x30) {\n+\t\tfor (; bi < dword_len + 2; bi++)\n+\t\t\tbuffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);\n+\n+\t\tbuf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)\n+\t\t\t\t & 0xF00) | resp->buf_len;\n+\t\thdr_size += (2 << 2);\n+\t} else {\n+\t\tbuf_len = resp->buf_len;\n+\t}\n+\tif (!buf_len)\n+\t\tgoto rel_out;\n+\n+\tif (length < buf_len + hdr_size) {\n+\t\tDEBUGOUT(\"Buffer not large enough for reply message.\\n\");\n+\t\terr = TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\t\tgoto rel_out;\n+\t}\n+\n+\t/* Calculate length in DWORDs, add 3 for odd lengths */\n+\tdword_len = (buf_len + 3) >> 2;\n+\n+\t/* Pull in the rest of the buffer (bi is where we left off) */\n+\tfor (; bi <= dword_len; bi++)\n+\t\tbuffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);\n+\n+rel_out:\n+\thw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_hic_sr_read - Read EEPROM word using a host interface cmd\n+ * assuming that the semaphore is already obtained.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 16 bit word from the EEPROM using the hostif.\n+ **/\n+s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)\n+{\n+\tstruct txgbe_hic_read_shadow_ram command;\n+\tu32 value;\n+\tint err, i = 0, j = 0;\n+\n+\tif (len > TXGBE_PMMBX_DATA_SIZE)\n+\t\treturn TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\n+\tmemset(&command, 0, sizeof(command));\n+\tcommand.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;\n+\tcommand.hdr.req.buf_lenh = 0;\n+\tcommand.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;\n+\tcommand.hdr.req.checksum = FW_DEFAULT_CHECKSUM;\n+\tcommand.address = cpu_to_be32(addr);\n+\tcommand.length = cpu_to_be16(len);\n+\n+\terr = txgbe_hic_unlocked(hw, (u32 *)&command,\n+\t\t\tsizeof(command), TXGBE_HI_COMMAND_TIMEOUT);\n+\tif (err)\n+\t\treturn err;\n+\n+\twhile (i < (len >> 2)) {\n+\t\tvalue = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i);\n+\t\t((u32 *)buf)[i] = value;\n+\t\ti++;\n+\t}\n+\n+\tvalue = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i);\n+\tfor (i <<= 2; i < len; i++)\n+\t\t((u8 *)buf)[i] = ((u8 *)&value)[j++];\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_hic_sr_write - Write EEPROM word using hostif\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of word in the EEPROM to write\n+ * @data: word write to the EEPROM\n+ *\n+ * Write a 16 bit word to the EEPROM using the hostif.\n+ **/\n+s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)\n+{\n+\tstruct txgbe_hic_write_shadow_ram command;\n+\tu32 value;\n+\tint err = 0, i = 0, j = 0;\n+\n+\tif (len > TXGBE_PMMBX_DATA_SIZE)\n+\t\treturn TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\n+\tmemset(&command, 0, sizeof(command));\n+\tcommand.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;\n+\tcommand.hdr.req.buf_lenh = 0;\n+\tcommand.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;\n+\tcommand.hdr.req.checksum = FW_DEFAULT_CHECKSUM;\n+\tcommand.address = cpu_to_be32(addr);\n+\tcommand.length = cpu_to_be16(len);\n+\n+\twhile (i < (len >> 2)) {\n+\t\tvalue = ((u32 *)buf)[i];\n+\t\twr32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i, value);\n+\t\ti++;\n+\t}\n+\n+\tfor (i <<= 2; i < len; i++)\n+\t\t((u8 *)&value)[j++] = ((u8 *)buf)[i];\n+\n+\twr32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + (i >> 2), value);\n+\n+\tUNREFERENCED_PARAMETER(&command);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_hic_set_drv_ver - Sends driver version to firmware\n+ * @hw: pointer to the HW structure\n+ * @maj: driver version major number\n+ * @min: driver version minor number\n+ * @build: driver version build number\n+ * @sub: driver version sub build number\n+ * @len: unused\n+ * @driver_ver: unused\n+ *\n+ * Sends driver version number to firmware through the manageability\n+ * block. On success return 0\n+ * else returns TXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n+ * semaphore or TXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ **/\n+s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min,\n+\t\t\t\t u8 build, u8 sub, u16 len,\n+\t\t\t\t const char *driver_ver)\n+{\n+\tstruct txgbe_hic_drv_info fw_cmd;\n+\tint i;\n+\ts32 ret_val = 0;\n+\n+\tDEBUGFUNC(\"txgbe_hic_set_drv_ver\");\n+\tUNREFERENCED_PARAMETER(len, driver_ver);\n+\n+\tfw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;\n+\tfw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;\n+\tfw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;\n+\tfw_cmd.port_num = (u8)hw->bus.func;\n+\tfw_cmd.ver_maj = maj;\n+\tfw_cmd.ver_min = min;\n+\tfw_cmd.ver_build = build;\n+\tfw_cmd.ver_sub = sub;\n+\tfw_cmd.hdr.checksum = 0;\n+\tfw_cmd.pad = 0;\n+\tfw_cmd.pad2 = 0;\n+\tfw_cmd.hdr.checksum = txgbe_calculate_checksum((u8 *)&fw_cmd,\n+\t\t\t\t(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));\n+\n+\tfor (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {\n+\t\tret_val = txgbe_host_interface_command(hw, (u32 *)&fw_cmd,\n+\t\t\t\t\t\t sizeof(fw_cmd),\n+\t\t\t\t\t\t TXGBE_HI_COMMAND_TIMEOUT,\n+\t\t\t\t\t\t true);\n+\t\tif (ret_val != 0)\n+\t\t\tcontinue;\n+\n+\t\tif (fw_cmd.hdr.cmd_or_resp.ret_status ==\n+\t\t FW_CEM_RESP_STATUS_SUCCESS)\n+\t\t\tret_val = 0;\n+\t\telse\n+\t\t\tret_val = TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\n+\t\tbreak;\n+\t}\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * txgbe_hic_reset - send reset cmd to fw\n+ * @hw: pointer to hardware structure\n+ *\n+ * Sends reset cmd to firmware through the manageability\n+ * block. On success return 0\n+ * else returns TXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n+ * semaphore or TXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n+ **/\n+s32\n+txgbe_hic_reset(struct txgbe_hw *hw)\n+{\n+\tstruct txgbe_hic_reset reset_cmd;\n+\tint i;\n+\ts32 err = 0;\n+\n+\tDEBUGFUNC(\"\\n\");\n+\n+\treset_cmd.hdr.cmd = FW_RESET_CMD;\n+\treset_cmd.hdr.buf_len = FW_RESET_LEN;\n+\treset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;\n+\treset_cmd.lan_id = hw->bus.lan_id;\n+\treset_cmd.reset_type = (u16)hw->reset_type;\n+\treset_cmd.hdr.checksum = 0;\n+\treset_cmd.hdr.checksum = txgbe_calculate_checksum((u8 *)&reset_cmd,\n+\t\t\t\t(FW_CEM_HDR_LEN + reset_cmd.hdr.buf_len));\n+\n+\tfor (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {\n+\t\terr = txgbe_host_interface_command(hw, (u32 *)&reset_cmd,\n+\t\t\t\t\t\t sizeof(reset_cmd),\n+\t\t\t\t\t\t TXGBE_HI_COMMAND_TIMEOUT,\n+\t\t\t\t\t\t true);\n+\t\tif (err != 0)\n+\t\t\tcontinue;\n+\n+\t\tif (reset_cmd.hdr.cmd_or_resp.ret_status ==\n+\t\t FW_CEM_RESP_STATUS_SUCCESS)\n+\t\t\terr = 0;\n+\t\telse\n+\t\t\terr = TXGBE_ERR_HOST_INTERFACE_COMMAND;\n+\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_mng_present - returns true when management capability is present\n+ * @hw: pointer to hardware structure\n+ */\n+bool\n+txgbe_mng_present(struct txgbe_hw *hw)\n+{\n+\tif (hw->mac.type == txgbe_mac_unknown)\n+\t\treturn false;\n+\n+\treturn !!rd32m(hw, TXGBE_STAT, TXGBE_STAT_MNGINIT);\n+}\n+\n+/**\n+ * txgbe_mng_enabled - Is the manageability engine enabled?\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns true if the manageability engine is enabled.\n+ **/\n+bool\n+txgbe_mng_enabled(struct txgbe_hw *hw)\n+{\n+\tUNREFERENCED_PARAMETER(hw);\n+\t/* firmware does not control laser */\n+\treturn false;\n+}\ndiff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h\nnew file mode 100644\nindex 000000000..7514cc1e1\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_mng.h\n@@ -0,0 +1,176 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#ifndef _TXGBE_MNG_H_\n+#define _TXGBE_MNG_H_\n+\n+#include \"txgbe_type.h\"\n+\n+\n+#define TXGBE_PMMBX_QSIZE 64 /* Num of dwords in range */\n+#define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4)\n+#define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4)\n+#define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */\n+#define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */\n+#define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */\n+#define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */\n+#define TXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */\n+\n+/* CEM Support */\n+#define FW_CEM_HDR_LEN 0x4\n+#define FW_CEM_CMD_DRIVER_INFO 0xDD\n+#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5\n+#define FW_CEM_CMD_RESERVED 0X0\n+#define FW_CEM_UNUSED_VER 0x0\n+#define FW_CEM_MAX_RETRIES 3\n+#define FW_CEM_RESP_STATUS_SUCCESS 0x1\n+#define FW_READ_SHADOW_RAM_CMD 0x31\n+#define FW_READ_SHADOW_RAM_LEN 0x6\n+#define FW_WRITE_SHADOW_RAM_CMD 0x33\n+#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */\n+#define FW_SHADOW_RAM_DUMP_CMD 0x36\n+#define FW_SHADOW_RAM_DUMP_LEN 0\n+#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */\n+#define FW_NVM_DATA_OFFSET 3\n+#define FW_MAX_READ_BUFFER_SIZE 244\n+#define FW_DISABLE_RXEN_CMD 0xDE\n+#define FW_DISABLE_RXEN_LEN 0x1\n+#define FW_PHY_MGMT_REQ_CMD 0x20\n+#define FW_RESET_CMD 0xDF\n+#define FW_RESET_LEN 0x2\n+#define FW_SETUP_MAC_LINK_CMD 0xE0\n+#define FW_SETUP_MAC_LINK_LEN 0x2\n+#define FW_FLASH_UPGRADE_START_CMD 0xE3\n+#define FW_FLASH_UPGRADE_START_LEN 0x1\n+#define FW_FLASH_UPGRADE_WRITE_CMD 0xE4\n+#define FW_FLASH_UPGRADE_VERIFY_CMD 0xE5\n+#define FW_FLASH_UPGRADE_VERIFY_LEN 0x4\n+#define FW_PHY_ACT_DATA_COUNT\t\t4\n+#define FW_PHY_TOKEN_DELAY\t\t5\t/* milliseconds */\n+#define FW_PHY_TOKEN_WAIT\t\t5\t/* seconds */\n+#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)\n+\n+/* Host Interface Command Structures */\n+struct txgbe_hic_hdr {\n+\tu8 cmd;\n+\tu8 buf_len;\n+\tunion {\n+\t\tu8 cmd_resv;\n+\t\tu8 ret_status;\n+\t} cmd_or_resp;\n+\tu8 checksum;\n+};\n+\n+struct txgbe_hic_hdr2_req {\n+\tu8 cmd;\n+\tu8 buf_lenh;\n+\tu8 buf_lenl;\n+\tu8 checksum;\n+};\n+\n+struct txgbe_hic_hdr2_rsp {\n+\tu8 cmd;\n+\tu8 buf_lenl;\n+\tu8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */\n+\tu8 checksum;\n+};\n+\n+union txgbe_hic_hdr2 {\n+\tstruct txgbe_hic_hdr2_req req;\n+\tstruct txgbe_hic_hdr2_rsp rsp;\n+};\n+\n+struct txgbe_hic_drv_info {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu8 port_num;\n+\tu8 ver_sub;\n+\tu8 ver_build;\n+\tu8 ver_min;\n+\tu8 ver_maj;\n+\tu8 pad; /* end spacing to ensure length is mult. of dword */\n+\tu16 pad2; /* end spacing to ensure length is mult. of dword2 */\n+};\n+\n+/* These need to be dword aligned */\n+struct txgbe_hic_read_shadow_ram {\n+\tunion txgbe_hic_hdr2 hdr;\n+\tu32 address;\n+\tu16 length;\n+\tu16 pad2;\n+\tu16 data;\n+\tu16 pad3;\n+};\n+\n+struct txgbe_hic_write_shadow_ram {\n+\tunion txgbe_hic_hdr2 hdr;\n+\tu32 address;\n+\tu16 length;\n+\tu16 pad2;\n+\tu16 data;\n+\tu16 pad3;\n+};\n+\n+struct txgbe_hic_disable_rxen {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu8 port_number;\n+\tu8 pad2;\n+\tu16 pad3;\n+};\n+\n+struct txgbe_hic_reset {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu16 lan_id;\n+\tu16 reset_type;\n+};\n+\n+struct txgbe_hic_phy_cfg {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu8 lan_id;\n+\tu8 phy_mode;\n+\tu16 phy_speed;\n+};\n+\n+enum txgbe_module_id {\n+\tTXGBE_MODULE_EEPROM = 0,\n+\tTXGBE_MODULE_FIRMWARE,\n+\tTXGBE_MODULE_HARDWARE,\n+\tTXGBE_MODULE_PCIE\n+};\n+\n+struct txgbe_hic_upg_start {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu8 module_id;\n+\tu8 pad2;\n+\tu16 pad3;\n+};\n+\n+struct txgbe_hic_upg_write {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu8 data_len;\n+\tu8 eof_flag;\n+\tu16 check_sum;\n+\tu32 data[62];\n+};\n+\n+enum txgbe_upg_flag {\n+\tTXGBE_RESET_NONE = 0,\n+\tTXGBE_RESET_FIRMWARE,\n+\tTXGBE_RELOAD_EEPROM,\n+\tTXGBE_RESET_LAN\n+};\n+\n+struct txgbe_hic_upg_verify {\n+\tstruct txgbe_hic_hdr hdr;\n+\tu32 action_flag;\n+};\n+\n+s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);\n+s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);\n+\n+s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,\n+\t\t\tu8 ver, u16 len, const char *str);\n+s32 txgbe_hic_reset(struct txgbe_hw *hw);\n+bool txgbe_mng_present(struct txgbe_hw *hw);\n+bool txgbe_mng_enabled(struct txgbe_hw *hw);\n+#endif /* _TXGBE_MNG_H_ */\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 87c2e1681..c43c39e99 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -13,6 +13,13 @@\n #include \"txgbe_osdep.h\"\n #include \"txgbe_devids.h\"\n \n+enum txgbe_eeprom_type {\n+\ttxgbe_eeprom_unknown = 0,\n+\ttxgbe_eeprom_spi,\n+\ttxgbe_eeprom_flash,\n+\ttxgbe_eeprom_none /* No NVM support */\n+};\n+\n enum txgbe_mac_type {\n \ttxgbe_mac_unknown = 0,\n \ttxgbe_mac_raptor,\n@@ -177,6 +184,15 @@ struct txgbe_rom_info {\n \ts32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);\n \ts32 (*update_checksum)(struct txgbe_hw *hw);\n \ts32 (*calc_checksum)(struct txgbe_hw *hw);\n+\n+\tenum txgbe_eeprom_type type;\n+\tu32 semaphore_delay;\n+\tu16 word_size;\n+\tu16 address_bits;\n+\tu16 word_page_size;\n+\tu16 ctrl_word_3;\n+\n+\tu32 sw_addr;\n };\n \n struct txgbe_flash_info {\n@@ -357,6 +373,11 @@ struct txgbe_hw {\n \n \tuint64_t isb_dma;\n \tvoid IOMEM *isb_mem;\n+\tenum txgbe_reset_type {\n+\t\tTXGBE_LAN_RESET = 0,\n+\t\tTXGBE_SW_RESET,\n+\t\tTXGBE_GLOBAL_RESET\n+\t} reset_type;\n };\n \n #include \"txgbe_regs.h\"\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 8cc0d79fe..9c980b9a9 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -51,6 +51,7 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \tstruct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tconst struct rte_memzone *mz;\n+\tuint16_t csum;\n \tint err;\n \n \tPMD_INIT_FUNC_TRACE();\n@@ -81,6 +82,19 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \t\treturn -EIO;\n \t}\n \n+\terr = hw->rom.init_params(hw);\n+\tif (err != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"The EEPROM init failed: %d\", err);\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Make sure we have a good EEPROM before we read from it */\n+\terr = hw->rom.validate_checksum(hw, &csum);\n+\tif (err != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"The EEPROM checksum is not valid: %d\", err);\n+\t\treturn -EIO;\n+\t}\n+\n \t/* Allocate memory for storing MAC addresses */\n \teth_dev->data->mac_addrs = rte_zmalloc(\"txgbe\", RTE_ETHER_ADDR_LEN *\n \t\t\t\t\t hw->mac.num_rar_entries, 0);\n", "prefixes": [ "v4", "07/58" ] }