Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/81294/?format=api
{ "id": 81294, "url": "http://patches.dpdk.org/api/patches/81294/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-12-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-12-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-12-jiawenwu@trustnetic.com", "date": "2020-10-19T08:53:28", "name": "[v4,11/58] net/txgbe: add PHY reset", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4d79ced66f155eb1df11ee5716b1995bba349598", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-12-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81294/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81294/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 72027A04DC;\n\tMon, 19 Oct 2020 10:56:20 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1379BC8CC;\n\tMon, 19 Oct 2020 10:53:04 +0200 (CEST)", "from smtpbg501.qq.com (smtpbg501.qq.com [203.205.250.101])\n by dpdk.org (Postfix) with ESMTP id 369E9C82C\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:52:48 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:52:41 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097561tvzqkvoe7", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "VGEHthcaPSSQZRYi8sTP67hzjHTw4PGY6tSG+fNCFF5HwOYm21nrpVXnnfHDR\n 9+p1+JOvWk3XlT5adpimvA7gRQMxJ3spaCMPKAO007NRvTZC43p0K4ELBod+5juHpiPeDqF\n Rdo4YBvLz8AJ9ZX3iToIaXkU+0E4J7XFBeZTlQ+4W69NBpfq9Mnu4A/i6jFDGCSNsc1+nxE\n z3x3ECMBIGzxdosY7KE8LQqqlnI7wDApYFtr06gVzXjYd6DAOXq3FIo23pq+ZbMfYcQx+7v\n 9g5BtCglffKx34V4mcExx1awuzSNJlE4tpdTyx31MQk67KkOfIoayJM7/jO8c2MjGJzU9wb\n ZKL7l8s2iPtD9Mj7Jwdi/BZQmE8Xg==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:53:28 +0800", "Message-Id": "<20201019085415.82207-12-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v4 11/58] net/txgbe: add PHY reset", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add phy reset function, support read and write phy registers.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_hw.c | 5 +\n drivers/net/txgbe/base/txgbe_phy.c | 226 +++++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_phy.h | 10 ++\n 3 files changed, 241 insertions(+)", "diff": "diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex d2d12a929..598ef3e99 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -291,10 +291,15 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)\n \t/* PHY */\n \tphy->identify = txgbe_identify_phy;\n \tphy->init = txgbe_init_phy_raptor;\n+\tphy->read_reg = txgbe_read_phy_reg;\n+\tphy->write_reg = txgbe_write_phy_reg;\n+\tphy->read_reg_mdi = txgbe_read_phy_reg_mdi;\n+\tphy->write_reg_mdi = txgbe_write_phy_reg_mdi;\n \tphy->read_i2c_byte = txgbe_read_i2c_byte;\n \tphy->write_i2c_byte = txgbe_write_i2c_byte;\n \tphy->read_i2c_eeprom = txgbe_read_i2c_eeprom;\n \tphy->write_i2c_eeprom = txgbe_write_i2c_eeprom;\n+\tphy->reset = txgbe_reset_phy;\n \n \t/* MAC */\n \tmac->init_hw = txgbe_init_hw;\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c\nindex b36bffcac..347641ce9 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.c\n+++ b/drivers/net/txgbe/base/txgbe_phy.c\n@@ -111,6 +111,30 @@ s32 txgbe_identify_phy(struct txgbe_hw *hw)\n \treturn err;\n }\n \n+/**\n+ * txgbe_check_reset_blocked - check status of MNG FW veto bit\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This function checks the STAT.MNGVETO bit to see if there are\n+ * any constraints on link from manageability. For MAC's that don't\n+ * have this bit just return faluse since the link can not be blocked\n+ * via this method.\n+ **/\n+s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)\n+{\n+\tu32 mmngc;\n+\n+\tDEBUGFUNC(\"txgbe_check_reset_blocked\");\n+\n+\tmmngc = rd32(hw, TXGBE_STAT);\n+\tif (mmngc & TXGBE_STAT_MNGVETO) {\n+\t\tDEBUGOUT(\"MNG_VETO bit detected.\\n\");\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n /**\n * txgbe_validate_phy_addr - Determines phy address is valid\n * @hw: pointer to hardware structure\n@@ -199,6 +223,208 @@ enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)\n \treturn phy_type;\n }\n \n+static s32\n+txgbe_reset_extphy(struct txgbe_hw *hw)\n+{\n+\tu16 ctrl = 0;\n+\tint err, i;\n+\n+\terr = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,\n+\t\t\tTXGBE_MD_DEV_GENERAL, &ctrl);\n+\tif (err != 0)\n+\t\treturn err;\n+\tctrl |= TXGBE_MD_PORT_CTRL_RESET;\n+\terr = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,\n+\t\t\tTXGBE_MD_DEV_GENERAL, ctrl);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\t/*\n+\t * Poll for reset bit to self-clear indicating reset is complete.\n+\t * Some PHYs could take up to 3 seconds to complete and need about\n+\t * 1.7 usec delay after the reset is complete.\n+\t */\n+\tfor (i = 0; i < 30; i++) {\n+\t\tmsec_delay(100);\n+\t\terr = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,\n+\t\t\tTXGBE_MD_DEV_GENERAL, &ctrl);\n+\t\tif (err != 0)\n+\t\t\treturn err;\n+\n+\t\tif (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {\n+\t\t\tusec_delay(2);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (ctrl & TXGBE_MD_PORT_CTRL_RESET) {\n+\t\terr = TXGBE_ERR_RESET_FAILED;\n+\t\tDEBUGOUT(\"PHY reset polling failed to complete.\\n\");\n+\t}\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_reset_phy - Performs a PHY reset\n+ * @hw: pointer to hardware structure\n+ **/\n+s32 txgbe_reset_phy(struct txgbe_hw *hw)\n+{\n+\ts32 err = 0;\n+\n+\tDEBUGFUNC(\"txgbe_reset_phy\");\n+\n+\tif (hw->phy.type == txgbe_phy_unknown)\n+\t\terr = txgbe_identify_phy(hw);\n+\n+\tif (err != 0 || hw->phy.type == txgbe_phy_none)\n+\t\treturn err;\n+\n+\t/* Don't reset PHY if it's shut down due to overtemp. */\n+\tif (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)\n+\t\treturn err;\n+\n+\t/* Blocked by MNG FW so bail */\n+\tif (txgbe_check_reset_blocked(hw))\n+\t\treturn err;\n+\n+\tswitch (hw->phy.type) {\n+\tcase txgbe_phy_cu_mtd:\n+\t\terr = txgbe_reset_extphy(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_read_phy_mdi - Reads a value from a specified PHY register without\n+ * the SWFW lock\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: 5 bit device type\n+ * @phy_data: Pointer to read data from PHY register\n+ **/\n+s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t u16 *phy_data)\n+{\n+\tu32 command, data;\n+\n+\t/* Setup and write the address cycle command */\n+\tcommand = TXGBE_MDIOSCA_REG(reg_addr) |\n+\t\t TXGBE_MDIOSCA_DEV(device_type) |\n+\t\t TXGBE_MDIOSCA_PORT(hw->phy.addr);\n+\twr32(hw, TXGBE_MDIOSCA, command);\n+\n+\tcommand = TXGBE_MDIOSCD_CMD_READ |\n+\t\t TXGBE_MDIOSCD_BUSY;\n+\twr32(hw, TXGBE_MDIOSCD, command);\n+\n+\t/*\n+\t * Check every 10 usec to see if the address cycle completed.\n+\t * The MDI Command bit will clear when the operation is\n+\t * complete\n+\t */\n+\tif (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,\n+\t\t0, NULL, 100, 100)) {\n+\t\tDEBUGOUT(\"PHY address command did not complete\\n\");\n+\t\treturn TXGBE_ERR_PHY;\n+\t}\n+\n+\tdata = rd32(hw, TXGBE_MDIOSCD);\n+\t*phy_data = (u16)TXGBD_MDIOSCD_DAT(data);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_read_phy_reg - Reads a value from a specified PHY register\n+ * using the SWFW lock - this function is needed in most cases\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: 5 bit device type\n+ * @phy_data: Pointer to read data from PHY register\n+ **/\n+s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,\n+\t\t\t u32 device_type, u16 *phy_data)\n+{\n+\ts32 err;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tDEBUGFUNC(\"txgbe_read_phy_reg\");\n+\n+\tif (hw->mac.acquire_swfw_sync(hw, gssr))\n+\t\treturn TXGBE_ERR_SWFW_SYNC;\n+\n+\terr = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);\n+\n+\thw->mac.release_swfw_sync(hw, gssr);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register\n+ * without SWFW lock\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 5 bit device type\n+ * @phy_data: Data to write to the PHY register\n+ **/\n+s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data)\n+{\n+\tu32 command;\n+\n+\t/* write command */\n+\tcommand = TXGBE_MDIOSCA_REG(reg_addr) |\n+\t\t TXGBE_MDIOSCA_DEV(device_type) |\n+\t\t TXGBE_MDIOSCA_PORT(hw->phy.addr);\n+\twr32(hw, TXGBE_MDIOSCA, command);\n+\n+\tcommand = TXGBE_MDIOSCD_CMD_WRITE |\n+\t\t TXGBE_MDIOSCD_DAT(phy_data) |\n+\t\t TXGBE_MDIOSCD_BUSY;\n+\twr32(hw, TXGBE_MDIOSCD, command);\n+\n+\t/* wait for completion */\n+\tif (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,\n+\t\t0, NULL, 100, 100)) {\n+\t\tTLOG_DEBUG(\"PHY write cmd didn't complete\\n\");\n+\t\treturn -TERR_PHY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_write_phy_reg - Writes a value to specified PHY register\n+ * using SWFW lock- this function is needed in most cases\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: 5 bit device type\n+ * @phy_data: Data to write to the PHY register\n+ **/\n+s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data)\n+{\n+\ts32 err;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tDEBUGFUNC(\"txgbe_write_phy_reg\");\n+\n+\tif (hw->mac.acquire_swfw_sync(hw, gssr))\n+\t\terr = TXGBE_ERR_SWFW_SYNC;\n+\n+\terr = hw->phy.write_reg_mdi(hw, reg_addr, device_type,\n+\t\t\t\t\t phy_data);\n+\thw->mac.release_swfw_sync(hw, gssr);\n+\n+\treturn err;\n+}\n /**\n * txgbe_identify_module - Identifies module type\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h\nindex 3c3f2914a..750934e06 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.h\n+++ b/drivers/net/txgbe/base/txgbe_phy.h\n@@ -327,6 +327,16 @@ bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr);\n enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id);\n s32 txgbe_get_phy_id(struct txgbe_hw *hw);\n s32 txgbe_identify_phy(struct txgbe_hw *hw);\n+s32 txgbe_reset_phy(struct txgbe_hw *hw);\n+s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t u16 *phy_data);\n+s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t u16 phy_data);\n+s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,\n+\t\t\t u32 device_type, u16 *phy_data);\n+s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data);\n+s32 txgbe_check_reset_blocked(struct txgbe_hw *hw);\n \n /* PHY specific */\n s32 txgbe_identify_module(struct txgbe_hw *hw);\n", "prefixes": [ "v4", "11/58" ] }