Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/80872/?format=api
{ "id": 80872, "url": "http://patches.dpdk.org/api/patches/80872/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201015103814.253636-17-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201015103814.253636-17-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201015103814.253636-17-ciara.power@intel.com", "date": "2020-10-15T10:38:12", "name": "[v6,16/18] net: add checks for max SIMD bitwidth", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1f87fce339d906ce03b836cf233ac64da3f3167c", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201015103814.253636-17-ciara.power@intel.com/mbox/", "series": [ { "id": 13000, "url": "http://patches.dpdk.org/api/series/13000/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13000", "date": "2020-10-15T10:37:56", "name": "add max SIMD bitwidth to EAL", "version": 6, "mbox": "http://patches.dpdk.org/series/13000/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80872/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/80872/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81E02A04DB;\n\tThu, 15 Oct 2020 12:43:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CA3761E48F;\n\tThu, 15 Oct 2020 12:39:03 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id C36F81E31E\n for <dev@dpdk.org>; Thu, 15 Oct 2020 12:39:00 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Oct 2020 03:39:00 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.239])\n by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:57 -0700" ], "IronPort-SDR": [ "\n gnFEQXg5+nRc+qcJLwwXNMAaOUD5bDJ7CghgjyQs9ABujKno6gtJFY6lhj5G5rKgd2GFHCjqYR\n x0DhHi2TFJyA==", "\n xMx0T1ZG2UPv9BDtNz4hTBz7RyS/Xxz64rMgJdVDbFEvchKWeEuiRkA1daw/2ItfE8+6Ope4B3\n 3w3XzSdsk3RA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9774\"; a=\"227964294\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"227964294\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"520728592\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com,\n drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, Ciara Power <ciara.power@intel.com>,\n Jasvinder Singh <jasvinder.singh@intel.com>,\n Olivier Matz <olivier.matz@6wind.com>", "Date": "Thu, 15 Oct 2020 11:38:12 +0100", "Message-Id": "<20201015103814.253636-17-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20201015103814.253636-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20201015103814.253636-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v6 16/18] net: add checks for max SIMD bitwidth", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath.\n\nThe vector path was initially chosen in RTE_INIT, however this is no\nlonger suitable as we cannot check the max SIMD bitwidth at that time.\nDefault handlers are now chosen on initialisation, these default\nhandlers are used the first time the crc calc is called, and they set\nthe suitable handlers to be used going forward.\n\nSuggested-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSuggested-by: Olivier Matz <olivier.matz@6wind.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n\n---\nv6:\n - Moved log variable and macro to c file instead of public header.\n - Added the max_simd_bitwidth condition check to the recently added\n handler helper functions.\n - Modified default handlers to follow the approach of the set alg\n function.\nv4:\n - Added default handlers to be set at RTE_INIT time, rather than\n choosing scalar handlers.\n - Modified logging.\n - Updated enum name.\nv3:\n - Moved choosing vector paths out of RTE_INIT.\n - Moved checking max_simd_bitwidth into the set_alg function.\n---\n lib/librte_net/rte_net_crc.c | 117 +++++++++++++++++++++++++----------\n 1 file changed, 86 insertions(+), 31 deletions(-)", "diff": "diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c\nindex 32a3665908..bce5f5f15b 100644\n--- a/lib/librte_net/rte_net_crc.c\n+++ b/lib/librte_net/rte_net_crc.c\n@@ -9,6 +9,8 @@\n #include <rte_cpuflags.h>\n #include <rte_common.h>\n #include <rte_net_crc.h>\n+#include <rte_eal.h>\n+#include <rte_log.h>\n \n #include \"net_crc.h\"\n \n@@ -22,6 +24,12 @@\n static uint32_t crc32_eth_lut[CRC_LUT_SIZE];\n static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];\n \n+static uint32_t\n+rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len);\n+\n+static uint32_t\n+rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len);\n+\n static uint32_t\n rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);\n \n@@ -31,7 +39,12 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);\n typedef uint32_t\n (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);\n \n-static const rte_net_crc_handler *handlers;\n+static rte_net_crc_handler handlers_default[] = {\n+\t[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler,\n+\t[RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler,\n+};\n+\n+static const rte_net_crc_handler *handlers = handlers_default;\n \n static const rte_net_crc_handler handlers_scalar[] = {\n \t[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,\n@@ -56,6 +69,15 @@ static const rte_net_crc_handler handlers_neon[] = {\n };\n #endif\n \n+static uint16_t max_simd_bitwidth;\n+extern int libnet_logtype;\n+\n+#define NET_LOG(level, fmt, args...)\t\t\t\t\t\\\n+\trte_log(RTE_LOG_ ## level, libnet_logtype, \"%s(): \" fmt \"\\n\",\t\\\n+\t\t__func__, ## args)\n+\n+RTE_LOG_REGISTER(libnet_logtype, lib.net, INFO);\n+\n /* Scalar handling */\n \n /**\n@@ -155,22 +177,21 @@ static const rte_net_crc_handler *\n avx512_vpclmulqdq_get_handlers(void)\n {\n #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT\n-\tif (AVX512_VPCLMULQDQ_CPU_SUPPORTED)\n+\tif (AVX512_VPCLMULQDQ_CPU_SUPPORTED &&\n+\t\t\tmax_simd_bitwidth >= RTE_SIMD_512)\n \t\treturn handlers_avx512;\n #endif\n+\tNET_LOG(INFO, \"Requirements not met, can't use AVX512\\n\");\n \treturn NULL;\n }\n \n-static uint8_t\n+static void\n avx512_vpclmulqdq_init(void)\n {\n #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT\n-\tif (AVX512_VPCLMULQDQ_CPU_SUPPORTED) {\n+\tif (AVX512_VPCLMULQDQ_CPU_SUPPORTED)\n \t\trte_net_crc_avx512_init();\n-\t\treturn 1;\n-\t}\n #endif\n-\treturn 0;\n }\n \n /* SSE4.2/PCLMULQDQ handling */\n@@ -182,22 +203,21 @@ static const rte_net_crc_handler *\n sse42_pclmulqdq_get_handlers(void)\n {\n #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n-\tif (SSE42_PCLMULQDQ_CPU_SUPPORTED)\n+\tif (SSE42_PCLMULQDQ_CPU_SUPPORTED &&\n+\t\t\tmax_simd_bitwidth >= RTE_SIMD_128)\n \t\treturn handlers_sse42;\n #endif\n+\tNET_LOG(INFO, \"Requirements not met, can't use SSE\\n\");\n \treturn NULL;\n }\n \n-static uint8_t\n+static void\n sse42_pclmulqdq_init(void)\n {\n #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n-\tif (SSE42_PCLMULQDQ_CPU_SUPPORTED) {\n+\tif (SSE42_PCLMULQDQ_CPU_SUPPORTED)\n \t\trte_net_crc_sse42_init();\n-\t\treturn 1;\n-\t}\n #endif\n-\treturn 0;\n }\n \n /* NEON/PMULL handling */\n@@ -209,22 +229,63 @@ static const rte_net_crc_handler *\n neon_pmull_get_handlers(void)\n {\n #ifdef CC_ARM64_NEON_PMULL_SUPPORT\n-\tif (NEON_PMULL_CPU_SUPPORTED)\n+\tif (NEON_PMULL_CPU_SUPPORTED &&\n+\t\t\tmax_simd_bitwidth >= RTE_SIMD_128)\n \t\treturn handlers_neon;\n #endif\n+\tNET_LOG(INFO, \"Requirements not met, can't use NEON\\n\");\n \treturn NULL;\n }\n \n-static uint8_t\n+static void\n neon_pmull_init(void)\n {\n #ifdef CC_ARM64_NEON_PMULL_SUPPORT\n-\tif (NEON_PMULL_CPU_SUPPORTED) {\n+\tif (NEON_PMULL_CPU_SUPPORTED)\n \t\trte_net_crc_neon_init();\n-\t\treturn 1;\n-\t}\n #endif\n-\treturn 0;\n+}\n+\n+/* Default handling */\n+\n+static uint32_t\n+rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len)\n+{\n+\thandlers = NULL;\n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n+\n+\thandlers = avx512_vpclmulqdq_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC16_CCITT](data, data_len);\n+\thandlers = sse42_pclmulqdq_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC16_CCITT](data, data_len);\n+\thandlers = neon_pmull_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC16_CCITT](data, data_len);\n+\thandlers = handlers_scalar;\n+\treturn handlers[RTE_NET_CRC16_CCITT](data, data_len);\n+}\n+\n+static uint32_t\n+rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len)\n+{\n+\thandlers = NULL;\n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n+\n+\thandlers = avx512_vpclmulqdq_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC32_ETH](data, data_len);\n+\thandlers = sse42_pclmulqdq_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC32_ETH](data, data_len);\n+\thandlers = neon_pmull_get_handlers();\n+\tif (handlers != NULL)\n+\t\treturn handlers[RTE_NET_CRC32_ETH](data, data_len);\n+\thandlers = handlers_scalar;\n+\treturn handlers[RTE_NET_CRC32_ETH](data, data_len);\n }\n \n /* Public API */\n@@ -233,6 +294,8 @@ void\n rte_net_crc_set_alg(enum rte_net_crc_alg alg)\n {\n \thandlers = NULL;\n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n \n \tswitch (alg) {\n \tcase RTE_NET_CRC_AVX512:\n@@ -270,19 +333,11 @@ rte_net_crc_calc(const void *data,\n \treturn ret;\n }\n \n-/* Select highest available crc algorithm as default one */\n+/* Call initialisation helpers for all crc algorithm handlers */\n RTE_INIT(rte_net_crc_init)\n {\n-\tenum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;\n-\n \trte_net_crc_scalar_init();\n-\n-\tif (sse42_pclmulqdq_init())\n-\t\talg = RTE_NET_CRC_SSE42;\n-\tif (avx512_vpclmulqdq_init())\n-\t\talg = RTE_NET_CRC_AVX512;\n-\tif (neon_pmull_init())\n-\t\talg = RTE_NET_CRC_NEON;\n-\n-\trte_net_crc_set_alg(alg);\n+\tsse42_pclmulqdq_init();\n+\tavx512_vpclmulqdq_init();\n+\tneon_pmull_init();\n }\n", "prefixes": [ "v6", "16/18" ] }