Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/80854/?format=api
{ "id": 80854, "url": "http://patches.dpdk.org/api/patches/80854/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201015103237.43497-1-harry.van.haaren@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201015103237.43497-1-harry.van.haaren@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201015103237.43497-1-harry.van.haaren@intel.com", "date": "2020-10-15T10:32:37", "name": "[v3] eal: add new prefetch write variants", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a10865bcb1ad7c136de729a21b08e308e008ddac", "submitter": { "id": 317, "url": "http://patches.dpdk.org/api/people/317/?format=api", "name": "Van Haaren, Harry", "email": "harry.van.haaren@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201015103237.43497-1-harry.van.haaren@intel.com/mbox/", "series": [ { "id": 12998, "url": "http://patches.dpdk.org/api/series/12998/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12998", "date": "2020-10-15T10:32:37", "name": "[v3] eal: add new prefetch write variants", "version": 3, "mbox": "http://patches.dpdk.org/series/12998/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80854/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80854/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA2C7A04DB;\n\tThu, 15 Oct 2020 12:31:16 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9871E1DE1E;\n\tThu, 15 Oct 2020 12:31:15 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 09E4A1DE1E\n for <dev@dpdk.org>; Thu, 15 Oct 2020 12:31:12 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Oct 2020 03:31:09 -0700", "from silpixa00399779.ir.intel.com (HELO\n silpixa00399779.ger.corp.intel.com) ([10.237.222.209])\n by orsmga001.jf.intel.com with ESMTP; 15 Oct 2020 03:31:07 -0700" ], "IronPort-SDR": [ "\n R4cfNhmY+oY43FUTrL6w0waF5tRb7NEMkiKbOHKVR9xWozBs4Or/yGGQ9yKngPhixPZOim+vvm\n 7webUrb/Ak4Q==", "\n anDv0E6YPFGqA5fN+hPjHNN1SMyu1l6B1rfcpKAnX3kwq5rpus9oAKGOUe6Iv3LiDV8s0o4UA7\n xQ9UOMrAh3dw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9774\"; a=\"183856149\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"183856149\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"390932683\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Harry van Haaren <harry.van.haaren@intel.com>", "To": "dev@dpdk.org", "Cc": "ruifeng.wang@arm.com, david.marchand@redhat.com, jerinj@marvell.com,\n pbhagavatula@marvell.com, Harry van Haaren <harry.van.haaren@intel.com>", "Date": "Thu, 15 Oct 2020 11:32:37 +0100", "Message-Id": "<20201015103237.43497-1-harry.van.haaren@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200914151021.23806-1-harry.van.haaren@intel.com>", "References": "<20200914151021.23806-1-harry.van.haaren@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] eal: add new prefetch write variants", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds new rte_prefetchX_write() variants, that suggest to the\ncompiler to use a prefetch instruction with intention to write. As a\ncompiler builtin, the compiler can choose based on compilation target\nwhat the best implementation for this instruction is.\n\nThree versions are provided, targeting the different levels of cache.\n\nSigned-off-by: Harry van Haaren <harry.van.haaren@intel.com>\nReviewed-by: Jerin Jacob <jerinj@marvell.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n\n---\n\nv3:\n- Add reviewed by tags from Jerin and Ruifeng, thanks!\n- Add __rte_experimental as they are new functions (David)\n This required adding the rte_compat.h include.\n- Rework return type to new line (Jerin)\n- Add calls in test_prefetch.c to new functions (David)\n- Add item to release notes (David)\n\nv2:\n- Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan)\n\nThe integer constants passed to the builtin are not available as\na #define value, and doing #defines just for this write variant\ndoes not seems a nice solution to me... particularly for those using\nIDEs where any #define value is auto-hinted for code-completion.\n---\n app/test/test_prefetch.c | 4 ++\n doc/guides/rel_notes/release_20_11.rst | 6 ++\n lib/librte_eal/include/generic/rte_prefetch.h | 57 +++++++++++++++++++\n 3 files changed, 67 insertions(+)", "diff": "diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c\nindex 41f219af78..32e08f8afe 100644\n--- a/app/test/test_prefetch.c\n+++ b/app/test/test_prefetch.c\n@@ -26,6 +26,10 @@ test_prefetch(void)\n \trte_prefetch1(&a);\n \trte_prefetch2(&a);\n \n+\trte_prefetch0_write(&a);\n+\trte_prefetch1_write(&a);\n+\trte_prefetch2_write(&a);\n+\n \treturn 0;\n }\n \ndiff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 0925123e9c..8b51ef0dbc 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -62,6 +62,12 @@ New Features\n The functions are provided as a generic stubs and\n x86 specific implementation.\n \n+* **Added prefetch with intention to write APIs.**\n+\n+ Added new prefetch function variants e.g. ``rte_prefetch0_write``,\n+ which allow the programmer to prefetch a cache line and also indicate\n+ the intention to write.\n+\n * **Updated CRC modules of the net library.**\n \n * Added runtime selection of the optimal architecture-specific CRC path.\ndiff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h\nindex 6e47bdfbad..53d68c40f1 100644\n--- a/lib/librte_eal/include/generic/rte_prefetch.h\n+++ b/lib/librte_eal/include/generic/rte_prefetch.h\n@@ -5,6 +5,8 @@\n #ifndef _RTE_PREFETCH_H_\n #define _RTE_PREFETCH_H_\n \n+#include \"rte_compat.h\"\n+\n /**\n * @file\n *\n@@ -51,4 +53,59 @@ static inline void rte_prefetch2(const volatile void *p);\n */\n static inline void rte_prefetch_non_temporal(const volatile void *p);\n \n+/**\n+ * Prefetch a cache line into all cache levels, with intention to write. This\n+ * prefetch variant hints to the CPU that the program is expecting to write to\n+ * the cache line being prefetched.\n+ *\n+ * @param p Address to prefetch\n+ */\n+__rte_experimental\n+static inline void\n+rte_prefetch0_write(const void *p)\n+{\n+\t/* 1 indicates intention to write, 3 sets target cache level to L1. See\n+\t * GCC docs where these integer constants are described in more detail:\n+\t * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html\n+\t */\n+\t__builtin_prefetch(p, 1, 3);\n+}\n+\n+/**\n+ * Prefetch a cache line into all cache levels, except the 0th, with intention\n+ * to write. This prefetch variant hints to the CPU that the program is\n+ * expecting to write to the cache line being prefetched.\n+ *\n+ * @param p Address to prefetch\n+ */\n+__rte_experimental\n+static inline void\n+rte_prefetch1_write(const void *p)\n+{\n+\t/* 1 indicates intention to write, 2 sets target cache level to L2. See\n+\t * GCC docs where these integer constants are described in more detail:\n+\t * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html\n+\t */\n+\t__builtin_prefetch(p, 1, 2);\n+}\n+\n+/**\n+ * Prefetch a cache line into all cache levels, except the 0th and 1st, with\n+ * intention to write. This prefetch variant hints to the CPU that the program\n+ * is expecting to write to the cache line being prefetched.\n+ *\n+ * @param p Address to prefetch\n+ */\n+__rte_experimental\n+static inline void\n+rte_prefetch2_write(const void *p)\n+{\n+\t/* 1 indicates intention to write, 1 sets target cache level to L3. See\n+\t * GCC docs where these integer constants are described in more detail:\n+\t * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html\n+\t */\n+\t__builtin_prefetch(p, 1, 1);\n+}\n+\n+\n #endif /* _RTE_PREFETCH_H_ */\n", "prefixes": [ "v3" ] }