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GET /api/patches/80834/?format=api
{ "id": 80834, "url": "http://patches.dpdk.org/api/patches/80834/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1602743893-345348-1-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1602743893-345348-1-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1602743893-345348-1-git-send-email-matan@nvidia.com", "date": "2020-10-15T06:38:10", "name": "[1/4] net/mlx5: fix Rx queue release", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "af3a479c2c9be4f6e17321258b0dbb0f7acb7966", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1602743893-345348-1-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 12988, "url": "http://patches.dpdk.org/api/series/12988/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12988", "date": "2020-10-15T06:38:10", "name": "[1/4] net/mlx5: fix Rx queue release", "version": 1, "mbox": "http://patches.dpdk.org/series/12988/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80834/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D81F6A04DB;\n\tThu, 15 Oct 2020 08:38:33 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EDFE71DC89;\n\tThu, 15 Oct 2020 08:38:31 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 330081DC86\n for <dev@dpdk.org>; Thu, 15 Oct 2020 08:38:30 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 15 Oct 2020 09:38:23 +0300", "from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09F6cNVs014993;\n Thu, 15 Oct 2020 09:38:23 +0300" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 15 Oct 2020 06:38:10 +0000", "Message-Id": "<1602743893-345348-1-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH 1/4] net/mlx5: fix Rx queue release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The HW objects of the Rx queue is created/destroyed in the device\nstart\\stop stage while the ethdev configurations for the Rx queue\nstarts from the rx_queue_setup stage.\nThe PMD should save all the last configurations it got from the ethdev\nand to apply them to the device in the dev_start operation.\n\nWrongly, last code added to mitigate the reference counters didn't take\ninto account the above rule and combined the configurations and HW\nobjects to be created\\destroyed together.\n\nThis causes to memory leak and other memory issues.\n\nMake sure the HW object is released in stop operation when there is no\nany reference to it while the configurations stay saved.\n\nFixes: 24e4b650badc (\"net/mlx5: mitigate Rx queue reference counters\")\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 23 +++++++++++++----------\n drivers/net/mlx5/mlx5_rxtx.h | 2 +-\n 2 files changed, 14 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex f1d8373..e1783ba 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -447,7 +447,8 @@\n \t\treturn -rte_errno;\n \t}\n \trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\treturn (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);\n+\treturn (__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED) == 1);\n+\n }\n \n /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */\n@@ -1541,7 +1542,7 @@ struct mlx5_rxq_ctrl *\n \ttmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;\n #endif\n \ttmpl->rxq.idx = idx;\n-\trte_atomic32_inc(&tmpl->refcnt);\n+\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n error:\n@@ -1588,7 +1589,7 @@ struct mlx5_rxq_ctrl *\n \ttmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };\n \ttmpl->hairpin_conf = *hairpin_conf;\n \ttmpl->rxq.idx = idx;\n-\trte_atomic32_inc(&tmpl->refcnt);\n+\t__atomic_add_fetch(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n }\n@@ -1613,7 +1614,7 @@ struct mlx5_rxq_ctrl *\n \n \tif (rxq_data) {\n \t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\t\trte_atomic32_inc(&rxq_ctrl->refcnt);\n+\t\t__atomic_add_fetch(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED);\n \t}\n \treturn rxq_ctrl;\n }\n@@ -1638,7 +1639,7 @@ struct mlx5_rxq_ctrl *\n \tif (!(*priv->rxqs)[idx])\n \t\treturn 0;\n \trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\tif (!rte_atomic32_dec_and_test(&rxq_ctrl->refcnt))\n+\tif (__atomic_sub_fetch(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)\n \t\treturn 1;\n \tif (rxq_ctrl->obj) {\n \t\tpriv->obj_ops.rxq_obj_release(rxq_ctrl->obj);\n@@ -1646,13 +1647,15 @@ struct mlx5_rxq_ctrl *\n \t\tmlx5_free(rxq_ctrl->obj);\n \t\trxq_ctrl->obj = NULL;\n \t}\n-\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {\n-\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n+\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n \t\trxq_free_elts(rxq_ctrl);\n+\tif (!__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED)) {\n+\t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n+\t\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n+\t\tLIST_REMOVE(rxq_ctrl, next);\n+\t\tmlx5_free(rxq_ctrl);\n+\t\t(*priv->rxqs)[idx] = NULL;\n \t}\n-\tLIST_REMOVE(rxq_ctrl, next);\n-\tmlx5_free(rxq_ctrl);\n-\t(*priv->rxqs)[idx] = NULL;\n \treturn 0;\n }\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 674296e..c3734e3 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -165,7 +165,7 @@ enum mlx5_rxq_type {\n struct mlx5_rxq_ctrl {\n \tstruct mlx5_rxq_data rxq; /* Data path structure. */\n \tLIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */\n-\trte_atomic32_t refcnt; /* Reference counter. */\n+\tuint32_t refcnt; /* Reference counter. */\n \tstruct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */\n \tstruct mlx5_priv *priv; /* Back pointer to private data. */\n \tenum mlx5_rxq_type type; /* Rxq type. */\n", "prefixes": [ "1/4" ] }