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GET /api/patches/80691/?format=api
{ "id": 80691, "url": "http://patches.dpdk.org/api/patches/80691/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201014084131.72035-6-simonx.lu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201014084131.72035-6-simonx.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201014084131.72035-6-simonx.lu@intel.com", "date": "2020-10-14T08:41:28", "name": "[v1,5/8] net/ixgbe: use generic flow command to re-realize mirror rule", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "63c8d17808960830693ec24f56c735a4e1e45992", "submitter": { "id": 2016, "url": "http://patches.dpdk.org/api/people/2016/?format=api", "name": "SimonX Lu", "email": "simonx.lu@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201014084131.72035-6-simonx.lu@intel.com/mbox/", "series": [ { "id": 12943, "url": "http://patches.dpdk.org/api/series/12943/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12943", "date": "2020-10-14T08:41:23", "name": "use generic flow command to re-realize mirror rule", "version": 1, "mbox": "http://patches.dpdk.org/series/12943/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80691/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80691/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 095C9A04B7;\n\tWed, 14 Oct 2020 10:44:52 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 081671DD1F;\n\tWed, 14 Oct 2020 10:43:25 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id B72C11DCD7\n for <dev@dpdk.org>; Wed, 14 Oct 2020 10:43:22 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Oct 2020 01:43:22 -0700", "from intel-npg-odc-srv01.cd.intel.com ([10.240.178.136])\n by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Oct 2020 01:43:18 -0700" ], "IronPort-SDR": [ "\n Z6ljX+eLf1QyMM5QGiPBHV03UN5/D7wFHgVUgdAwbz95npQ79kDe0iJ26/6l+YwTQCaGfoGKjt\n oaeSRp2o2HzA==", "\n 2anE/pNQehPPjZ4h0fKXGUmeSH0uHAJteTae85ljQiZbjMQRfFVdzxxzfmFmchBy4fM40r+4wR\n e9ypoKOBu69g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9773\"; a=\"163432223\"", "E=Sophos;i=\"5.77,374,1596524400\"; d=\"scan'208\";a=\"163432223\"", "E=Sophos;i=\"5.77,374,1596524400\"; d=\"scan'208\";a=\"299864582\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "From": "SimonX Lu <simonx.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "jia.guo@intel.com, haiyue.wang@intel.com, qiming.yang@intel.com,\n beilei.xing@intel.com, orika@nvidia.com, Simon Lu <simonx.lu@intel.com>", "Date": "Wed, 14 Oct 2020 08:41:28 +0000", "Message-Id": "<20201014084131.72035-6-simonx.lu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201014084131.72035-1-simonx.lu@intel.com>", "References": "<20201014084131.72035-1-simonx.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v1 5/8] net/ixgbe: use generic flow command to\n\tre-realize mirror rule", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Simon Lu <simonx.lu@intel.com>\n\nfollow mirror rule to add new action called mirror in flow management,\nso we can use \"flow create * pattern * action mirror *\" to replace\nold \"set port * mirror-rule *\" command now\n\nthe example of mirror rule command mapping to flow management command:\n(in below command, port 0 is PF and port 1-3 is VF):\n\n1) ingress: pf => pf\n set port 0 mirror-rule 0 uplink-mirror dst-pool 4 on\n or\n flow create 0 ingress pattern pf / end actions mirror pf / end\n2) egress: pf => pf\n set port 0 mirror-rule 0 downlink-mirror dst-pool 4 on\n or\n flow create 0 egress pattern pf / end actions mirror pf / end\n3) ingress: pf => vf 3\n set port 0 mirror-rule 0 uplink-mirror dst-pool 3 on\n or\n flow create 0 ingress pattern pf / end actions mirror vf id 3 / end\n4) egress: pf => vf 3\n set port 0 mirror-rule 0 downlink-mirror dst-pool 3 on\n or\n flow create 0 egress pattern pf / end actions mirror vf id 3 / end\n5) ingress: vf 0,1 => pf\n set port 0 mirror-rule 0 pool-mirror-up 0x3 dst-pool 4 on\n or\n flow create 0 ingress pattern vf id is 0 / end actions mirror pf / end\n flow create 0 ingress pattern vf id is 1 / end actions mirror pf / end\n or\n flow create 0 ingress pattern vf id last 1 / end \\\n actions mirror pf / end\n or\n flow create 0 ingress pattern vf id mask 0x3 / end \\\n actions mirror pf / end\n6) ingress: vf 1,2 => vf 3\n set port 0 mirror-rule 0 pool-mirror-up 0x6 dst-pool 3 on\n or\n flow create 0 ingress pattern vf id is 1 / end \\\n actions mirror vf id 3 / end\n\n flow create 0 ingress pattern vf id is 2 / end \\\n actions mirror vf id 3 / end\n or\n flow create 0 ingress pattern vf id is 1 id last 2 / end \\\n actions mirror vf id 3 / end\n or\n flow create 0 ingress pattern vf id mask 0x6 / end \\\n actions mirror vf id 3 / end\n7) ingress: vlan 4,6 => vf 3\n rx_vlan add 4 port 0 vf 0xf\n rx_vlan add 6 port 0 vf 0xf\n set port 0 mirror-rule 0 vlan-mirror 4,6 dst-pool 4 on\n or\n rx_vlan add 4 port 0 vf 0xf\n rx_vlan add 6 port 0 vf 0xf\n flow create 0 ingress pattern vlan vid is 4 / end \\\n actions mirror vf id 3 / end\n\n flow create 0 ingress pattern vlan vid is 6 / end \\\n actions mirror vf id 3 end\n or\n rx_vlan add 4 port 0 vf 0xf\n rx_vlan add 6 port 0 vf 0xf\n flow create 0 ingress pattern vlan vid mask 0x28 / end \\\n actions mirror vf id 3 / end\n or\n rx_vlan add 4 port 0 vf 0xf\n rx_vlan add 6 port 0 vf 0xf\n flow create 0 ingress pattern vlan vid is 4 vid \\\n last 6 vid mask 0x5 / end actions mirror vf id 3 / end\n\nSigned-off-by: Simon Lu <simonx.lu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_flow.c | 217 +++++++++++++++++++++++++++++++++\n 1 file changed, 217 insertions(+)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_flow.c b/drivers/net/ixgbe/ixgbe_flow.c\nindex 0b0e7c630..7670f6870 100644\n--- a/drivers/net/ixgbe/ixgbe_flow.c\n+++ b/drivers/net/ixgbe/ixgbe_flow.c\n@@ -117,6 +117,7 @@ static struct ixgbe_syn_filter_list filter_syn_list;\n static struct ixgbe_fdir_rule_filter_list filter_fdir_list;\n static struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;\n static struct ixgbe_rss_filter_list filter_rss_list;\n+static struct ixgbe_mirror_filter_list filter_mirror_list;\n static struct ixgbe_flow_mem_list ixgbe_flow_list;\n \n /**\n@@ -3170,6 +3171,172 @@ ixgbe_parse_mirror_filter(struct rte_eth_dev *dev,\n \treturn ixgbe_flow_parse_mirror_action(dev, actions, error, conf);\n }\n \n+static int\n+ixgbe_config_mirror_filter_add(struct rte_eth_dev *dev,\n+\t\t\t struct ixgbe_flow_mirror_conf *mirror_conf)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tuint32_t mr_ctl, vlvf;\n+\tuint32_t mp_lsb = 0;\n+\tuint32_t mv_msb = 0;\n+\tuint32_t mv_lsb = 0;\n+\tuint32_t mp_msb = 0;\n+\tuint8_t i = 0;\n+\tint reg_index = 0;\n+\tuint64_t vlan_mask = 0;\n+\n+\tconst uint8_t pool_mask_offset = 32;\n+\tconst uint8_t vlan_mask_offset = 32;\n+\tconst uint8_t dst_pool_offset = 8;\n+\tconst uint8_t rule_mr_offset = 4;\n+\tconst uint8_t mirror_rule_mask = 0x0F;\n+\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_filter_info *filter_info =\n+\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n+\tint8_t rule_id;\n+\tuint8_t mirror_type = 0;\n+\n+\tif (ixgbe_vt_check(hw) < 0)\n+\t\treturn -ENOTSUP;\n+\n+\tif (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {\n+\t\tPMD_DRV_LOG(ERR, \"unsupported mirror type 0x%x.\",\n+\t\t\t mirror_conf->rule_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trule_id = ixgbe_mirror_filter_insert(filter_info, mirror_conf);\n+\tif (rule_id < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"more than maximum mirror count(%d).\",\n+\t\t\t IXGBE_MAX_MIRROR_RULES);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VLAN) {\n+\t\tmirror_type |= IXGBE_MRCTL_VLME;\n+\t\t/* Check if vlan id is valid and find conresponding VLAN ID\n+\t\t * index in VLVF\n+\t\t */\n+\t\tfor (i = 0; i < pci_dev->max_vfs; i++)\n+\t\t\tif (mirror_conf->vlan_mask & (1ULL << i)) {\n+\t\t\t\t/* search vlan id related pool vlan filter\n+\t\t\t\t * index\n+\t\t\t\t */\n+\t\t\t\treg_index = ixgbe_find_vlvf_slot(hw,\n+\t\t\t\t\t\tmirror_conf->vlan_id[i],\n+\t\t\t\t\t\tfalse);\n+\t\t\t\tif (reg_index < 0)\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\tvlvf = IXGBE_READ_REG(hw,\n+\t\t\t\t\t\t IXGBE_VLVF(reg_index));\n+\t\t\t\tif ((vlvf & IXGBE_VLVF_VIEN) &&\n+\t\t\t\t ((vlvf & IXGBE_VLVF_VLANID_MASK) ==\n+\t\t\t\t mirror_conf->vlan_id[i])) {\n+\t\t\t\t\tvlan_mask |= (1ULL << reg_index);\n+\t\t\t\t} else {\n+\t\t\t\t\tixgbe_mirror_filter_remove(filter_info,\n+\t\t\t\t\t\tmirror_conf->rule_id);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\tmv_lsb = vlan_mask & 0xFFFFFFFF;\n+\t\tmv_msb = vlan_mask >> vlan_mask_offset;\n+\t}\n+\n+\t/**\n+\t * if enable pool mirror, write related pool mask register,if disable\n+\t * pool mirror, clear PFMRVM register\n+\t */\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {\n+\t\tmirror_type |= IXGBE_MRCTL_VPME;\n+\t\tmp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;\n+\t\tmp_msb = mirror_conf->pool_mask >> pool_mask_offset;\n+\t}\n+\tif (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)\n+\t\tmirror_type |= IXGBE_MRCTL_UPME;\n+\tif (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)\n+\t\tmirror_type |= IXGBE_MRCTL_DPME;\n+\n+\t/* read mirror control register and recalculate it */\n+\tmr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));\n+\tmr_ctl |= mirror_type;\n+\tmr_ctl &= mirror_rule_mask;\n+\tmr_ctl |= mirror_conf->dst_pool << dst_pool_offset;\n+\n+\t/* write mirrror control register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);\n+\n+\t/* write pool mirrror control register */\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),\n+\t\t\t\tmp_msb);\n+\t}\n+\t/* write VLAN mirrror control register */\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VLAN) {\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),\n+\t\t\t\tmv_msb);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* remove the mirror filter */\n+static int\n+ixgbe_config_mirror_filter_del(struct rte_eth_dev *dev,\n+\t\t\t struct ixgbe_flow_mirror_conf *conf)\n+{\n+\tstruct ixgbe_hw *hw =\n+\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_filter_info *filter_info =\n+\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n+\tuint8_t rule_id = conf->rule_id;\n+\tint mr_ctl = 0;\n+\tuint32_t lsb_val = 0;\n+\tuint32_t msb_val = 0;\n+\tconst uint8_t rule_mr_offset = 4;\n+\n+\tif (ixgbe_vt_check(hw) < 0)\n+\t\treturn -ENOTSUP;\n+\n+\tif (rule_id >= IXGBE_MAX_MIRROR_RULES)\n+\t\treturn -EINVAL;\n+\n+\t/* clear PFVMCTL register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);\n+\n+\t/* clear pool mask register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);\n+\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);\n+\n+\t/* clear vlan mask register */\n+\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);\n+\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);\n+\n+\tixgbe_mirror_filter_remove(filter_info, rule_id);\n+\treturn 0;\n+}\n+\n+static void\n+ixgbe_clear_all_mirror_filter(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_filter_info *filter_info =\n+\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n+\tint i;\n+\n+\tfor (i = 0; i < IXGBE_MAX_MIRROR_RULES; i++) {\n+\t\tif (filter_info->mirror_mask & (1 << i)) {\n+\t\t\tixgbe_config_mirror_filter_del(dev,\n+\t\t\t\t&filter_info->mirror_filters[i]);\n+\t\t}\n+\t}\n+}\n+\n void\n ixgbe_filterlist_init(void)\n {\n@@ -3179,6 +3346,7 @@ ixgbe_filterlist_init(void)\n \tTAILQ_INIT(&filter_fdir_list);\n \tTAILQ_INIT(&filter_l2_tunnel_list);\n \tTAILQ_INIT(&filter_rss_list);\n+\tTAILQ_INIT(&filter_mirror_list);\n \tTAILQ_INIT(&ixgbe_flow_list);\n }\n \n@@ -3192,6 +3360,7 @@ ixgbe_filterlist_flush(void)\n \tstruct ixgbe_fdir_rule_ele *fdir_rule_ptr;\n \tstruct ixgbe_flow_mem *ixgbe_flow_mem_ptr;\n \tstruct ixgbe_rss_conf_ele *rss_filter_ptr;\n+\tstruct ixgbe_mirror_conf_ele *mirror_filter_ptr;\n \n \twhile ((ntuple_filter_ptr = TAILQ_FIRST(&filter_ntuple_list))) {\n \t\tTAILQ_REMOVE(&filter_ntuple_list,\n@@ -3235,6 +3404,13 @@ ixgbe_filterlist_flush(void)\n \t\trte_free(rss_filter_ptr);\n \t}\n \n+\twhile ((mirror_filter_ptr = TAILQ_FIRST(&filter_mirror_list))) {\n+\t\tTAILQ_REMOVE(&filter_mirror_list,\n+\t\t\t mirror_filter_ptr,\n+\t\t\t entries);\n+\t\trte_free(mirror_filter_ptr);\n+\t}\n+\n \twhile ((ixgbe_flow_mem_ptr = TAILQ_FIRST(&ixgbe_flow_list))) {\n \t\tTAILQ_REMOVE(&ixgbe_flow_list,\n \t\t\t\t ixgbe_flow_mem_ptr,\n@@ -3266,6 +3442,7 @@ ixgbe_flow_create(struct rte_eth_dev *dev,\n \tstruct ixgbe_hw_fdir_info *fdir_info =\n \t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n \tstruct ixgbe_rte_flow_rss_conf rss_conf;\n+\tstruct ixgbe_flow_mirror_conf mirror_conf;\n \tstruct rte_flow *flow = NULL;\n \tstruct ixgbe_ntuple_filter_ele *ntuple_filter_ptr;\n \tstruct ixgbe_ethertype_filter_ele *ethertype_filter_ptr;\n@@ -3273,6 +3450,7 @@ ixgbe_flow_create(struct rte_eth_dev *dev,\n \tstruct ixgbe_eth_l2_tunnel_conf_ele *l2_tn_filter_ptr;\n \tstruct ixgbe_fdir_rule_ele *fdir_rule_ptr;\n \tstruct ixgbe_rss_conf_ele *rss_filter_ptr;\n+\tstruct ixgbe_mirror_conf_ele *mirror_filter_ptr;\n \tstruct ixgbe_flow_mem *ixgbe_flow_mem_ptr;\n \tuint8_t first_mask = FALSE;\n \n@@ -3495,6 +3673,32 @@ ixgbe_flow_create(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \n+\tmemset(&mirror_conf, 0, sizeof(struct ixgbe_flow_mirror_conf));\n+\tret = ixgbe_parse_mirror_filter(dev, attr, pattern,\n+\t\t\t\t actions, &mirror_conf, error);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"failed to parse mirror filter\");\n+\t\tgoto out;\n+\t}\n+\n+\tret = ixgbe_config_mirror_filter_add(dev, &mirror_conf);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"failed to add mirror filter\");\n+\t\tgoto out;\n+\t}\n+\n+\tmirror_filter_ptr = rte_zmalloc(\"ixgbe_mirror_filter\",\n+\t\t\t\tsizeof(struct ixgbe_mirror_conf_ele), 0);\n+\tif (!mirror_filter_ptr) {\n+\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n+\t\tgoto out;\n+\t}\n+\tmirror_filter_ptr->filter_info = mirror_conf;\n+\tTAILQ_INSERT_TAIL(&filter_mirror_list,\n+\t\t\t mirror_filter_ptr, entries);\n+\tflow->rule = mirror_filter_ptr;\n+\tflow->filter_type = RTE_ETH_FILTER_MIRROR;\n+\treturn flow;\n out:\n \tTAILQ_REMOVE(&ixgbe_flow_list,\n \t\tixgbe_flow_mem_ptr, entries);\n@@ -3586,6 +3790,7 @@ ixgbe_flow_destroy(struct rte_eth_dev *dev,\n \tstruct ixgbe_hw_fdir_info *fdir_info =\n \t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n \tstruct ixgbe_rss_conf_ele *rss_filter_ptr;\n+\tstruct ixgbe_mirror_conf_ele *mirror_filter_ptr;\n \n \tswitch (filter_type) {\n \tcase RTE_ETH_FILTER_NTUPLE:\n@@ -3665,6 +3870,17 @@ ixgbe_flow_destroy(struct rte_eth_dev *dev,\n \t\t\trte_free(rss_filter_ptr);\n \t\t}\n \t\tbreak;\n+\tcase RTE_ETH_FILTER_MIRROR:\n+\t\tmirror_filter_ptr = (struct ixgbe_mirror_conf_ele *)\n+\t\t\tpmd_flow->rule;\n+\t\tret = ixgbe_config_mirror_filter_del(dev,\n+\t\t\t\t\t&mirror_filter_ptr->filter_info);\n+\t\tif (!ret) {\n+\t\t\tTAILQ_REMOVE(&filter_mirror_list,\n+\t\t\t\tmirror_filter_ptr, entries);\n+\t\t\trte_free(mirror_filter_ptr);\n+\t\t}\n+\t\tbreak;\n \tdefault:\n \t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n \t\t\t filter_type);\n@@ -3717,6 +3933,7 @@ ixgbe_flow_flush(struct rte_eth_dev *dev,\n \t}\n \n \tixgbe_clear_rss_filter(dev);\n+\tixgbe_clear_all_mirror_filter(dev);\n \n \tixgbe_filterlist_flush();\n \n", "prefixes": [ "v1", "5/8" ] }