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GET /api/patches/80644/?format=api
{ "id": 80644, "url": "http://patches.dpdk.org/api/patches/80644/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201014055517.1214386-23-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201014055517.1214386-23-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201014055517.1214386-23-jiawenwu@trustnetic.com", "date": "2020-10-14T05:54:43", "name": "[v3,22/56] net/txgbe: add Rx and Tx start and stop", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6df36f3c6b3ebac91ec5a45fb41ab3561782fbae", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201014055517.1214386-23-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12938, "url": "http://patches.dpdk.org/api/series/12938/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12938", "date": "2020-10-14T05:54:22", "name": "net: txgbe PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/12938/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80644/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80644/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 034C4A04B7;\n\tWed, 14 Oct 2020 08:03:51 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D529B1DC9A;\n\tWed, 14 Oct 2020 07:54:46 +0200 (CEST)", "from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130])\n by dpdk.org (Postfix) with ESMTP id 7DD4B1DC52\n for <dev@dpdk.org>; Wed, 14 Oct 2020 07:54:33 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp10.qq.com (ESMTP) with\n id ; Wed, 14 Oct 2020 13:54:29 +0800 (CST)" ], "X-QQ-mid": "bizesmtp28t1602654869ta6vwuyj", "X-QQ-SSF": "01400000000000C0C000B00A0000000", "X-QQ-FEAT": "Ry58bBY793sVQOyqHMcicuvohh8nyWgDibBkWv6QBpvUB7zUbNaQP6fKvrFTH\n X9oXAoCTJ8lJbFttmIeAA1vfHulrKbbsgL9BEazzPpSwVCuP7f6aeOxKPkDF1XnbXjNfKMQ\n DXDH4fJsIKOjvYbvphTLwNYJxXWEMvlgHEP5Nh9h3G+UO0nPlNwXAvIW6v73d6bznBkeo5J\n 2fzNk6TJwW8SdGtL1t2fLaj2TPMFUSLYRPb1hg7/2B+btnX6kobyVLX/TY+dQvLqK4YoGTF\n put/Gcx3zjX0TkClayMwQJ009WsqpAnod2h8JYpnRBqwdrTKfKJoUpUm8pIgzra29GoxnyB\n uhu3ilJnvJlF8/l/V6MXTuAgNkIDw==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Wed, 14 Oct 2020 13:54:43 +0800", "Message-Id": "<20201014055517.1214386-23-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201014055517.1214386-1-jiawenwu@trustnetic.com>", "References": "<20201014055517.1214386-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign6", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v3 22/56] net/txgbe: add Rx and Tx start and stop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add receive and transmit units start and stop for specified queue.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n drivers/net/txgbe/base/txgbe_type.h | 3 +\n drivers/net/txgbe/txgbe_ethdev.c | 6 +\n drivers/net/txgbe/txgbe_ethdev.h | 15 ++\n drivers/net/txgbe/txgbe_rxtx.c | 256 ++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_rxtx.h | 12 ++\n 6 files changed, 293 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 707f64131..e76e9af46 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -7,6 +7,7 @@\n Speed capabilities = Y\n Link status = Y\n Link status event = Y\n+Queue start/stop = Y\n Jumbo frame = Y\n Scattered Rx = Y\n Unicast MAC filter = Y\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 747ada0f9..5237200d4 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -469,6 +469,9 @@ struct txgbe_hw {\n \t\tTXGBE_SW_RESET,\n \t\tTXGBE_GLOBAL_RESET\n \t} reset_type;\n+\n+\tu32 q_rx_regs[128 * 4];\n+\tu32 q_tx_regs[128 * 4];\n };\n \n #include \"txgbe_regs.h\"\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 6186cace1..dd13f73b2 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -566,6 +566,8 @@ txgbe_dev_close(struct rte_eth_dev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\ttxgbe_dev_free_queues(dev);\n+\n \tdev->dev_ops = NULL;\n \n \t/* disable uio intr before callback unregister */\n@@ -1322,6 +1324,10 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.dev_infos_get = txgbe_dev_info_get,\n \t.dev_set_link_up = txgbe_dev_set_link_up,\n \t.dev_set_link_down = txgbe_dev_set_link_down,\n+\t.rx_queue_start\t = txgbe_dev_rx_queue_start,\n+\t.rx_queue_stop = txgbe_dev_rx_queue_stop,\n+\t.tx_queue_start\t = txgbe_dev_tx_queue_start,\n+\t.tx_queue_stop = txgbe_dev_tx_queue_stop,\n \t.rx_queue_setup = txgbe_dev_rx_queue_setup,\n \t.rx_queue_release = txgbe_dev_rx_queue_release,\n \t.tx_queue_setup = txgbe_dev_tx_queue_setup,\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex 6636b6e9a..1a29281a8 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -80,6 +80,8 @@ struct txgbe_adapter {\n /*\n * RX/TX function prototypes\n */\n+void txgbe_dev_free_queues(struct rte_eth_dev *dev);\n+\n void txgbe_dev_rx_queue_release(void *rxq);\n \n void txgbe_dev_tx_queue_release(void *txq);\n@@ -97,6 +99,19 @@ int txgbe_dev_rx_init(struct rte_eth_dev *dev);\n \n void txgbe_dev_tx_init(struct rte_eth_dev *dev);\n \n+void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);\n+void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);\n+void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);\n+void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);\n+\n+int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n+int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+\n+int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n+int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,\n \t\t\t uint8_t queue, uint8_t msix_vector);\n \ndiff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c\nindex 707d5b2e4..d6ba1545c 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.c\n+++ b/drivers/net/txgbe/txgbe_rxtx.c\n@@ -10,6 +10,9 @@\n #include <errno.h>\n \n #include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_log.h>\n+#include <rte_debug.h>\n #include <rte_ethdev.h>\n #include <rte_ethdev_driver.h>\n #include <rte_memzone.h>\n@@ -622,12 +625,64 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+void\n+txgbe_dev_free_queues(struct rte_eth_dev *dev)\n+{\n+\tunsigned int i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\ttxgbe_dev_rx_queue_release(dev->data->rx_queues[i]);\n+\t\tdev->data->rx_queues[i] = NULL;\n+\t}\n+\tdev->data->nb_rx_queues = 0;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxgbe_dev_tx_queue_release(dev->data->tx_queues[i]);\n+\t\tdev->data->tx_queues[i] = NULL;\n+\t}\n+\tdev->data->nb_tx_queues = 0;\n+}\n+\n void __rte_cold\n txgbe_set_rx_function(struct rte_eth_dev *dev)\n {\n \tRTE_SET_USED(dev);\n }\n \n+static int __rte_cold\n+txgbe_alloc_rx_queue_mbufs(struct txgbe_rx_queue *rxq)\n+{\n+\tstruct txgbe_rx_entry *rxe = rxq->sw_ring;\n+\tuint64_t dma_addr;\n+\tunsigned int i;\n+\n+\t/* Initialize software ring entries */\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tvolatile struct txgbe_rx_desc *rxd;\n+\t\tstruct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);\n+\n+\t\tif (mbuf == NULL) {\n+\t\t\tPMD_INIT_LOG(ERR, \"RX mbuf alloc failed queue_id=%u\",\n+\t\t\t\t (unsigned int)rxq->queue_id);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\tmbuf->port = rxq->port_id;\n+\n+\t\tdma_addr =\n+\t\t\trte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));\n+\t\trxd = &rxq->rx_ring[i];\n+\t\tTXGBE_RXD_HDRADDR(rxd, 0);\n+\t\tTXGBE_RXD_PKTADDR(rxd, dma_addr);\n+\t\trxe[i].mbuf = mbuf;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * txgbe_get_rscctl_maxdesc\n *\n@@ -958,3 +1013,204 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)\n \t}\n }\n \n+void\n+txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id)\n+{\n+\tu32 *reg = &hw->q_rx_regs[rx_queue_id * 8];\n+\t*(reg++) = rd32(hw, TXGBE_RXBAL(rx_queue_id));\n+\t*(reg++) = rd32(hw, TXGBE_RXBAH(rx_queue_id));\n+\t*(reg++) = rd32(hw, TXGBE_RXCFG(rx_queue_id));\n+}\n+\n+void\n+txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id)\n+{\n+\tu32 *reg = &hw->q_rx_regs[rx_queue_id * 8];\n+\twr32(hw, TXGBE_RXBAL(rx_queue_id), *(reg++));\n+\twr32(hw, TXGBE_RXBAH(rx_queue_id), *(reg++));\n+\twr32(hw, TXGBE_RXCFG(rx_queue_id), *(reg++) & ~TXGBE_RXCFG_ENA);\n+}\n+\n+void\n+txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id)\n+{\n+\tu32 *reg = &hw->q_tx_regs[tx_queue_id * 8];\n+\t*(reg++) = rd32(hw, TXGBE_TXBAL(tx_queue_id));\n+\t*(reg++) = rd32(hw, TXGBE_TXBAH(tx_queue_id));\n+\t*(reg++) = rd32(hw, TXGBE_TXCFG(tx_queue_id));\n+}\n+\n+void\n+txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id)\n+{\n+\tu32 *reg = &hw->q_tx_regs[tx_queue_id * 8];\n+\twr32(hw, TXGBE_TXBAL(tx_queue_id), *(reg++));\n+\twr32(hw, TXGBE_TXBAH(tx_queue_id), *(reg++));\n+\twr32(hw, TXGBE_TXCFG(tx_queue_id), *(reg++) & ~TXGBE_TXCFG_ENA);\n+}\n+\n+/*\n+ * Start Receive Units for specified queue.\n+ */\n+int __rte_cold\n+txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_rx_queue *rxq;\n+\tuint32_t rxdctl;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\t/* Allocate buffers for descriptor rings */\n+\tif (txgbe_alloc_rx_queue_mbufs(rxq) != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Could not alloc mbuf for queue:%d\",\n+\t\t\t rx_queue_id);\n+\t\treturn -1;\n+\t}\n+\trxdctl = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));\n+\trxdctl |= TXGBE_RXCFG_ENA;\n+\twr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxdctl);\n+\n+\t/* Wait until RX Enable ready */\n+\tpoll_ms = RTE_TXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\trxdctl = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));\n+\t} while (--poll_ms && !(rxdctl & TXGBE_RXCFG_ENA));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not enable Rx Queue %d\", rx_queue_id);\n+\trte_wmb();\n+\twr32(hw, TXGBE_RXRP(rxq->reg_idx), 0);\n+\twr32(hw, TXGBE_RXWP(rxq->reg_idx), rxq->nb_rx_desc - 1);\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Stop Receive Units for specified queue.\n+ */\n+int __rte_cold\n+txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\tstruct txgbe_rx_queue *rxq;\n+\tuint32_t rxdctl;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\ttxgbe_dev_save_rx_queue(hw, rxq->reg_idx);\n+\twr32m(hw, TXGBE_RXCFG(rxq->reg_idx), TXGBE_RXCFG_ENA, 0);\n+\n+\t/* Wait until RX Enable bit clear */\n+\tpoll_ms = RTE_TXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\trxdctl = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));\n+\t} while (--poll_ms && (rxdctl & TXGBE_RXCFG_ENA));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not disable Rx Queue %d\", rx_queue_id);\n+\n+\trte_delay_us(RTE_TXGBE_WAIT_100_US);\n+\ttxgbe_dev_store_rx_queue(hw, rxq->reg_idx);\n+\n+\ttxgbe_rx_queue_release_mbufs(rxq);\n+\ttxgbe_reset_rx_queue(adapter, rxq);\n+\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Start Transmit Units for specified queue.\n+ */\n+int __rte_cold\n+txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_tx_queue *txq;\n+\tuint32_t txdctl;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\twr32m(hw, TXGBE_TXCFG(txq->reg_idx), TXGBE_TXCFG_ENA, TXGBE_TXCFG_ENA);\n+\n+\t/* Wait until TX Enable ready */\n+\tpoll_ms = RTE_TXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\ttxdctl = rd32(hw, TXGBE_TXCFG(txq->reg_idx));\n+\t} while (--poll_ms && !(txdctl & TXGBE_TXCFG_ENA));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not enable \"\n+\t\t\t \"Tx Queue %d\", tx_queue_id);\n+\n+\trte_wmb();\n+\twr32(hw, TXGBE_TXWP(txq->reg_idx), txq->tx_tail);\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Stop Transmit Units for specified queue.\n+ */\n+int __rte_cold\n+txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_tx_queue *txq;\n+\tuint32_t txdctl;\n+\tuint32_t txtdh, txtdt;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\t/* Wait until TX queue is empty */\n+\tpoll_ms = RTE_TXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_us(RTE_TXGBE_WAIT_100_US);\n+\t\ttxtdh = rd32(hw, TXGBE_TXRP(txq->reg_idx));\n+\t\ttxtdt = rd32(hw, TXGBE_TXWP(txq->reg_idx));\n+\t} while (--poll_ms && (txtdh != txtdt));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"Tx Queue %d is not empty when stopping.\",\n+\t\t\ttx_queue_id);\n+\n+\ttxgbe_dev_save_tx_queue(hw, txq->reg_idx);\n+\twr32m(hw, TXGBE_TXCFG(txq->reg_idx), TXGBE_TXCFG_ENA, 0);\n+\n+\t/* Wait until TX Enable bit clear */\n+\tpoll_ms = RTE_TXGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\ttxdctl = rd32(hw, TXGBE_TXCFG(txq->reg_idx));\n+\t} while (--poll_ms && (txdctl & TXGBE_TXCFG_ENA));\n+\tif (!poll_ms)\n+\t\tPMD_INIT_LOG(ERR, \"Could not disable Tx Queue %d\",\n+\t\t\ttx_queue_id);\n+\n+\trte_delay_us(RTE_TXGBE_WAIT_100_US);\n+\ttxgbe_dev_store_tx_queue(hw, txq->reg_idx);\n+\n+\tif (txq->ops != NULL) {\n+\t\ttxq->ops->release_mbufs(txq);\n+\t\ttxq->ops->reset(txq);\n+\t}\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\ndiff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h\nindex be165dd19..5b991e304 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.h\n+++ b/drivers/net/txgbe/txgbe_rxtx.h\n@@ -42,6 +42,14 @@ struct txgbe_rx_desc {\n \t} qw1; /* also as r.hdr_addr */\n };\n \n+/* @txgbe_rx_desc.qw0 */\n+#define TXGBE_RXD_PKTADDR(rxd, v) \\\n+\t(((volatile __le64 *)(rxd))[0] = cpu_to_le64(v))\n+\n+/* @txgbe_rx_desc.qw1 */\n+#define TXGBE_RXD_HDRADDR(rxd, v) \\\n+\t(((volatile __le64 *)(rxd))[1] = cpu_to_le64(v))\n+\n /**\n * Transmit Data Descriptor (TXGBE_TXD_TYP=DATA)\n **/\n@@ -59,6 +67,9 @@ struct txgbe_tx_desc {\n \n #define TXGBE_PTID_MASK 0xFF\n \n+#define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS 10\n+#define RTE_TXGBE_WAIT_100_US 100\n+\n #define TXGBE_TX_MAX_SEG 40\n \n /**\n@@ -140,6 +151,7 @@ struct txgbe_tx_queue {\n \tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n \tvolatile uint32_t *tdc_reg_addr; /**< Address of TDC register. */\n \tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n+\tuint16_t tx_tail; /**< current value of TDT reg. */\n \t/**< Start freeing TX buffers if there are less free descriptors than\n \t * this value.\n \t */\n", "prefixes": [ "v3", "22/56" ] }