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GET /api/patches/80162/?format=api
{ "id": 80162, "url": "http://patches.dpdk.org/api/patches/80162/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201009123919.43004-6-savinay.dharmappa@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201009123919.43004-6-savinay.dharmappa@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201009123919.43004-6-savinay.dharmappa@intel.com", "date": "2020-10-09T12:39:16", "name": "[v9,5/8] example/ip_pipeline: update subport rate dynamically", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5514a43750eae0201bea114dc9d0073439c60445", "submitter": { "id": 1535, "url": "http://patches.dpdk.org/api/people/1535/?format=api", "name": "Savinay Dharmappa", "email": "savinay.dharmappa@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201009123919.43004-6-savinay.dharmappa@intel.com/mbox/", "series": [ { "id": 12825, "url": "http://patches.dpdk.org/api/series/12825/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12825", "date": "2020-10-09T12:39:11", "name": "Enable dynamic config of subport bandwidth", "version": 9, "mbox": "http://patches.dpdk.org/series/12825/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80162/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80162/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DFEE8A04BC;\n\tFri, 9 Oct 2020 14:41:30 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 70D991D642;\n\tFri, 9 Oct 2020 14:39:45 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 2506E1D628\n for <dev@dpdk.org>; Fri, 9 Oct 2020 14:39:39 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Oct 2020 05:39:38 -0700", "from silpixa00400629.ir.intel.com ([10.237.214.112])\n by orsmga005.jf.intel.com with ESMTP; 09 Oct 2020 05:39:36 -0700" ], "IronPort-SDR": [ "\n iFzt5gF/t2JAsRczcLXTGvaRNV3DZraotGP2kII0EjxXxBWeojx6om0RJgQ4GtmbM036dSJ0TE\n uT+k/X+viXsw==", "\n mt5mauuSkxswxtYeg9xdmIdP+gfblaiLyaCre4TxKYUVAd4R6LBZaAIER08Opsv9/HiOMrYsUg\n C+B43DM4TCIw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9768\"; a=\"152397587\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"152397587\"", "E=Sophos;i=\"5.77,355,1596524400\"; d=\"scan'208\";a=\"528914530\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Savinay Dharmappa <savinay.dharmappa@intel.com>", "To": "cristian.dumitrescu@intel.com,\n\tjasvinder.singh@intel.com,\n\tdev@dpdk.org", "Cc": "savinay.dharmappa@intel.com", "Date": "Fri, 9 Oct 2020 13:39:16 +0100", "Message-Id": "<20201009123919.43004-6-savinay.dharmappa@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201009123919.43004-1-savinay.dharmappa@intel.com>", "References": "<20201007140915.19491-1-savinay.dharmappa@intel.com>\n <20201009123919.43004-1-savinay.dharmappa@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 5/8] example/ip_pipeline: update subport rate\n\tdynamically", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Modify the ip_pipeline application to build the hierarchical scheduler\nwith default subport bandwidth profile. It also allows to update\na subport with different subport rates dynamically\n\nSigned-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>\n---\n examples/ip_pipeline/cli.c | 68 ++++++++------------\n examples/ip_pipeline/tmgr.c | 121 ++++++++++++++++++++++++++++++------\n examples/ip_pipeline/tmgr.h | 5 +-\n 3 files changed, 134 insertions(+), 60 deletions(-)", "diff": "diff --git a/examples/ip_pipeline/cli.c b/examples/ip_pipeline/cli.c\nindex dafc95ae9..ec4acf0ac 100644\n--- a/examples/ip_pipeline/cli.c\n+++ b/examples/ip_pipeline/cli.c\n@@ -393,12 +393,7 @@ static const char cmd_tmgr_subport_profile_help[] =\n \" <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate> <tc4_rate>\"\n \" <tc5_rate> <tc6_rate> <tc7_rate> <tc8_rate>\"\n \" <tc9_rate> <tc10_rate> <tc11_rate> <tc12_rate>\\n\"\n-\" <tc_period>\\n\"\n-\" pps <n_pipes_per_subport>\\n\"\n-\" qsize <qsize_tc0> <qsize_tc1> <qsize_tc2>\"\n-\" <qsize_tc3> <qsize_tc4> <qsize_tc5> <qsize_tc6>\"\n-\" <qsize_tc7> <qsize_tc8> <qsize_tc9> <qsize_tc10>\"\n-\" <qsize_tc11> <qsize_tc12>\";\n+\" <tc_period>\\n\";\n \n static void\n cmd_tmgr_subport_profile(char **tokens,\n@@ -406,57 +401,37 @@ cmd_tmgr_subport_profile(char **tokens,\n \tchar *out,\n \tsize_t out_size)\n {\n-\tstruct rte_sched_subport_params p;\n+\tstruct rte_sched_subport_profile_params subport_profile;\n \tint status, i;\n \n-\tif (n_tokens != 35) {\n+\tif (n_tokens != 19) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint64(&p.tb_rate, tokens[3]) != 0) {\n+\tif (parser_read_uint64(&subport_profile.tb_rate, tokens[3]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tb_rate\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint64(&p.tb_size, tokens[4]) != 0) {\n+\tif (parser_read_uint64(&subport_profile.tb_size, tokens[4]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tb_size\");\n \t\treturn;\n \t}\n \n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tif (parser_read_uint64(&p.tc_rate[i], tokens[5 + i]) != 0) {\n+\t\tif (parser_read_uint64(&subport_profile.tc_rate[i],\n+\t\t\t\ttokens[5 + i]) != 0) {\n \t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tc_rate\");\n \t\t\treturn;\n \t\t}\n \n-\tif (parser_read_uint64(&p.tc_period, tokens[18]) != 0) {\n+\tif (parser_read_uint64(&subport_profile.tc_period, tokens[18]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tc_period\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[19], \"pps\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pps\");\n-\t\treturn;\n-\t}\n-\n-\tif (parser_read_uint32(&p.n_pipes_per_subport_enabled, tokens[20]) != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_pipes_per_subport\");\n-\t\treturn;\n-\t}\n-\n-\tif (strcmp(tokens[21], \"qsize\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"qsize\");\n-\t\treturn;\n-\t}\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tif (parser_read_uint16(&p.qsize[i], tokens[22 + i]) != 0) {\n-\t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"qsize\");\n-\t\t\treturn;\n-\t\t}\n-\n-\tstatus = tmgr_subport_profile_add(&p);\n+\tstatus = tmgr_subport_profile_add(&subport_profile);\n \tif (status != 0) {\n \t\tsnprintf(out, out_size, MSG_CMD_FAIL, tokens[0]);\n \t\treturn;\n@@ -530,6 +505,7 @@ static const char cmd_tmgr_help[] =\n \"tmgr <tmgr_name>\\n\"\n \" rate <rate>\\n\"\n \" spp <n_subports_per_port>\\n\"\n+\" pps <n_pipes_per_subport>\\n\"\n \" fo <frame_overhead>\\n\"\n \" mtu <mtu>\\n\"\n \" cpu <cpu_id>\\n\";\n@@ -544,7 +520,7 @@ cmd_tmgr(char **tokens,\n \tchar *name;\n \tstruct tmgr_port *tmgr_port;\n \n-\tif (n_tokens != 12) {\n+\tif (n_tokens != 14) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -571,32 +547,42 @@ cmd_tmgr(char **tokens,\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[6], \"fo\") != 0) {\n+\tif (strcmp(tokens[6], \"pps\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"spp\");\n+\t\treturn;\n+\t}\n+\n+\tif (parser_read_uint32(&p.n_pipes_per_subport, tokens[7]) != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_pipes_per_subport\");\n+\t\treturn;\n+\t}\n+\n+\tif (strcmp(tokens[8], \"fo\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"fo\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.frame_overhead, tokens[7]) != 0) {\n+\tif (parser_read_uint32(&p.frame_overhead, tokens[9]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"frame_overhead\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[8], \"mtu\") != 0) {\n+\tif (strcmp(tokens[10], \"mtu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.mtu, tokens[9]) != 0) {\n+\tif (parser_read_uint32(&p.mtu, tokens[11]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[10], \"cpu\") != 0) {\n+\tif (strcmp(tokens[12], \"cpu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"cpu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.cpu_id, tokens[11]) != 0) {\n+\tif (parser_read_uint32(&p.cpu_id, tokens[13]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"cpu_id\");\n \t\treturn;\n \t}\ndiff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c\nindex 46c6a83a4..e4e364cbc 100644\n--- a/examples/ip_pipeline/tmgr.c\n+++ b/examples/ip_pipeline/tmgr.c\n@@ -4,11 +4,12 @@\n \n #include <stdlib.h>\n \n+#include <rte_common.h>\n #include <rte_string_fns.h>\n \n #include \"tmgr.h\"\n \n-static struct rte_sched_subport_params\n+static struct rte_sched_subport_profile_params\n \tsubport_profile[TMGR_SUBPORT_PROFILE_MAX];\n \n static uint32_t n_subport_profiles;\n@@ -18,6 +19,82 @@ static struct rte_sched_pipe_params\n \n static uint32_t n_pipe_profiles;\n \n+static const struct rte_sched_subport_params subport_params_default = {\n+\t.n_pipes_per_subport_enabled = 0, /* filled at runtime */\n+\t.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},\n+\t.pipe_profiles = pipe_profile,\n+\t.n_pipe_profiles = 0, /* filled at run time */\n+\t.n_max_pipe_profiles = RTE_DIM(pipe_profile),\n+#ifdef RTE_SCHED_RED\n+.red_params = {\n+\t/* Traffic Class 0 Colors Green / Yellow / Red */\n+\t[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 1 - Colors Green / Yellow / Red */\n+\t[1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 2 - Colors Green / Yellow / Red */\n+\t[2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 3 - Colors Green / Yellow / Red */\n+\t[3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 4 - Colors Green / Yellow / Red */\n+\t[4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 5 - Colors Green / Yellow / Red */\n+\t[5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 6 - Colors Green / Yellow / Red */\n+\t[6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 7 - Colors Green / Yellow / Red */\n+\t[7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 8 - Colors Green / Yellow / Red */\n+\t[8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 9 - Colors Green / Yellow / Red */\n+\t[9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 10 - Colors Green / Yellow / Red */\n+\t[10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 11 - Colors Green / Yellow / Red */\n+\t[11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\n+\t/* Traffic Class 12 - Colors Green / Yellow / Red */\n+\t[12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n+\t},\n+#endif /* RTE_SCHED_RED */\n+};\n+\n static struct tmgr_port_list tmgr_port_list;\n \n int\n@@ -44,17 +121,16 @@ tmgr_port_find(const char *name)\n }\n \n int\n-tmgr_subport_profile_add(struct rte_sched_subport_params *p)\n+tmgr_subport_profile_add(struct rte_sched_subport_profile_params *params)\n {\n \t/* Check input params */\n-\tif (p == NULL ||\n-\t\tp->n_pipes_per_subport_enabled == 0)\n+\tif (params == NULL)\n \t\treturn -1;\n \n \t/* Save profile */\n \tmemcpy(&subport_profile[n_subport_profiles],\n-\t\tp,\n-\t\tsizeof(*p));\n+\t\tparams,\n+\t\tsizeof(*params));\n \n \tn_subport_profiles++;\n \n@@ -81,6 +157,7 @@ tmgr_pipe_profile_add(struct rte_sched_pipe_params *p)\n struct tmgr_port *\n tmgr_port_create(const char *name, struct tmgr_port_params *params)\n {\n+\tstruct rte_sched_subport_params subport_params;\n \tstruct rte_sched_port_params p;\n \tstruct tmgr_port *tmgr_port;\n \tstruct rte_sched_port *s;\n@@ -91,6 +168,7 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\ttmgr_port_find(name) ||\n \t\t(params == NULL) ||\n \t\t(params->n_subports_per_port == 0) ||\n+\t\t(params->n_pipes_per_subport == 0) ||\n \t\t(params->cpu_id >= RTE_MAX_NUMA_NODES) ||\n \t\t(n_subport_profiles == 0) ||\n \t\t(n_pipe_profiles == 0))\n@@ -103,15 +181,22 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tp.mtu = params->mtu;\n \tp.frame_overhead = params->frame_overhead;\n \tp.n_subports_per_port = params->n_subports_per_port;\n-\tp.n_pipes_per_subport = TMGR_PIPE_SUBPORT_MAX;\n+\tp.n_subport_profiles = n_subport_profiles;\n+\tp.subport_profiles = subport_profile;\n+\tp.n_max_subport_profiles = TMGR_SUBPORT_PROFILE_MAX;\n+\tp.n_pipes_per_subport = params->n_pipes_per_subport;\n+\n \n \ts = rte_sched_port_config(&p);\n \tif (s == NULL)\n \t\treturn NULL;\n \n-\tsubport_profile[0].pipe_profiles = pipe_profile;\n-\tsubport_profile[0].n_pipe_profiles = n_pipe_profiles;\n-\tsubport_profile[0].n_max_pipe_profiles = TMGR_PIPE_PROFILE_MAX;\n+\tmemcpy(&subport_params, &subport_params_default,\n+\t\tsizeof(subport_params_default));\n+\n+\tsubport_params.n_pipe_profiles = n_pipe_profiles;\n+\tsubport_params.n_pipes_per_subport_enabled =\n+\t\t\t\t\t\tparams->n_pipes_per_subport;\n \n \tfor (i = 0; i < params->n_subports_per_port; i++) {\n \t\tint status;\n@@ -119,7 +204,7 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\tstatus = rte_sched_subport_config(\n \t\t\ts,\n \t\t\ti,\n-\t\t\t&subport_profile[0],\n+\t\t\t&subport_params,\n \t\t\t0);\n \n \t\tif (status) {\n@@ -127,7 +212,8 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\t\treturn NULL;\n \t\t}\n \n-\t\tfor (j = 0; j < subport_profile[0].n_pipes_per_subport_enabled; j++) {\n+\t\tfor (j = 0; j < params->n_pipes_per_subport; j++) {\n+\n \t\t\tstatus = rte_sched_pipe_config(\n \t\t\t\ts,\n \t\t\t\ti,\n@@ -152,6 +238,7 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tstrlcpy(tmgr_port->name, name, sizeof(tmgr_port->name));\n \ttmgr_port->s = s;\n \ttmgr_port->n_subports_per_port = params->n_subports_per_port;\n+\ttmgr_port->n_pipes_per_subport = params->n_pipes_per_subport;\n \n \t/* Node add to list */\n \tTAILQ_INSERT_TAIL(&tmgr_port_list, tmgr_port, node);\n@@ -181,8 +268,8 @@ tmgr_subport_config(const char *port_name,\n \tstatus = rte_sched_subport_config(\n \t\tport->s,\n \t\tsubport_id,\n-\t\t&subport_profile[subport_profile_id],\n-\t\t0);\n+\t\tNULL,\n+\t\tsubport_profile_id);\n \n \treturn status;\n }\n@@ -204,10 +291,8 @@ tmgr_pipe_config(const char *port_name,\n \tport = tmgr_port_find(port_name);\n \tif ((port == NULL) ||\n \t\t(subport_id >= port->n_subports_per_port) ||\n-\t\t(pipe_id_first >=\n-\t\t\tsubport_profile[subport_id].n_pipes_per_subport_enabled) ||\n-\t\t(pipe_id_last >=\n-\t\t\tsubport_profile[subport_id].n_pipes_per_subport_enabled) ||\n+\t\t(pipe_id_first >= port->n_pipes_per_subport) ||\n+\t\t(pipe_id_last >= port->n_pipes_per_subport) ||\n \t\t(pipe_id_first > pipe_id_last) ||\n \t\t(pipe_profile_id >= n_pipe_profiles))\n \t\treturn -1;\ndiff --git a/examples/ip_pipeline/tmgr.h b/examples/ip_pipeline/tmgr.h\nindex ee50cf7cc..1994c55bc 100644\n--- a/examples/ip_pipeline/tmgr.h\n+++ b/examples/ip_pipeline/tmgr.h\n@@ -9,6 +9,7 @@\n #include <sys/queue.h>\n \n #include <rte_sched.h>\n+#include <rte_red.h>\n \n #include \"common.h\"\n \n@@ -29,6 +30,7 @@ struct tmgr_port {\n \tchar name[NAME_SIZE];\n \tstruct rte_sched_port *s;\n \tuint32_t n_subports_per_port;\n+\tuint32_t n_pipes_per_subport;\n };\n \n TAILQ_HEAD(tmgr_port_list, tmgr_port);\n@@ -42,13 +44,14 @@ tmgr_port_find(const char *name);\n struct tmgr_port_params {\n \tuint64_t rate;\n \tuint32_t n_subports_per_port;\n+\tuint32_t n_pipes_per_subport;\n \tuint32_t frame_overhead;\n \tuint32_t mtu;\n \tuint32_t cpu_id;\n };\n \n int\n-tmgr_subport_profile_add(struct rte_sched_subport_params *p);\n+tmgr_subport_profile_add(struct rte_sched_subport_profile_params *sp);\n \n int\n tmgr_pipe_profile_add(struct rte_sched_pipe_params *p);\n", "prefixes": [ "v9", "5/8" ] }