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GET /api/patches/80034/?format=api
{ "id": 80034, "url": "http://patches.dpdk.org/api/patches/80034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201008103435.19187-4-adwivedi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201008103435.19187-4-adwivedi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201008103435.19187-4-adwivedi@marvell.com", "date": "2020-10-08T10:34:35", "name": "[v4,3/3] event/octeontx2: add crypto adapter datapath", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f8dec00c446dc28300117a7881ceb2df45259cd3", "submitter": { "id": 1561, "url": "http://patches.dpdk.org/api/people/1561/?format=api", "name": "Ankur Dwivedi", "email": "adwivedi@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201008103435.19187-4-adwivedi@marvell.com/mbox/", "series": [ { "id": 12775, "url": "http://patches.dpdk.org/api/series/12775/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12775", "date": "2020-10-08T10:34:32", "name": "event/octeontx2: add support for event crypto adapter", "version": 4, "mbox": "http://patches.dpdk.org/series/12775/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80034/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/80034/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7CE81A04BC;\n\tThu, 8 Oct 2020 12:35:50 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D4FDA1BF33;\n\tThu, 8 Oct 2020 12:35:12 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 92BBC1BF33\n for <dev@dpdk.org>; Thu, 8 Oct 2020 12:35:10 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 098AUIwB024748; Thu, 8 Oct 2020 03:35:08 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0a-0016f401.pphosted.com with ESMTP id 33xpnq0duh-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 08 Oct 2020 03:35:08 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 8 Oct 2020 03:35:07 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 8 Oct 2020 03:35:07 -0700", "from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13])\n by maili.marvell.com (Postfix) with ESMTP id 9E3853F703F;\n Thu, 8 Oct 2020 03:35:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=8XGkzARvFyxaej/HcV841k5s+11yvPE8dd2Yfx436LM=;\n b=MupNEumZFlFzhX75LmHdfd9ZufJn0u5T38Sz/OwuFHoo8nmNpsP93uSN2r0hHUDjzTU2\n Ge5OA9Ml+mRmhxFxuONANZuBbBgU/UvzTSdJ7GTLN5oWQFqqpWy6q9/l78tXfCuL6Z7R\n VPOrsdYT0WEoAiqgHgnSWLb3sUupcvPVTLtuQgreSg70XRJuT2wrsQjJEZq88kPOPZx/\n zRoGPyffwB18XhTbTSuEgZIywAkhaUfKZYYViWdugTRPiT5vwDYiY7lD0ZbBTfoIontV\n tOc+q2UMzkK5VsrPViqiNctP9dHGoUzWXtJ4Xi/XYn42ZeWkh/Tru3iEp3F7i1g2Xktr aQ==", "From": "Ankur Dwivedi <adwivedi@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <pbhagavatula@marvell.com>, <akhil.goyal@nxp.com>,\n <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>", "Date": "Thu, 8 Oct 2020 16:04:35 +0530", "Message-ID": "<20201008103435.19187-4-adwivedi@marvell.com>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20201008103435.19187-1-adwivedi@marvell.com>", "References": "<20201008055423.32259-1-adwivedi@marvell.com>\n <20201008103435.19187-1-adwivedi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-10-08_04:2020-10-08,\n 2020-10-08 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 3/3] event/octeontx2: add crypto adapter\n\tdatapath", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In the op new mode of crypto adapter, the completed crypto operation\nis submitted to the event device by the OCTEON TX2 crypto PMD.\nDuring event device dequeue the result of crypto operation is checked.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\n---\n drivers/common/cpt/cpt_common.h | 1 +\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 47 ++++++++++++\n .../rte_pmd_octeontx2_crypto_version.map | 1 +\n .../octeontx2/otx2_evdev_crypto_adptr_dp.h | 75 +++++++++++++++++++\n drivers/event/octeontx2/otx2_worker.h | 28 ++++---\n drivers/event/octeontx2/otx2_worker_dual.h | 44 ++++++-----\n 6 files changed, 168 insertions(+), 28 deletions(-)\n create mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nindex 0141b2aed..1ce28e90b 100644\n--- a/drivers/common/cpt/cpt_common.h\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -72,6 +72,7 @@ struct cpt_request_info {\n \t\tuint64_t ei3;\n \t} ist;\n \tuint8_t *rptr;\n+\tconst struct otx2_cpt_qp *qp;\n \n \t/** Control path fields */\n \tuint64_t time_out;\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 027fd0d47..9125369d3 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -417,6 +417,48 @@ sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,\n \treturn -ENOTSUP;\n }\n \n+static __rte_always_inline void __rte_hot\n+otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n+\t\t struct cpt_request_info *req,\n+\t\t void *lmtline)\n+{\n+\tunion cpt_inst_s inst;\n+\tuint64_t lmt_status;\n+\n+\tinst.u[0] = 0;\n+\tinst.s9x.res_addr = req->comp_baddr;\n+\tinst.u[2] = 0;\n+\tinst.u[3] = 0;\n+\n+\tinst.s9x.ei0 = req->ist.ei0;\n+\tinst.s9x.ei1 = req->ist.ei1;\n+\tinst.s9x.ei2 = req->ist.ei2;\n+\tinst.s9x.ei3 = req->ist.ei3;\n+\n+\tinst.s9x.qord = 1;\n+\tinst.s9x.grp = qp->ev.queue_id;\n+\tinst.s9x.tt = qp->ev.sched_type;\n+\tinst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |\n+\t\t\tqp->ev.flow_id;\n+\tinst.s9x.wq_ptr = (uint64_t)req >> 3;\n+\treq->qp = qp;\n+\n+\tdo {\n+\t\t/* Copy CPT command to LMTLINE */\n+\t\tmemcpy(lmtline, &inst, sizeof(inst));\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_io_wmb();\n+\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n+\t} while (lmt_status == 0);\n+\n+}\n+\n static __rte_always_inline int32_t __rte_hot\n otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\t struct pending_queue *pend_q,\n@@ -426,6 +468,11 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \tunion cpt_inst_s inst;\n \tuint64_t lmt_status;\n \n+\tif (qp->ca_enable) {\n+\t\totx2_ca_enqueue_req(qp, req, lmtline);\n+\t\treturn 0;\n+\t}\n+\n \tif (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))\n \t\treturn -EAGAIN;\n \ndiff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\nindex 95ebda255..02684781b 100644\n--- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n@@ -5,6 +5,7 @@ DPDK_21 {\n INTERNAL {\n \tglobal:\n \n+\totx2_cryptodev_driver_id;\n \totx2_cpt_af_reg_read;\n \totx2_cpt_af_reg_write;\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h\nnew file mode 100644\nindex 000000000..70b63933e\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h\n@@ -0,0 +1,75 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_\n+#define _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_\n+\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_eventdev.h>\n+\n+#include \"cpt_pmd_logs.h\"\n+#include \"cpt_ucode.h\"\n+\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_hw_access.h\"\n+#include \"otx2_cryptodev_ops_helper.h\"\n+#include \"otx2_cryptodev_qp.h\"\n+\n+static inline void\n+otx2_ca_deq_post_process(const struct otx2_cpt_qp *qp,\n+\t\t\t struct rte_crypto_op *cop, uintptr_t *rsp,\n+\t\t\t uint8_t cc)\n+{\n+\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\tif (likely(cc == NO_ERR)) {\n+\t\t\t/* Verify authentication data if required */\n+\t\t\tif (unlikely(rsp[2]))\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n+\t\t\t\t\t\t rsp[3]);\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t} else {\n+\t\t\tif (cc == ERR_GC_ICV_MISCOMPARE)\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t}\n+\n+\t\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\t\tsym_session_clear(otx2_cryptodev_driver_id,\n+\t\t\t\t\t cop->sym->session);\n+\t\t\tmemset(cop->sym->session, 0,\n+\t\t\trte_cryptodev_sym_get_existing_header_session_size(\n+\t\t\t\tcop->sym->session));\n+\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n+\t\t\tcop->sym->session = NULL;\n+\t\t}\n+\t}\n+\n+}\n+\n+static inline uint64_t\n+otx2_handle_crypto_event(uint64_t get_work1)\n+{\n+\tstruct cpt_request_info *req;\n+\tstruct rte_crypto_op *cop;\n+\tuintptr_t *rsp;\n+\tvoid *metabuf;\n+\tuint8_t cc;\n+\n+\treq = (struct cpt_request_info *)(get_work1);\n+\tcc = otx2_cpt_compcode_get(req);\n+\n+\trsp = req->op;\n+\tmetabuf = (void *)rsp[0];\n+\tcop = (void *)rsp[1];\n+\n+\totx2_ca_deq_post_process(req->qp, cop, rsp, cc);\n+\n+\trte_mempool_put(req->qp->meta_info.pool, metabuf);\n+\n+\treturn (uint64_t)(cop);\n+}\n+#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\nindex cde1288d9..3a3ec0fd4 100644\n--- a/drivers/event/octeontx2/otx2_worker.h\n+++ b/drivers/event/octeontx2/otx2_worker.h\n@@ -10,6 +10,7 @@\n \n #include <otx2_common.h>\n #include \"otx2_evdev.h\"\n+#include \"otx2_evdev_crypto_adptr_dp.h\"\n #include \"otx2_ethdev_sec_tx.h\"\n \n /* SSO Operations */\n@@ -66,16 +67,23 @@ otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,\n \tws->cur_tt = event.sched_type;\n \tws->cur_grp = event.queue_id;\n \n-\tif (event.sched_type != SSO_TT_EMPTY &&\n-\t event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n-\t\totx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,\n-\t\t\t\t (uint32_t) event.get_work0, flags, lookup_mem);\n-\t\t/* Extracting tstamp, if PTP enabled*/\n-\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)\n-\t\t\t\t\t + OTX2_SSO_WQE_SG_PTR);\n-\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, ws->tstamp,\n-\t\t\t\t\tflags, (uint64_t *)tstamp_ptr);\n-\t\tget_work1 = mbuf;\n+\tif (event.sched_type != SSO_TT_EMPTY) {\n+\t\tif ((flags & NIX_RX_OFFLOAD_SECURITY_F) &&\n+\t\t (event.event_type == RTE_EVENT_TYPE_CRYPTODEV)) {\n+\t\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n+\t\t} else if (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\totx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,\n+\t\t\t\t\t (uint32_t) event.get_work0, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\t/* Extracting tstamp, if PTP enabled*/\n+\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n+\t\t\t\t\t\t get_work1) +\n+\t\t\t\t\t\t OTX2_SSO_WQE_SG_PTR);\n+\t\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,\n+\t\t\t\t\t\tws->tstamp, flags,\n+\t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n+\t\t\tget_work1 = mbuf;\n+\t\t}\n \t}\n \n \tev->event = event.get_work0;\ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h\nindex 60aa14cca..6e6061821 100644\n--- a/drivers/event/octeontx2/otx2_worker_dual.h\n+++ b/drivers/event/octeontx2/otx2_worker_dual.h\n@@ -10,6 +10,7 @@\n \n #include <otx2_common.h>\n #include \"otx2_evdev.h\"\n+#include \"otx2_evdev_crypto_adptr_dp.h\"\n \n /* SSO Operations */\n static __rte_always_inline uint16_t\n@@ -63,25 +64,32 @@ otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,\n \tws->cur_tt = event.sched_type;\n \tws->cur_grp = event.queue_id;\n \n-\tif (event.sched_type != SSO_TT_EMPTY &&\n-\t event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n-\t\tuint8_t port = event.sub_event_type;\n+\tif (event.sched_type != SSO_TT_EMPTY) {\n+\t\tif ((flags & NIX_RX_OFFLOAD_SECURITY_F) &&\n+\t\t (event.event_type == RTE_EVENT_TYPE_CRYPTODEV)) {\n+\t\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n+\t\t} else if (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = event.sub_event_type;\n \n-\t\tevent.sub_event_type = 0;\n-\t\totx2_wqe_to_mbuf(get_work1, mbuf, port,\n-\t\t\t\t event.flow_id, flags, lookup_mem);\n-\t\t/* Extracting tstamp, if PTP enabled. CGX will prepend the\n-\t\t * timestamp at starting of packet data and it can be derieved\n-\t\t * from WQE 9 dword which corresponds to SG iova.\n-\t\t * rte_pktmbuf_mtod_offset can be used for this purpose but it\n-\t\t * brings down the performance as it reads mbuf->buf_addr which\n-\t\t * is not part of cache in general fast path.\n-\t\t */\n-\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)\n-\t\t\t\t\t + OTX2_SSO_WQE_SG_PTR);\n-\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp, flags,\n-\t\t\t\t\t(uint64_t *)tstamp_ptr);\n-\t\tget_work1 = mbuf;\n+\t\t\tevent.sub_event_type = 0;\n+\t\t\totx2_wqe_to_mbuf(get_work1, mbuf, port,\n+\t\t\t\t\t event.flow_id, flags, lookup_mem);\n+\t\t\t/* Extracting tstamp, if PTP enabled. CGX will prepend\n+\t\t\t * the timestamp at starting of packet data and it can\n+\t\t\t * be derieved from WQE 9 dword which corresponds to SG\n+\t\t\t * iova.\n+\t\t\t * rte_pktmbuf_mtod_offset can be used for this purpose\n+\t\t\t * but it brings down the performance as it reads\n+\t\t\t * mbuf->buf_addr which is not part of cache in general\n+\t\t\t * fast path.\n+\t\t\t */\n+\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n+\t\t\t\t\t\t get_work1) +\n+\t\t\t\t\t\t OTX2_SSO_WQE_SG_PTR);\n+\t\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,\n+\t\t\t\t\t\tflags, (uint64_t *)tstamp_ptr);\n+\t\t\tget_work1 = mbuf;\n+\t\t}\n \t}\n \n \tev->event = event.get_work0;\n", "prefixes": [ "v4", "3/3" ] }