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GET /api/patches/79787/?format=api
{ "id": 79787, "url": "http://patches.dpdk.org/api/patches/79787/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201006150316.5776-5-konstantin.ananyev@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201006150316.5776-5-konstantin.ananyev@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201006150316.5776-5-konstantin.ananyev@intel.com", "date": "2020-10-06T15:03:06", "name": "[v4,04/14] acl: remove library constructor", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "907942fb6b96442fb10d9885621990fd19f4686e", "submitter": { "id": 33, "url": "http://patches.dpdk.org/api/people/33/?format=api", "name": "Ananyev, Konstantin", "email": "konstantin.ananyev@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201006150316.5776-5-konstantin.ananyev@intel.com/mbox/", "series": [ { "id": 12721, "url": "http://patches.dpdk.org/api/series/12721/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12721", "date": "2020-10-06T15:03:02", "name": "acl: introduce AVX512 classify methods", "version": 4, "mbox": "http://patches.dpdk.org/series/12721/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/79787/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/79787/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5752FA04BB;\n\tTue, 6 Oct 2020 17:09:45 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B8FC1BA83;\n\tTue, 6 Oct 2020 17:08:21 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id 5FD4E1BA7F\n for <dev@dpdk.org>; Tue, 6 Oct 2020 17:08:19 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Oct 2020 08:03:39 -0700", "from sivswdev08.ir.intel.com ([10.237.217.47])\n by fmsmga005.fm.intel.com with ESMTP; 06 Oct 2020 08:03:38 -0700" ], "IronPort-SDR": [ "\n 6Yi9jXOQGDXHAveKvEhRzlmfm+a9gyBSrWJQvu3mOe/T4OhvaslPyHwJX1XmIp5Db6j6DvmHPV\n kmwZv15rGtkQ==", "\n sNnpS03ORtwZRedFi8qihyaQWqHq+LWSw3+NWTt9NeYGWRRPHXQRxP3kEdkahFu8hWh0V2nE38\n qIvg1qAR9W3g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9765\"; a=\"143919547\"", "E=Sophos;i=\"5.77,343,1596524400\"; d=\"scan'208\";a=\"143919547\"", "E=Sophos;i=\"5.77,343,1596524400\"; d=\"scan'208\";a=\"518315389\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Konstantin Ananyev <konstantin.ananyev@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, ruifeng.wang@arm.com, vladimir.medvedkin@intel.com,\n Konstantin Ananyev <konstantin.ananyev@intel.com>", "Date": "Tue, 6 Oct 2020 16:03:06 +0100", "Message-Id": "<20201006150316.5776-5-konstantin.ananyev@intel.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20201006150316.5776-1-konstantin.ananyev@intel.com>", "References": "<20201005184526.7465-1-konstantin.ananyev@intel.com>\n <20201006150316.5776-1-konstantin.ananyev@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 04/14] acl: remove library constructor", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Right now ACL library determines best possible (default) classify method\non a given platform with specilal constructor function rte_acl_init().\nThis patch makes the following changes:\n - Move selection of default classify method into a separate private\n function and call it for each ACL context creation (rte_acl_create()).\n - Remove library constructor function\n - Make rte_acl_set_ctx_classify() to check that requested algorithm\n is supported on given platform.\n\nThe purpose of these changes to improve and simplify algorithm selection\nprocess and prepare ACL library to be integrated with:\nadd max SIMD bitwidth to EAL\n(https://patches.dpdk.org/project/dpdk/list/?series=11831)\npatch-set\n\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n lib/librte_acl/rte_acl.c | 166 ++++++++++++++++++++++++++++++---------\n lib/librte_acl/rte_acl.h | 1 +\n 2 files changed, 132 insertions(+), 35 deletions(-)", "diff": "diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex 715b023592..863549a38b 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -79,57 +79,153 @@ static const rte_acl_classify_t classify_fns[] = {\n \t[RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,\n };\n \n-/* by default, use always available scalar code path. */\n-static enum rte_acl_classify_alg rte_acl_default_classify =\n-\tRTE_ACL_CLASSIFY_SCALAR;\n+/*\n+ * Helper function for acl_check_alg.\n+ * Check support for ARM specific classify methods.\n+ */\n+static int\n+acl_check_alg_arm(enum rte_acl_classify_alg alg)\n+{\n+\tif (alg == RTE_ACL_CLASSIFY_NEON) {\n+#if defined(RTE_ARCH_ARM64)\n+\t\treturn 0;\n+#elif defined(RTE_ARCH_ARM)\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))\n+\t\t\treturn 0;\n+\t\treturn -ENOTSUP;\n+#else\n+\t\treturn -ENOTSUP;\n+#endif\n+\t}\n+\n+\treturn -EINVAL;\n+}\n \n-static void\n-rte_acl_set_default_classify(enum rte_acl_classify_alg alg)\n+/*\n+ * Helper function for acl_check_alg.\n+ * Check support for PPC specific classify methods.\n+ */\n+static int\n+acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n {\n-\trte_acl_default_classify = alg;\n+\tif (alg == RTE_ACL_CLASSIFY_ALTIVEC) {\n+#if defined(RTE_ARCH_PPC_64)\n+\t\treturn 0;\n+#else\n+\t\treturn -ENOTSUP;\n+#endif\n+\t}\n+\n+\treturn -EINVAL;\n }\n \n-extern int\n-rte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)\n+/*\n+ * Helper function for acl_check_alg.\n+ * Check support for x86 specific classify methods.\n+ */\n+static int\n+acl_check_alg_x86(enum rte_acl_classify_alg alg)\n {\n-\tif (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))\n-\t\treturn -EINVAL;\n+\tif (alg == RTE_ACL_CLASSIFY_AVX2) {\n+#ifdef CC_AVX2_SUPPORT\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n+\t\t\treturn 0;\n+#endif\n+\t\treturn -ENOTSUP;\n+\t}\n \n-\tctx->alg = alg;\n-\treturn 0;\n+\tif (alg == RTE_ACL_CLASSIFY_SSE) {\n+#ifdef RTE_ARCH_X86\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n+\t\t\treturn 0;\n+#endif\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\treturn -EINVAL;\n }\n \n /*\n- * Select highest available classify method as default one.\n- * Note that CLASSIFY_AVX2 should be set as a default only\n- * if both conditions are met:\n- * at build time compiler supports AVX2 and target cpu supports AVX2.\n+ * Check if input alg is supported by given platform/binary.\n+ * Note that both conditions should be met:\n+ * - at build time compiler supports ISA used by given methods\n+ * - at run time target cpu supports necessary ISA.\n */\n-RTE_INIT(rte_acl_init)\n+static int\n+acl_check_alg(enum rte_acl_classify_alg alg)\n {\n-\tenum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;\n+\tswitch (alg) {\n+\tcase RTE_ACL_CLASSIFY_NEON:\n+\t\treturn acl_check_alg_arm(alg);\n+\tcase RTE_ACL_CLASSIFY_ALTIVEC:\n+\t\treturn acl_check_alg_ppc(alg);\n+\tcase RTE_ACL_CLASSIFY_AVX2:\n+\tcase RTE_ACL_CLASSIFY_SSE:\n+\t\treturn acl_check_alg_x86(alg);\n+\t/* scalar method is supported on all platforms */\n+\tcase RTE_ACL_CLASSIFY_SCALAR:\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n \n-#if defined(RTE_ARCH_ARM64)\n-\talg = RTE_ACL_CLASSIFY_NEON;\n-#elif defined(RTE_ARCH_ARM)\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))\n-\t\talg = RTE_ACL_CLASSIFY_NEON;\n+/*\n+ * Get preferred alg for given platform.\n+ */\n+static enum rte_acl_classify_alg\n+acl_get_best_alg(void)\n+{\n+\t/*\n+\t * array of supported methods for each platform.\n+\t * Note that order is important - from most to less preferable.\n+\t */\n+\tstatic const enum rte_acl_classify_alg alg[] = {\n+#if defined(RTE_ARCH_ARM)\n+\t\tRTE_ACL_CLASSIFY_NEON,\n #elif defined(RTE_ARCH_PPC_64)\n-\talg = RTE_ACL_CLASSIFY_ALTIVEC;\n-#else\n-#ifdef CC_AVX2_SUPPORT\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n-\t\talg = RTE_ACL_CLASSIFY_AVX2;\n-\telse if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n-#else\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n+\t\tRTE_ACL_CLASSIFY_ALTIVEC,\n+#elif defined(RTE_ARCH_X86)\n+\t\tRTE_ACL_CLASSIFY_AVX2,\n+\t\tRTE_ACL_CLASSIFY_SSE,\n #endif\n-\t\talg = RTE_ACL_CLASSIFY_SSE;\n+\t\tRTE_ACL_CLASSIFY_SCALAR,\n+\t};\n \n-#endif\n-\trte_acl_set_default_classify(alg);\n+\tuint32_t i;\n+\n+\t/* find best possible alg */\n+\tfor (i = 0; i != RTE_DIM(alg) && acl_check_alg(alg[i]) != 0; i++)\n+\t\t;\n+\n+\t/* we always have to find something suitable */\n+\tRTE_VERIFY(i != RTE_DIM(alg));\n+\treturn alg[i];\n+}\n+\n+extern int\n+rte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)\n+{\n+\tint32_t rc;\n+\n+\t/* formal parameters check */\n+\tif (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))\n+\t\treturn -EINVAL;\n+\n+\t/* user asked us to select the *best* one */\n+\tif (alg == RTE_ACL_CLASSIFY_DEFAULT)\n+\t\talg = acl_get_best_alg();\n+\n+\t/* check that given alg is supported */\n+\trc = acl_check_alg(alg);\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\tctx->alg = alg;\n+\treturn 0;\n }\n \n+\n int\n rte_acl_classify_alg(const struct rte_acl_ctx *ctx, const uint8_t **data,\n \tuint32_t *results, uint32_t num, uint32_t categories,\n@@ -262,7 +358,7 @@ rte_acl_create(const struct rte_acl_param *param)\n \t\tctx->max_rules = param->max_rule_num;\n \t\tctx->rule_sz = param->rule_size;\n \t\tctx->socket_id = param->socket_id;\n-\t\tctx->alg = rte_acl_default_classify;\n+\t\tctx->alg = acl_get_best_alg();\n \t\tstrlcpy(ctx->name, param->name, sizeof(ctx->name));\n \n \t\tte->data = (void *) ctx;\ndiff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h\nindex b814423a63..3999f15ded 100644\n--- a/lib/librte_acl/rte_acl.h\n+++ b/lib/librte_acl/rte_acl.h\n@@ -329,6 +329,7 @@ rte_acl_classify_alg(const struct rte_acl_ctx *ctx,\n * existing algorithm, and that it could be run on the given CPU.\n * @return\n * - -EINVAL if the parameters are invalid.\n+ * - -ENOTSUP requested algorithm is not supported by given platform.\n * - Zero if operation completed successfully.\n */\n extern int\n", "prefixes": [ "v4", "04/14" ] }